Analog Integrated Circuits and Signal Processing 

Abstract: Afully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large-and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ inv is controlled by the voltage differenceV P — Vch whereV ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV P is defined as the particular value of Vch, such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV P —V S andV P —V D Using the charge sheet model with the assumption of constant doping in the channel, the drain currentIDis derived and expressed as the difference between a forward componentI F and a reverse componentI R. Each of these is proportional to a function ofV P —V S respectivelyV P —V D through a specific currentI S This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.

Abstract: An equivalent circuit for the translinear implementation of the second generation current conveyors with positive or negative current transfer is given. This circuit takes into account the various parasitic elements of the conveyor which induce frequency limitations (gain values, poles of the transfers, and parasitic impedances). The methods allowing the determination of the values for these parasitic elements are indicated and discussed. The effect of each element on the frequency responses of the circuits using the conveyors are studied in every detail. The frequency behavior of two circuits are analyzed as examples: a voltage amplifier without feedback and two configurations for a second order biquad filter operating in current-mode. All the theoretical results of the analysis are well confirmed from SPICE simulations.

Abstract: The linear range of approximately ±75 mV of traditional subthreshold transconductance amplifiers is too small for certain applications—for example, for filters in electronic cochleas, where it is desirable to handle loud sounds without distortion and to have a large dynamic range. We describe a transconductance amplifier designed for low-power (< 1 µW) subthreshold operation with a wide input linear range. We obtain wide linear range by widening the tanh, or decreasing the ratio of transconductance to bias current, by a combination of four techniques. First, the well terminals of the input differential-pair transistors are used as the amplifier inputs. Then, feedback techniques known as source degeneration (a common technique) and gate degeneration (a new technique) provide further improvements. Finally, a novel bump-linearization technique extends the linear range even further. We present signal-flow diagrams for speedy analysis of such circuit techniques. Our transconductance reduction is achieved in a compact 13-transistor circuit without degrading other characteristics such as dc-input operating range. In a standard 2 µm process, we were able to obtain a linear range of ±1.7V. Using our wide-linear-range amplifier and a capacitor, we construct a follower–integrator with an experimental dynamic range of 65 dB. We show that, if the amplifier‘s noise is predominantly thermal, then an increase in its linear range increases the follower–integrator‘s dynamic range. If the amplifier‘s noise is predominantly 1/f, then an increase in its linear range has no effect on the follower–integrator‘s dynamic range. To preserve follower–integrator bandwidth, power consumption increases proportionately with an increase in the amplifier‘s linear range. We also present data for changes in the subthreshold exponential parameter with current level and with gate-to-bulk voltage that should be of interest to all low-power designers. We have described the use of our amplifier in a silicon cochlea [1, 2].

Abstract: In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI “translinear system” with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.

Abstract: A novel building block is described, termed FCS (floating current source), which may serve as class A output stage for CFAs (current-mode feedback amplifiers). It is capable of driving a grounded load with a bipolar signal, and yields a feedback current equal to the output current over a wide frequency range. Its possible range of application covers MOSFET amplifiers employed in analog signal processing and current-operated control systems. An internal interconnection converts the FCS into a CCII-. Another novel CCII- configuration employs a push-pull folded cascode and may serve as noninverting input stage for a standard amplifier configuration. Finally, a feedback-stabilized CCII- and a CFA are described, both employing the FCS as output stage.