Showing papers in "Analog Integrated Circuits and Signal Processing in 2010"

Analog circuit design optimization through the particle swarm optimization technique

Abstract: This paper details the Particle Swarm Optimization (PSO) technique for the optimal design of analog circuits. It is shown the practical suitability of PSO to solve both mono-objective and multiobjective discrete optimization problems. Two application examples are presented: maximizing the voltage gain of a low noise amplifier for the UMTS standard and computing the Pareto front of a bi-objective problem, maximizing the high current cut off frequency and minimizing the parasitic input resistance of a second generation current conveyor. The aptness of PSO to optimize difficult circuit problems, in terms of numbers of parameters and constraints, is shown.

0.8 V bulk-driven operational amplifier

Abstract: A low-voltage bulk-driven CMOS operational amplifier is proposed in this paper. The inherent small transconductance of the bulk-driven devices is enlarged using a positive feedback, improving also the noise performance. The amplifier is designed using standard 0.18 μm n-well CMOS process. Although the amplifier is optimized for 0.8 V supply voltage, it is also capable to operate under supply voltage of 0.7 V. The amplifier consumes 130 μΑ, performing 56 dB open-loop gain, 154 nV/√Hz input-referred spot noise at 100 kHz, 80 dB CMRR at 100 kHz and IIP3 equal to −4.7 dBV.

First-order voltage-mode all-pass filter employing one active element and one grounded capacitor

Abstract: A new circuit topology of first-order voltage-mode all-pass filter providing high-input and low-output impedances is described. The filter consists of only one grounded capacitor and one active element, namely VD-DIBA (Voltage Differencing-Differential Input Buffered Amplifier), with the possibility of electronically tuning the natural frequency. The filter is assembled from commercial integrated circuits, and the frequency responses measured are compared with the theoretical characteristics.

On a multivibrator that employs a fractional capacitor

Abstract: The simple free running multivibrator built around a single fractional capacitor is examined in this letter. Equations for the oscillation frequency of the multivibrator are derived taking into account the positive feedback factor around the multivibrator. We show that the use of the fractional capacitance allows the multivibrator to have very high frequencies of oscillation for reasonable time constants used. PSPICE simulation and experimental results demonstrate the analysis with an approximation to a fractional capacitor that yields a result, which is at least 1000 times in frequency compared to if a normal capacitor of the same value was employed.

Sub 1 V CMOS bandgap reference design techniques: a survey

Abstract: This paper presents a review of constraints, limitation factors and challenges to implement sub 1 V CMOS bandgap voltage reference (BVR) circuits in today's and future submicron technology. Moreover, we provide insight analysis of BVR circuit architectures a designer can relay upon when building CMOS voltage reference.

Electronically tunable multiphase sinusoidal oscillator using translinear current conveyors

Abstract: A new electronically tunable current-mode multiphase sinusoidal oscillator based on translinear current conveyors is presented. The proposed oscillator circuit, which employs only one translinear current conveyor and one grounded capacitor for each phase, can generate arbitrary N output current equal-amplitude signals that are equally spaced in phase (N being even or odd), all at high output impedance terminals. The frequency of oscillation and the condition of oscillation can be controlled electronically and independently through the bias current of the translinear current conveyor. The proposed structure also has simple circuitry, low-component count, and is highly suitable for integrated circuit implementation. The theoretical results were verified by PSPICE simulation. In addition, the modification of the N sinusoidal oscillators to construct a programmable multiphase oscillator is also discussed.

New grounded simulated inductance circuit using a single PFTFN

Abstract: A new single-PFTFN based lossless grounded inductance simulation circuit has been presented. The proposed circuit employs a single PFTFN along with four resistors and a single capacitor and realises a lossless grounded inductance subject to the fulfillment of only one realization condition. Some sample results of circuits realized with the new simulated inductor using existing CMOS FTFN implementation have been given to demonstrate the workability of the new circuit.

Lossless inductance simulation and voltage-mode universal biquadratic filter with one input and five outputs using DVCCs

Abstract: A lossless floating inductance has been simulated using two differential voltage current conveyors, two resistors and one grounded capacitor. The proposed floating inductance needs not component matching condition. Base on the proposed floating inductance as building block, a new voltage-mode universal biquadratic filter with one input and five outputs can be obtained. The proposed universal biquad uses two differential voltage current conveyors, three resistors and two grounded capacitors. All standard filter functions; highpass, bandpass, lowpass, notch and allpass can be obtained, simultaneously, without changing the passive elements. The proposed universal biquad has the features of using only grounded capacitors and orthogonal controllable of resonance angular frequency and quality factor.

Symbolic analysis of analog circuits containing voltage mirrors and current mirrors

Abstract: The pathological elements voltage mirror (VM) and current mirror (CM) have shown advantages in analog behavioral modeling and circuit synthesis, where many nullor-mirror equivalences have been explored to design and to transform voltage-mode circuits to current-mode ones and viceversa. However, both the VM and CM have not equivalents to perform automatic symbolic circuit analysis. In this manner, we introduce nullor-equivalents for these pathological elements allowing to include parasitics and to perform only symbolic nodal analysis. The nullor-equivalent of the CM is extended to provide multiple-outpus (MO-CM). Finally, two active filters containing VMs, CMs and MO-CMs are analysed to show the usefulness of the models.

An analog drive loop for a capacitive MEMS gyroscope

Abstract: The linear model and the design of an analog drive loop for the drive (primary) resonator in a capacitive gyroscope are presented. Four different types of gain control topologies are compared and analyzed with both P- and PI-type controllers. The simple model proposed in the paper allows the small signal properties of the loop to be predicted. The theoretical models based on the small signal analysis are compared to the simulated and measured results. A proportional amplitude controller, together with the rest of the drive loop, is implemented using a high-voltage 0.35-μm CMOS technology and a nominal supply of 3 V. Clock generation using a PLL and the drive loop signal as the reference are also discussed in the paper.

Generation of current conveyor based oscillators using nodal admittance matrix expansion

Abstract: A new approach in the systematic synthesis of current conveyor based active RC canonic oscillators is given. The synthesis procedure is based on the generalized systematic synthesis framework using admittance matrix expansion. The resulting derived oscillators include many novel oscillators, using various types of current conveyors and inverting current conveyors. The oscillators considered in this paper uses the minimum number of passive elements namely two capacitors and three resistors necessary to have independent control on the condition of oscillation and on the frequency of oscillation. The generated oscillators employ two grounded capacitors and have the advantage of their ability to absorb parasitic element effects. Three classes are considered in this paper, class I oscillators have a common node between one of the capacitors and one of the two grounded resistors. Class II oscillators have a common node between one of the capacitors and the floating resistor. Class III has all three resistors being grounded and one of them shares a node with one of the capacitors. It should be noted that this is the first paper in the literature to use nodal admittance matrix expansion in the generation of current conveyor oscillators. Spice simulation results are included to support the theory. The proposed method can be generalized to other active devices.

Transformation of oscillators using Op Amps, unity gain cells and CFOA

Abstract: The realization of two integrator loop oscillators using Operational Amplifiers (Op Amps) is reviewed and a new additional circuit to provide independent control on the oscillation condition is proposed. Four new grounded capacitor oscillator circuits using unity gain cells and having independent control on the condition of oscillation and on the frequency of oscillation are introduced. The link between the Op Amp based two integrator loop oscillators and three Current Feedback Operational Amplifier (CFOA) based oscillators is detected and clearly explained. This paper serves also as a tutorial paper in introducing the subject of second order two integrator loop oscillators using state variable matrix equation and Nodal Admittance Matrix (NAM) equation.

Voltage-mode quadrature sinusoidal oscillator with current tunable properties

Abstract: This letter presents a realization of voltage-mode quadrature sinusoidal oscillator with independent current tunable frequency of oscillation. The circuit uses a single differential voltage current conveyor transconductance amplifier (DVCCTA) as the active building block and four all grounded passive elements. PSPICE simulation results have been included to verify the theoretical results.

Discussion on Barkhausen and Nyquist stability criteria

Abstract: Most textbooks on analog circuits and signal processing describe the Barkhausen criterion pertaining to the determination of sinusoidal oscillations in a closed-loop system. On the other hand, the Nyquist stability criterion is well known, as discussed in most textbooks on control systems. Recently, some examples in which the Barkhausen criterion fails to produce the correct condition for startup of oscillations have been reported. In the present paper, an explanation of oscillation startup based on the Nyquist stability criterion is given and the close relationship between the Barkhausen and the Nyquist criteria highlighted. It is shown that the Nyquist criterion (which is a rigorous technique) is a more robust approach than the Barkhausen criterion concerning the determination of sinusoidal oscillations in a closed-loop system and that the Barkhausen criterion (whenever it yields the correct result) is subsumed by the Nyquist criterion as a special case. The textbooks usually describe the Barkhausen criterion as a separate topic, i.e., do not discuss the relationship of this criterion with the Nyquist criterion. It is, therefore, felt that the present discussion will go a long way to put the subject in a broader perspective.

A high-speed differential CMOS Schmitt trigger with regenerative current feedback and adjustable hysteresis

Abstract: This paper presents a brief overview of Schmitt triggers and proposes a new differential current-feedback Schmitt trigger. The hysteresis of the proposed Schmitt trigger is generated using regenerative current feedback and can be adjusted by varying the current of the regenerative feedback network. The center of the hysteresis can also be adjusted by varying the common-mode input voltage. The proposed Schmitt trigger has the characteristics of current-mode circuits, making it particularly attractive for low-voltage high-speed applications. The proposed Schmitt trigger has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results are presented.

Single CCII-based voltage-mode universal filter

Abstract: A new voltage-mode universal biquad filter is presented which can realize all the five standard filter functions namely lowpass, bandpass, highpass, notch, and allpass employing only one CCII as active element. The new circuit is composed of only one CCII, two capacitors, and three resistors, and realizes five generic filter signals without any inverting-type voltage input signals. This is unlike biquad reported by filter structures which employs more active components and needed an inverting-type voltage input signal to realize allpass signal.

Differential CMOS Schmitt trigger with tunable hysteresis

Abstract: This letter presents a new differential Schmitt trigger with tunable hysteresis. The hysteresis is generated using a cross-coupled inverter pair. The amount of hysteresis can be adjusted by varying the current of the symmetrical load. The proposed Schmitt trigger has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the triggering voltage of the Schmitt trigger can be adjusted from 0.95 to 1.35 V approximately.

Voltage mode universal filters employing single FDCCII

Abstract: In this paper, four new voltage-mode universal biquad filters configuration are proposed. First of two circuits proposed high-input impedance universal filter with single-input and three-outputs, which can simultaneously realize voltage mode low-pass, band-pass and high-pass filter responses employing all grounded passive components. The third proposed universal filter three-input and single-output, which also can realize all the standard filter functions. The fourth circuit proposed universal filter with three-input and five-outputs, which can be used as either a three-inputs single-output or a two-inputs five-outputs universal filters. It can realize all five different generic filtering signals: low-pass, band-pass, high-pass, band-stop and all-pass. Simulation results are given to confirm the theoretical analysis. The proposed biquad filters are simulated using TSMC CMOS 0.35 μm technology.

A 0.8-V 816-nW delta---sigma modulator for low-power biomedical applications

Abstract: This letter discusses the implementation of a low-voltage, low-power delta---sigma modulator as a sensing stage for biomedical applications. A distributed feed-forward structure and bulk-driven operational transconductance amplifier are used in order to achieve efficient operation at a supply voltage of 0.8 V. Instead of conventional low-voltage amplifier architectures, our design uses folded-cascode amplifiers, although they are not used in most low-voltage circuits. A wide input swing is achieved by using the bulk-driven approach, and the drawback of the limited voltage swing of the cascoded output stage is overcome by the distributed feed-forward modulator. The designed modulator has a dynamic range of 49 dB at a 0.8-V supply voltage and consumes only 816 nW of power for the 250-Hz bandwidth. The core chip size of the modulator is 1000 μm × 500 μm by using the 0.18-μm standard CMOS process.

Design of a CMOS low-power and low-voltage four-quadrant analog multiplier

Abstract: A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications.

FEM modelling and experimental characterization of microbeams in presence of residual stress

Abstract: Out-of-plane bending tests are here used to experimentally validate some numerical models of microbeams actuated by the electric field. Out-of-plane bending microcantilevers and clamped–clamped microbeams often suffer the presence of residual strain and stress, respectively, which affect their static and dynamic behaviour and pull-in voltage. In case of microcantilever an accurate modelling has to include the effect of an initial curvature due to microfabrication process, while in double clamped microbeams constraints may impose a pre-loading caused by a tensile stress. So-called geometrical nonlinearity sometimes occurs, when microcantilever exhibits large displacement, or because of the mechanical coupling between axial and flexural behaviours in double clamped microbeams. Modelling this kind of nonlinearity is an additional goal of this study. Experiments demonstrated a good agreement with results of FEM approaches proposed. In the case of microbridges numerical models are used to identify the residual stress. A reverse analysis is implemented, the axial pre-stress is calculated by means of the measured pull-in voltage.

A technique for improving gain and noise figure of common-gate wideband LNAs

Abstract: A technique for improving gain and noise performance of differential wideband common-gate low noise amplifiers is presented. It is based on current bleeding and noise cancellation. An amplifier employing the technique has been designed and simulated in a 90 nm standard CMOS process using a 1 V supply. It has been compared to designs using both basic and cross-coupled common-gate topologies. Simulation results confirm the improvements in gain and noise figure, yielding a superior figure of merit for the new technique.

An ultra-low power successive approximation A/D converter with time---domain comparator

Abstract: This paper presents an ultra-low power successive approximation analog-to-digital converter. An improved implementation of the binary weighted capacitors array and a novel comparator that operates in the time instead of the voltage domain are effective and power efficient. The circuit, fabricated in a conventional 0.18-μm CMOS technology, achieves a sampling rate of 100 kS/s and an effective number of bit of 9.4. Using a 1-V supply voltage, the achieved power consumption is 3.8 μW, leading to a Figure of Merit as low as 56 fJ/conversion-level.

A 3 V 110 μW 3.1 ppm/°C curvature-compensated CMOS bandgap reference

Abstract: This paper presents design of a high-precision curvature-compensated bandgap reference (BGR) circuit implemented in a 0.35 μm CMOS technology. The circuit delivers an output voltage of 1.09 V and achieves the lowest reported temperature coefficient of ~3.1 ppm/°C over a wide temperature range of [?20°C/+100°C] after trimming, a power supply rejection ratio of ?80 dB at 1 kHz and an output noise level of 1.43 μV $$ \sqrt {\text{Hz}} $$ at 1 kHz. The BGR circuit consumes a very low current of 37 μA at 3 V and works for a power supply down to 1.5 V. The BGR circuit has a die size of 980 μm × 830 μm.

A novel phase shifter using two NMOS transistors and passive elements

Abstract: In this paper, a new voltage-mode configuration for realizing a first-order phase shifter is suggested. The proposed phase shifter contains low number of components, i.e. two n-type metal-oxide semiconductor field effect transistors (NMOS transistors) both operating in saturation region, a grounded capacitor and three resistors. The presented circuit can be equipped with electronic tunability by using externally controllable electronic resistor. Computer simulation results, using SPICE program, are given to demonstrate the performance of the proposed phase shifter.

Identification of a class of two CFOA-based sinusoidal RC oscillators

Abstract: Using a unified representation for a class of the two current-feedback operational amplifier (CFOA) sinusoidal oscillators, new circuits of this type can be systematically discovered. A catalogue of two circuit structures, each structure realizing 18 oscillator circuits, is presented. Moreover, using the RC:CR transformation, additional 18 oscillator circuits can be obtained from each structure. A third structure realizing additional two oscillator circuits is also presented. Some of the circuits enjoy one or more of the following attractive features: use of grounded capacitors, feasibility of absorbing the parasitic components of the CFOAs, availability of a buffered output voltage and orthogonal tuning of the frequency and the startup condition of oscillation. Moreover, it is shown that the use of the Barkhausen criterion for the determination of the startup condition of oscillation and the frequency of oscillation yields inaccurate results with relatively large errors depending on the selected component values. Furthermore, it is shown that using the roots of the characteristic equation of a specific oscillator structure will result in a startup condition that cannot be adjusted without disturbing the frequency of oscillation.

A 200-mA, 93% peak power efficiency, single-inductor, dual-output DC---DC buck converter

Abstract: A single-inductor dual-output (SIDO) DC---DC buck converter is presented. The circuit uses only one (external) inductor to provide two independent output voltages ranging from 1.2 V to the power supply (2.6---5 V) with a maximum total output current of 200 mA. The proposed converter has been fabricated in a 0.35-μm p-substrate CMOS technology. Measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved. An automatic substrate bias switch technique, that cancels the body effect of the p-channel output power transistors, improves the converter power efficiency performance.

Low voltage low power CMOS current differencing buffered amplifier

Abstract: The major goal of this work is to present a new CMOS realization for the current differencing buffered amplifier (CDBA). A design technique based on flipped voltage follower current sources is preferred to obtain a high performance CDBA. The proposed circuit can operate with the minimum supply voltages of ±0.6 V. It also consumes less power than its counterparts that have been reported so far. Moreover, the proposed CDBA has good voltage and current gain accuracies. For the simulations, UMC 0.18 μm CMOS process is used. The performance of the CDBA is verified with HSPICE. Finally, a second-order, allpass/notch filter configuration is proposed to show the performance and usefulness of the circuit. The results from HSPICE simulations are in remarkable agreement with the expected ones.

Design techniques for ASK demodulators of passive wireless microsystems: a state-of-the-art review

Abstract: ASK demodulators are widely used in passive wireless microsystems due to their simple design and low power consumption. Although a large number of ASK demodulators emerged recently, an in-depth examination of the pros and cons and design constraints of these ASK demodulators is not available. This paper presents a comprehensive in-depth review of the design techniques for ASK demodulators of passive wireless microsystems. The classification of ASK demodulators of passive wireless microsystems is introduced. We show that ASK demodulators of passive wireless microsystems can be classified into three categories on the basis of the information carriers: voltage-mode, current-mode, and mixed-mode. The design constraints of these ASK demodulators differ fundamentally. Challenges encountered in design of ASK modulators for passive wireless microsystems are examined in detail. The configurations of voltage-mode, current-mode and mixed-mode ASK demodulators for passive wireless microsystems emerged recently are studied and their circuit implementations are examined in detail. The performance of these ASK demodulators such as date rates, carrier frequencies, and modulation index is compared.

PLL performance comparison with application to spread spectrum clock generator design

Abstract: This paper presents performance, power and area comparisons of LC vs. Ring VCO-based PLL designs in order to determine the best option for high-speed spread spectrum clock generator (SSCG) designs. Analytical performance, power and area comparisons of LC versus Ring VCO-based PLL designs demonstrate that a Ring VCO can be used to meet the requirements of SATA and SAS applications at rates up to 6 Gbps. The designed SSCG operating frequency range is 2---4.25 GHz with RMS RJ jitter <1.3 and <1.5 pS for non-SSC and SSC modes, respectively, at 3 GHz. The measured EMI reduction is 18 and 21 dB for 2,300 and 4,600 ppm SSC, respectively, also at 3 GHz.