Showing papers in "Analog Integrated Circuits and Signal Processing in 2020"

R-peak detection based chaos analysis of ECG signal

Abstract: Electrocardiography (ECG) is a non-invasive test that is used for recording contraction and relaxation activities of the heart by using an electrocardiogram. Early detection of abnormalities of the heart through ECG is essential for reducing the prevalence of casualties due to cardiac arrests worldwide. In this study, physioNet ECG records have been considered for analysis. During recording, ECG signal is also affected by various noises, where analog filters fail due to the effect of temperature and drift, and digital filters fail due to inappropriate selection of passband and gain parameters. For adequate and frequent usage in the medical field, it demands correct and precise R-peak (QRS-complex) detection; which requires an appropriate combination of pre-processing, feature extraction and detection techniques. Therefore, independent component analysis (ICA) is used in the pre-processing stage due to nonlinear nature of the ECG signals and chaos analysis is applied for feature extraction for different ECG databases. The ICA method separates an individual signal from mixed signals by assuming that the original underlying source signals are mutually independently distributed. Chaos analysis examines the irregular attitude of the system and fits it into deterministic equations of motion. Chaos analysis is implemented by plotting different attractors against various time delay dimensions. R-peak detection is well known to be useful in diagnosing cardiac diseases. The R-peaks are detected using principal component analysis (PCA) which outperforms the existing state-of-the-art techniques.

Design, FPGA implementation and statistical analysis of chaos-ring based dual entropy core true random number generator

Abstract: In this paper, a novel chaos-ring based dual entropy core TRNG architecture on FPGA with high operating frequency and high throughput has been performed and presented. The design of dual entropy core TRNG has been generated by uniting the chaotic system-based RNG and the RO-based RNG structures on FPGA. The chaotic oscillator structure as the basic entropy source has been implemented in VHDL using Euler numerical algorithm in 32-bit IQ-Math fixed point number standart on FPGA. The designed chaotic oscillator has been synthesized for the FPGA chip and the statistics related to chip resource consumption and clock frequencies of the units have been presented. The RO-based RNG structure has been designed as the second entropy source. Chaos-ring based dual entropy core novel TRNG unit have been created by combining of these two FPGA-based structures in the XOR function used at the post processing unit. The throughput of the designed dual entropy core TRNG unit ranges 464 Mbps. The output bit streams obtained from FPGA-based novel TRNG have been subjected to NIST 800-22 test suites.

Design of 4 × 4 antenna array for breast cancer detection

Abstract: In the present world, malignant growth in bosom is the commonly prevailing disease among women. Early bosom diagnosis and treatment are compulsory to diminish the death rates of bosom malignancy. Here, a dielectric differentiation is being detected among typical and malignant growth tissues, having applied ideal scope of frequencies. Winding radio wires becomes the most appropriate in this application due to its double polarization property where an adaptable substrate fulfils the wearable prerequisites. In this paper, the Winding Reception Apparatus is structured as a 4 × 4 exhibit with a goal that covers the greatest diameter of the bosom. The radio wire parameters such as expansion, direction and return misfortune are upgraded to get acceptable resistance, coordination and great reaction over the necessary recurrence. The receiving wires at the thickness 0.035 mm and with length, width of 19 mm and 15 mm are planned on an adaptable FR-4 substrate with a thickness of 0.4 mm. The proposed receiving wire cluster is structured and recreated in ADS programming for the recurrence scope of 2–4 GHz. In this regard, the obtained outcomes are contrasted and the foreordained qualities and nearness or non-appearance of the disease are distinguished.

Design and implementation of high performance and area efficient square architecture using Vedic Mathematics

Abstract: Now a days, an efficient arithmetic operations are important to accomplish the high performance. In every one of these applications, multiplier is an important arithmetic operation. Usually multipliers are utilized to evaluate the square operand. A square operation is faster than a multiplication. This paper proposes a high performance and area efficient square architecture using Anurupya Sutra of Vedic Mathematics. The proposed method is efficient method, which divided the large magnitude number into smaller magnitude numbers and concatenated smaller magnitude numbers. The proposed architecture is synthesized and simulated using Vivado design suite 2018.3 and implemented on Kintex-7 FPGA board. The results revealed a high performance and area efficient compared to a well-known prior art multipliers.

An enhanced fuzzy controller based on improved genetic algorithm for speed control of DC motors

Abstract: Because of being imprecision and existence of uncertainty in input variables to fuzzy systems, and also their easy implementation, fuzzy controllers are introduced as one of useful optimization tools in industry especially in DC motors. Given to the growth of controller systems usages in industry, use of optimization methods has been noticed in the recent years; so that improve precision and performance of these systems. In addition to making improvement in their performance, real time implementation, less energy spending in comparison with other tools, having high speed in mathematical computation and decreasing hardware resources consumption are some serious challenges in this terrain. To optimize fuzzy controllers’ performance, various methods have been proposed by the researchers. This paper firstly focuses on applying improved Genetic Algorithm in regulating optimum parameters of fuzzy controller to rise convergence speed and accuracy. Secondly, a pipeline technique with specific strategies of diminishing required bit width for fuzzy controllers is provided to achieve maximum efficiency in fuzzy controller implementation. In general, it can be seen that optimized fuzzy controller in this paper has precise performance, high convergence speed and such advantages in efficient hardware implementation in comparison with other fuzzy controllers.

A novel secure chaos-based pseudo random number generator based on ANN-based chaotic and ring oscillator: design and its FPGA implementation

Abstract: This paper presents a novel, real time, high speed and robust chaos-based pseudo random number generator (PRNG) design using the structures of artificial neural network (ANN)-based 2D chaotic oscillator and ring oscillator. In this study, four different robust PRNGs have been implemented using four different approaches (TS-55, Elliott-93, Elliott-2, Cordic-LUT) of TanSig activation functions (TSAF) that have been used in the design of ANN-based 2D chaotic oscillators. The designs have been coded in VHDL using IEEE-754–1985 number standard. The PRNGs have been synthesized for Virtex-6 FPGA chip using Xilinx ISE Design Tools. After Place&Route operation, FPGA chip statistics and maximum operating frequencies have been presented. The maximum operating frequencies of the proposed PRNGs range between 184 and 241 MHz. The 1 Mbit of bit streams generated by PRNGs have been subjected to NIST-800–22 randomness tests. Among 4 different proposed PRNGs, the proposed PRNGs that designed using the Elliott-93 and Cordic-LUT approaches have successfully passed all NIST-800–22 tests and have a bit production rate of 241 Mbps. The proposed secure hybrid chaos-based PRNG structures were compared with similar studies conducted in the literature in recent years. According to the results, the proposed FPGA-based secure new chaotic PRNG structures are useful in cryptographic applications.

Simple charge controlled floating memcapacitor emulator using DXCCDITA

Abstract: This research article introduces generalized design procedure for incremental/decremental memcapacitor using analog active device that brings a charge controlled floating memcapacitor emulator. The demonstration of generalized model using Dual X current conveyor differential input transconductance amplifier (DXCCDITA) as an analog active device comes with grounded capacitor and single resistor. The important features of proposed memcapacitor emulator in comparison with other emulators are the absence of mutator and multiplier circuits that causes less design complexity, CMOS compatible circuits, high frequency operation and few more. The switching operation incorporated in proposed memcapacitor model provides incremental and decremental mode of operation to control the state of memcapacitor for real time application. The CMOS implementation of DXCCDITA uses 0.18 µm CMOS technology parameter for the design verification. The performance of the memcapacitor is verified using PSPICE simulation and the observation validates the synchronization of theoretical perspective. An adaptive learning circuit is examined as an application with the proposed memcapacitor model that validates the usage of proposed model.

A 1.1 μW biopotential amplifier based on bulk-driven quasi-floating gate technique with extremely low-value of offset voltage

Abstract: Biopotential amplifier (BPA) remains one of the most crucial blocks for the successful implementation of any of the biomedical systems. However, design of a BPA remains challenging owing to most of the topologies reported in literature displaying high values of noise, consuming high value of power and working in limited range of bandwidth. Thus, circuit topologies capable of providing an optimum and an acceptable combination of these parameters remains a topic of immense interest among researchers. We in this paper, report the results of a BPA designed using Bulk-Driven Quasi-Floating Gate (BDQFG) technique with a special focus on the effect of variation in the values of biasing resistor (Rlarge). Results obtained through mathematical modelling and analysis of the circuit have been verified by conducting simulations in Cadence Analog Design Environment using standard 0.18 µm technology. Circuit design has been optimized for least values of power consumption of the order of 1.1 µW, noise (≈ 3.15 µVRMS), mid-band gain of 39.9 dB (from 0.266 Hz to f-3dB of 2.8 kHz), offset voltage of 455 μV and phase margin of 65.83°.

A novel modified U-shaped microstrip antenna for super wide band (SWB) applications

Abstract: In this work, a novel wideband microstrip modified slotted U-shaped printed monopole antenna operating from 3 to 20 GHz for super-wideband applications is proposed. To have an effect on the enhancement of bandwidth and to get better impedance matching over the frequency band, three modifications are introduced, the first one is to print two symmetric triangular shaped slots in the radiating element and the second one is to modify the partial rectangular ground plane to be defected ground plane by slotting three triangular structures. The third modification is to embed a circular slot in the center of the patch for integrating the entire FCC band (3.1–10.6 GHz) in the super wide band antenna. Both CST Microwave Studio and Ansoft HFSS 3-D EM solver were used for the simulation analysis of antennas while measurements after fabrication are performed by applying ZVB 20—vector network analyzer 20 MHz–20 GHz. The average maximum gain of the antenna is 5.72 dB with good radiation patterns. The antennas have only been measured up to 20 GHz (the upper frequency limit of the laboratory vector network analyzer device), simulations results both in CST and HFSS shows satisfactory design’s performance up to 40 GHz. So as this antenna is a candidate to fulfils the future UWB spectrum requirements in a very wide band. A good agreement between the measured and simulated results is achieved in term of return loss in the measured band (up to 20 GHz).

A true random number generator based on a Chua and RO-PUF: design, implementation and statistical analysis

Abstract: Physical unclonable function (PUF) and true random number generator structures are important components used for security in cryptographic systems. Random numbers can be generated for cryptography by using these two components together. In particular, it is desirable that these numbers be unpredictable, non-reproducible and have good statistical properties. This study presents the design of a ring oscillator (RO)-based PUF in a field programmable gate array. Random numbers—obtained from a Chua circuit that exhibits chaotic behavior in 3D and continuous time—were applied to the RO-based PUF challenge inputs. Normalization operations were performed to convert the values in floating number format—obtained by sampling the Chua circuit—into the binary number system. Because modular arithmetic was used in the normalization process, it was simple and fast to obtain the generated numbers to be applied to the challenge inputs. NIST, autocorrelation and scale index tests were used to reveal the usability of the random numbers obtained by the RO-PUF for key generation. The results showed that the statistical properties of the numbers obtained were good and could be used in cryptography.

A single-ended low leakage and low voltage 10T SRAM cell with high yield

Abstract: This paper presents a low leakage power 10T single-ended SRAM cell in the sub-threshold region that improves read, write, and hold stability. While at low voltages, the write-ability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the data-storage node from the read bit line by using only a single transistor. According to Simulations using HSPICE software in 10 nm FinFET technology, the read stability of the proposed cell is approximately 4.8× higher than the conventional 6T at 200 mV. Furthermore, the proposed cell is found to have the lowest static power dissipation, as it tends to be 4% lower than the standard six-transistor cell at this voltage. This study shows that the yield of the proposed cell is higher than 6σ in all operations, and supply voltages down to 200 mV.

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

Abstract: This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

Complex dynamics of a novel 3D autonomous system without linear terms having line of equilibria: coexisting bifurcations and circuit design

Abstract: In recent years, an increasing interest has been devoted to the discovery of new chaotic systems with special properties. In this paper, a novel and singular 3D autonomous system without linear terms is introduced. The singularity of the model is that it is dissipative, possesses rotation symmetry and line of equilibria thus displays complex dynamics. The nonlinear behaviour of the introduced model is studied in terms of bifurcation diagrams, Lyapunov exponent plots, time series, frequency spectra two-parameter diagrams, Lyapunov stability diagrams as well as basins of attraction. Some interesting phenomena are found including, for instance, periodic oscillations, chaotic oscillations, periodic windows, symmetry restoring crises scenario, the coexistence of multiple bifurcations and offset-boosting property while monitoring the system parameters. Coexistence of attractors discovered in this work includes up to six competing attractors with one point attractor. Compared to some few cases previously reported (system without linear terms) (Xu and Wang in Opt Int J Light Electron Opt 125:2526–2530, 2014. https://doi.org/10.1007/s11071-016-3170-x; Kengne in Commun Nonlinear Sci Numer Simul 52:62–76, 2017. https://doi.org/10.1016/j.cnsns.2017.04.017; Mobayen et al. in Int J Syst Sci 49:1–15, 2018. https://doi.org/10.1080/00207721.2017.1410251; Zhang et al. in Int J Non-linear Mech 106:1–12, 2018. https://doi.org/10.1016/j.ijnonlinmec.2018.08.012; Pham et al. in Chaos Solitons Fractals 120:213–221, 2019. https://doi.org/10.1016/j.chaos.2019.02.003), the model considered in this work is the only one in which such type of complex dynamics has already been found. A suitable analog simulator (electronics circuit) is designed and used to support the theoretical analysis.

A TRNG using chaotic entropy pool as a post-processing technique: analysis, design and FPGA implementation

Abstract: In this study, the hardware implementation of a TRNG using an alternative post-processing technique is presented. ROs (ROs) are used as the noise source of TRNG and true randomness is obtained from the jitter. The use of an entropy pool composed of discrete-time chaotic systems (quadratic map, cubic map, Bernoulli shift map and tent map) is proposed as the post-processing technique for TRNG. In the system, the statistical quality of true random numbers with low statistical quality, obtained from jitter, is improved to meet cryptographic qualifications with the proposed post-processing technique. Unlike other known post-processing techniques in the literature, the post-processing technique based on the effective use of chaos is user-controlled, and is dynamically adaptable to the chosen chaotic systems. Thus, optional post-processing inputs fed from a single chaotic system or different combinations of those systems can be obtained for the TRNG. The performance of the proposed TRNG with this post-processing is high. In addition to this, the fact that any random number sequence can be generated with the contribution of more than one chaotic input in the post-processing stage makes both the post-processing and TRNG safer and more secure. In addition to the chaos-based comprehensive security analysis of the post-processing, the statistical validation of the TRNG is made by using test-based tools. As a result, it has been found that the proposed post-processing technique can be used for cryptographic purposes.

Passive–active integrators chaotic oscillator with anti-parallel diodes: analysis and its chaos-based encryption application to protect electrocardiogram signals

Abstract: An autonomous passive–active integrators oscillator with anti-parallel diodes is proposed and analysed in this paper. It consists of anti-parallel diodes and two main blocks: A second-order passive RLC integrator and a first-order active RC integrator. The existence of two Hopf bifurcations is established during the stability analysis of the unique equilibrium point. For a suitable choice of the circuit parameters, the proposed oscillator can generate periodic oscillations, one-scroll, bistable chaotic attractors and antimonotonicity. The electronic circuit realization of the proposed oscillator is carried out to confirm results found during the numerical simulations. A good qualitative agreement is illustrated between the numerical simulations and experimental results. In addition, chaos-based encryption application to protect electrocardiogram (ECG) signals for secure transmission of medical information is performed using the proposed oscillator in chaotic regime. The ECG signals are successfully encrypted and the original ECG signal is successfully decrypted from noisy ECG signals.

Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications

Abstract: Physically unclonable functions (PUF) are digital fingerprints which generate high entropy, temper-resilient keys and/or chip-identifiers for security applications. When considering the miniaturized hardware development for the Internet of Things (IoT), security is of high importance. In this case, PUF designing using SRAM or D flip-flops are quite common but with compromised uniqueness due to the limited silicon area. In this work, a symmetric tri-state D flip-flop based lightweight PUF is proposed with increased uniqueness. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers a uniqueness of 0.4994, which is the highest among all the considered architectures. Compared to the Arbiter PUF the proposed architecture has 0.267 $$\times$$, 0.064 $$\times$$, and 0.043 $$\times$$ less, power, silicon area, and energy per bit, respectively. Similarly, when compared with the Ring Oscillator PUF, the proposed architecture has 0.017 $$\times$$, 0.031 $$\times$$, and 0.0005 $$\times$$ less, power, silicon area, and energy per bit, respectively. Also, unlike other flip-flop based PUF, the proposed one does not require any post-processing block to remove the bias, thus contributes to saving the total implementation area and power of the system. An FPGA implementation is also presented as a proof-of-concept to verify functional correctness. For a better performance comparison among the considered architectures, a novel figure of merit (FOM) considering power, reliability, delay, silicon area, and uniqueness has been proposed, and it is observed that the proposed architecture offers the highest FOM among considered PUF architectures.

A VDTA-based robust electronically tunable memristor emulator circuit

Abstract: In this paper, a fully-integrated tunable grounded memristor emulator circuit based on voltage differencing transconductance amplifier (VDTA) has been proposed. The proposed memristor emulator circuit utilizes two VDTA active building blocks, two grounded resistors, a grounded capacitor and a four-quadrant analog multiplier. The working concept along with the detailed derivation of the mathematical model of the circuit has been discussed numerically and analytically to validate the operation of the proposed emulator. The operations of the proposed emulator circuit, as governed by the established model, have been verified by performing simulations in Cadence Virtuoso at 45 nm technology node. Robustness analyses performed, reveal significant process-variation tolerance at deep sub-micron technology node.

A Schmitt-trigger based low read power 12T SRAM cell

Abstract: In this article, a Schmitt trigger based 12-Transistors(ST12T) static random-access memory (SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52 $$\times$$ and 1.86 $$\times$$ lesser variability in read current and read power respectively as compared to conventional 6T SRAM cell. Further, the write access time/read access time of the proposed topology are improved by $$1.71 \times /1.82 \times$$ as compared to 6T SRAM cell. The read power delay product of proposed ST12T cell is minimum with variation in supply voltage from 0.5 to 1 V when compared with all considered SRAM cells. ST12T SRAM cell also exhibits 26.82% and 8.87% higher read static noise margin and write static noise margin respectively as compared to conventional 6T SRAM cell. This may be attributed to Schmitt trigger design of inverters in core latch of proposed SRAM cell. The proposed bit-cell is free from half select issue and supports bit interleaving format. Authors have used cadence virtuoso tool with Generic Process Design Kit 45 nm technology file to carry out simulation.

A wide linear range CMOS OTA and its application in continuous-time filters

Abstract: In this paper, we have proposed a highly linear Operational Transconductance Amplifier (OTA) with wide linear input range. The proposed OTA utilizes conventional source degeneration with an auxiliary differential pair which increases the linear range significantly by reducing the distortion components. The proposed OTA is targeted for current mode circuit applications including low-frequency continuous time filters. A second-order fully differential filter architecture is also implemented by using this proposed OTA. The linear OTA and the filter are implemented in SCL 180 nm CMOS process technology with 1.8 V supply voltage. The proposed OTA achieves third order harmonic distortion ($${\textit{HD}}_3$$) of $$-\,74.3$$ dB, inter modulation distortion ($${\textit{IM}}_3$$) of $$-\,75.5$$ dB for $$600\,\hbox{mV}_{p-p}$$ differential input with 1 MHz signal frequency and a linear range of 0.9 V for 1% transconductance variation. The filter is designed for 100 kHz cutoff frequency and achieves $${\textit{HD}}_3$$ of $$-\,68.75$$ dB and $${\textit{IM}}_3$$ of $$-\,64.3$$ dB for $$300\,\hbox{mV}_{p-p}$$, 10 kHz input signal.

Energy-efficient magnetic approximate full adder with spin-Hall assistance for signal processing applications

Abstract: As the technology node shrinks to the nanoscale, several challenges such as high power density have become more critical. One of the most effective methods for addressing these problems is utilizing spintronic devices based on magnetic tunnel junction (MTJ). Furthermore, approximate computing is an emerging paradigm for reducing the power consumption and design complexity in some applications, where the computational error is tolerable. In this paper, a novel non-volatile hybrid MTJ/FinFET-based approximate full adder is presented. The proposed design uses the spin Hall effect (SHE) assisted method for writing data on MTJs, which significantly reduces the power consumption and write energy of the MTJ switching as compared to the conventional STT writing method. The proposed design leads to an effective trade-off between efficiency and quality, as it has a simple and energy-efficient structure, while it provides an acceptable quality in applications like approximate image processing. The circuits are simulated using HSPICE with 14 nm FinFET and SHE perpendicular-anisotropy MTJ models. According to the extensive HSPICE and MATLAB simulations, the proposed approach improves power consumption, delay, power-delay product, and energy-delay product on average by 47%, 53%, 75%, and 86%, while achieving relatively better quality metrics as compared to its state-of-the-art counterparts.

A 0.35 V-to-1.0 V synthesizable rail-to-rail dynamic voltage comparator based OAI&AOI logic

Abstract: In this letter, we present a two-stage rail-to-rail fully synthesizable dynamic voltage comparator. To improve the speed and mismatch performance of the NAND&NOR-based synthesizable comparator, we have proposed to replace these logics with OAI&AOI logic gates, respectively. The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage from 350 mV to 1.0 V. The proposed comparator has reduced the delay by 2–11 $$\times$$ , reduced the standard deviation of offset by 1.09–1.39 $$\times$$ , and reduced the power consumption up to 3.80 $$\times$$ compared to the NAND–&NOR-based comparator. Hence, these improvements can be used to further advance the performance of all-digital synthesizable design circuits.

Optimization of thermal aware multilevel routing for 3D IC

Abstract: Due to the technological advancements, the three dimensional Integrated Circuits become the most popular technology. But it has the major drawback of increased time consumption as well power consumption. This happens because of the increased wire length and routing path for connecting the components in chip. Thus it is essential to reduce the wire length for the purpose of enhancing the circuit speed and minimize the power dissipation. But there may be a chance of temperature rise due to the heat generated by the slacked layers which also needs to be reduced. Several traditional approaches have addressed the issues of temperature rise and layer assignment. But the utilization of through-silicon-via is considered. Thus a new stochastic based genetic algorithm is proposed in this work for reducing the thermal estimations. Also the length of wire can be reduced by determining the minimal path so as to connect the components. Both partitioning and routing process takes place in this approach. The performance of the proposed approach is analyzed using ISPD2008 dataset. Also the results of this stochastic based model are compared with the existing algorithm. The superiority of this proposed approach is proved with reduced wire length and temperature estimations.

Design and development of triple-band compact ACS-fed MIMO antenna for 2.4/3.5/5 GHz WLAN/WiMAX applications

Abstract: In this paper, a very small size (20 × 14.75 mm2) triple-band multiple-input multiple-output (MIMO) microstrip patch antenna for WLAN (2.4/5.2/5.8 GHz) and WiMAX (2.5/3.5/5.5 GHz) wireless applications. The goal of this paper is to merge these two wireless standards into a single antenna that can be easily accommodated inside the devices operating in three different frequency ranges. The proposed MIMO antenna consists of an asymmetric coplanar strip (ACS) feedline loaded with an inverted L-shaped slot and a meanderline. The inverted L-shaped slot and the meanderline both having an electrical length 0.5λ, are responsible for the achieving the operating band around 3.5 and 2.4 GHz, respectively whereas the ACS feedline is responsible for the generation of 5 GHz frequency band. The fabricated prototype of the proposed MIMO antenna when tested, shows three distinct frequency bands; I from 2.38 to 3.00 GHz, II from 3.21 to 3.61 GHz and III from 5.02 to 6.18 GHz that covers entire frequency bands of WLAN and WiMAX wireless applications along with different standards of IEEE 802.11 including a/b/j/p/g/n/ac/ax. The peak gain in I, II and III frequency bands is 7.93, 4.23 and 7.57 dBi, respectively. In addition, the diversity performance in terms of envelope correlation coefficient, diversity gain, multiplexing efficiency, total active reflection coefficient, and mean effective gain is also performed for the proposed MIMO antenna.

Convergence rates of the efficient global optimization algorithm for improving the design of analog circuits

Abstract: Optimal sizing of analog circuits is a hard and time-consuming challenge. Nowadays, analog designers are more than ever interested in developing solutions for automating such a task. In order to overcome well-known drawbacks of the conventional equation-based and simulation-based sizing techniques, analog designers are being attracted by the so-called metamodeling techniques and recently have used them for establishing accurate models of circuits’ performances. Metamodels have been associated to optimization routines to maximize circuits’ performances. In this work we deal with the newly proposed efficient global optimization (EGO) algorithm that intrinsically offers both the metamodel generation and the optimization routine. Furthermore, it performs the requested task by using a relatively very small number of performance evaluations. Firstly, we focus on the convergence rates of the EGO technique via twenty benchmark test problems. Then, we use EGO for the optimal design of a couple of analog CMOS circuits. Comparison between EGO performances and those obtained using two surrogate-assisted metaheuristics is provided to show potentialities of the proposed approach. Finally, The case of muti-objective problems is also considered. The multi-objective efficient global optimization algorithm is used for generating Pareto fronts of conflicting perormances of two analog circuits. Obtained results are compared to those of the conventional in-loop optimization technique.

Dynamics, control and symmetry breaking aspects of a modified van der Pol–Duffing oscillator, and its analog circuit implementation

Abstract: This article focuses on the dynamics of a modified van der Pol–Duffing circuit (MVDPD hereafter) (Fotsin and Woafo in Chaos Solitons and Fractals 24(5):1363–1371, 2005) whose symmetry is explicitly broken with the presence an offset term. When ignoring offset terms, the system displays an exact symmetry which is reflected in the location of the equilibrium points, the attractor topologies and the attraction basins shapes as well. In this mode of operation, the system displays typical behaviors such as period doubling sequences; spontaneous symmetry breaking, symmetry recovering, and multistability involving several pairs of mutually symmetric attractors. In the presence of offset terms, the MVDPD circuit is non-symmetric and more complex nonlinear phenomena arise such as parallel bifurcation branches, coexisting multiple (i.e. two, three, four or five) asymmetric attractors, and crises. It should be noted that for each case of multistability discussed in this work, a hidden attractor (period-1 limit cycle) coexists with self-excited others. To the best of our knowledge, the coexistence of five attractors (symmetrical or asymmetrical), one of which is hidden has not yet been reported in the MVDPD circuit and thus deserves dissemination. PSpice simulation investigations based on the implementation of the MVDPD confirm the theoretical predictions.

A low-power low-noise multi-stage transimpedance amplifier for amperometric based blood glucose monitoring systems

Abstract: In this paper, the design of low-noise, low-power transimpedance amplifier (TIA) is presented for a miniaturized amperometric based continuous blood glucose monitoring system for wearable devices. The proposed multi-stage cascode common source transimpedance amplifier circuit is designed and implemented in a 180 nm CMOS technology. It has been demonstrated that the proposed TIA shows a significant increase in transimpedance gain, 1.72 GΩ with a bandwidth of 180 kHz and input referred current noise is 18 fA/√Hz for an input current of 200 pA. The total power consumption is 52 μW with a 1.4 V supply and occupies a chip area of 110 μm × 140 μm.

A broken symmetry approach for the modeling and analysis of antiparallel diodes-based chaotic circuits: a case study

Abstract: This paper focuses on the modeling and symmetry breaking analysis of the large class of chaotic electronic circuits utilizing an antiparallel diodes pair as nonlinear device necessary for chaotic oscillations. A new and relatively simple autonomous jerk circuit is used as a paradigm. Unlike current approaches assuming identical diodes (and thus a perfect symmetric circuit), we consider the more realistic situation where both antiparallel diodes present different electrical properties in spite of unavoidable scattering of parameters. Hence, the nonlinear component synthesized by the diodes pair exhibits an asymmetric current–voltage characteristic which engenders the explicit symmetry break of the whole electronic circuit. The mathematical model of the new circuit consists of a continuous time 3D autonomous system with exponential nonlinear terms. We investigate the chaos mechanism with respect to model parameters and initial conditions as well, both in the symmetric and asymmetric modes of operation by using bifurcation diagrams and phase space trajectories plots as main indicators. We report period doubling route to chaos, spontaneous symmetry breaking, merging crisis and the coexistence of two, four, or six mutually symmetric attractors in the symmetric regime of operation. More intriguing and complex nonlinear behaviors are revealed in the asymmetric system such as coexisting asymmetric bubbles of bifurcation (a new kind of phenomenon discovered in this work), hysteretic dynamics, critical phenomena, and coexisting multiple (i.e. two, three, four, or five) asymmetric attractors for some appropriately selected values of parameters. Laboratory experimental tests are conducted to support the theoretical analysis. The results obtained in this work clearly indicate that chaotic circuits with back to back diodes can demonstrate much more complex dynamics than what is reported in the relevant literature and thus should be reconsidered accordingly following the method described in this paper.

A 0.9-V supply, 16.2 nW, fully MOSFET resistorless bandgap reference using sub-threshold operation

Abstract: A nano-watt bandgap voltage reference (BGR) is presented. To provide a low-voltage and low-power BGR, the circuit has been biased in the sub-threshold region; thereby, drawing a few nano-amperes current from the source, has been achieved. In order to reduce die area and also power consumption, instead of resistor, transistor is used. To generate PTAT voltage, self-cascode composite structure is used for the transistors. The results from post-layout simulation using 0.18-μm standard CMOS technology show that the proposed BGR circuit generates a reference voltage of 625 mV, obtaining temperature coefficient of 13 ppm/ °C in the temperature range of − 25 °C to 110 °C. The simulated power supply rejection ratio is 42 dB. Fully designed with MOS transistors, the circuit draws 18 nA from a 0.9-V supply. The active area of the proposed BGR is 0.00067 mm2.

Design analysis of high level inverter with EANFIS controller for grid connected PV system

Abstract: For providing better reliability and getting minimal harmonics, multilevel inverters are commonly employed in grid connected photovoltaic systems. This paper presents 27 level inverter with reduced switch topology to get better reliability with low harmonics. This inverter performance completely relies on EANFIS controller which is the combination of ANFIS and Emperor Penguin Optimization (EPO) algorithm. Working procedure of ANFIS will be optimized by EPO to make us easy to deal MLI switching angle and produce harmonic-less control voltage. EPO provides efficient result by means of computational complexity, time and space complexity. In our work, this is the main reason to select EPO for optimizing ANFIS controller. The proposed work will be implemented in Simulink working environment. Resultant outcomes like inverter output, controller output and THD analysis will be compared with recently developed existing works.

Ultra low power wide range four quadrant analog multiplier

Abstract: A novel four quadrant FGMOS analog multiplier having properties such as low voltage-low power and wide input linearity range is presented. Power consumption of the proposed multiplier is 26.2 nW and the input swing is rail-to-rail which is obtained by choosing the ratio of input capacitances to total capacitance of FGMOS transistors resulting a reduction in the transconductance. Other important features of the proposed multiplier are the bandwidth of 52.5 MHz and maximum THD of 2.04% (when the input voltages are at supply voltage level).