Showing papers in "Chinese Journal of Semiconductors in 2000"

Transit Properties of High Power Ultra\|Fast Photoconductive Semiconductor Switch

Abstract: Experiments of a GaAs ultra\|fast Photo\|Conductive Semiconductor Switch (PCSS) are reported. Both the linear and nonlinear modes were observed when triggered by the μJ nano\|second laser. The peak current could be as high as 560A. The rise time of the current pulse responses is less than 200ps when triggered with 76MHz femto\|second laser.

Fame:A Fast Detailed Placement Algorithm for Standard\| Cell Layout Based on Mixed Mincut and Enumeration

Abstract: Rapid progress in manufacturing greatly challenges to the VLSI physical design in both speed and performance. A fast detailed placement algorithm, FAME is presented in this paper, according to these demands. It inherits the optimal positions of cells given by a global placer and exact position to each cell by local optimization. FM Mincut heuristic and local enumeration are used to optimize the total wirelength in y and x directions respectively, and a two way mixed optimizing flow is adopted to combine the two methods for a better performance. Furthermore, a better enumeration strategy is introduced to speed up the algorithm. An extension dealing with blockages in placement has also been discussed. Experimental results show that FAME runs 4 times faster than RITUAL and achieves a 5% short in total wirelength on average.

Control of Spontaneous Emission in Quantum Well Micro Cavity Lasers with Distributed Bragg Reflectors

Abstract: Based on cavity quantum electrodynamics and physics of quantum well, the spontaneous emission spectra in quantum well micro cavity lasers with DBRs have been calculated. As a result, spontaneous emission intensity in one direction can be enhanced to about10\+3 times greater than that in the semiconductor bulk material due to the confinement of the micro cavity with DBRs and quantum well to the photons and carries, respectively. The total spontaneous emission intensity also increases 10 times.

Numerical Simulation of BJMOSFET on Current\|Voltage Characteristics

Abstract: A new power MOSFET Structure with a pn junction——Bipolar Junction MOSFET(BJMOSFET) has been proposed.The device has the advantages of both BJT and FET. The numerical model of the I V characteristics of BJMOSFET has been obtained on the basis of both numerical and analytical methods. With the software package of Mathematic, we firstly calculate the gain factor, and then simulate the voltage tranmission,voltage output and voltage transfer's characteristic graphs of the BJMOSFET. The simulation result indicates that BJMOSFET has the current density, which is about 25% larger than the power MOSFET, under the same operating conditions and with the same structure parameters, except that the threshold voltage increase a little.

A Type of Bootstrapped Charge\| Recovery Logic Circuit

Abstract: A new Bootstrapped Charge\|Recovery Logic (BCRL) driven by two\|phase no n\|overlap power clock is presented. The logic value of BCRL circuit is calculat ed by the CMO S\|latch type circuits, and the loads driven full\|adiabatically by bootstrapped NMOS transistors with full\|swing operation. Comparision between the powers of static CMOS and state\|of\|art semi\|adiabatic circuits is performed on an inver ter with capacitance load. With the paramters of 0.65 micron CMOS device,the simulation results show that the BCRL circuit can work a t 100MHz power clock and it has a satisfactory power saving comparing with other semi\|adiabatic circ uits.

Mechanism on Energy Transfer of Photoluminescence Exciton in Erbium Doped Silicon

Abstract: Erbium implanted silicon was treated by lamp\|heating rapid thermal annealing (RTA). An exciton\|mediated energy transfer model in erbium\|doped silicon is presented. The emission intensity is related to optical active erbium concentration, lifetime of excited Er 3+ ion and spontaneous emission time. The thermal quenching of the erbium luminescence in Si is caused by thermal ionization of erbium bound exciton complex and nonradiative energy backtransfer processes, which correspond to the activation energy of 6 6 meV and 47 4 meV, respectively.

Reliability of n\|GaAs Ohmic Contact With TiN Diffusion Barrier\+*

Abstract: A rapid evaluation method——temperature ramp method, for GaAs MESFETs ohmic contacts is proposed, and an automatic evaluation system has been developed. By using these method and system, activation energy for ohmic contacts degradation can be obtained with less time and samples than traditional method, but the results are in agreement with those obtained by traditional methods. In accordance with the drawbacks of traditional AuGeNi/Au ohmic contacts, a new ohmic contacts system with TiN diffusion barrier layer is proposed. Experimental results show that the reliability of ohmic contacts with TiN are greatly superior to that of traditional AuGeNi/Au ohmic contacts.

Low-Temperature Deposition of AlN Films\+*

Abstract: A new method for low\|temperature deposition of AlN films by combining ECR microwave discharge with pulsed laser deposition is presented. By means of pul sed laser ablation of Al target in ECR nitrogen plasma, AlN films were deposited on Si substrates in temperatures below 80℃. Together with the sample charact erization and plasma emission analysis, the mechanism of the film growth was dis cusse d. The existence of activated nitrogen species is responsible for the Al\|N syn thesis. The irradiation of the substrates with plasma accelerates the film formation.

Analysis of Single Event Upset in CMOS SRAMs

Abstract: The time factor in Single Event Upset (SEU) in CMOS SRAMs is analyzed. It is not appropriate only according to the critical charge to determine whether a SEU occurs in a SRAM. The recovery time, the feedback time and charge collection process must be considered. The formulas to calculate the recovery time and the feedback time are presented and some methods to harden CMOS SRAMs against SEU are proposed. The drain potential of the off\|MOSFET is analyzed during the charge collection. A new definition of the critical charge for CMOS SRAM is suggested. A way to determine whether an ion can induce SEU in SRAM is presented.

High Speed Multilevel Staged Clock Routing

Abstract: Clock routing is one of major steps in high performance driven layout design under deep sub micron technology. Buffered clock tree construction is a key factor for clock routing. A novel buffered clock routing algorithm is proposed. The strategy is to perform buffer insertion and placement according to clock sink distribution before clock net routing, and to optimize clock tree topology generation, detailed embedding following the buffer insertion process. The influence of the placed buffers on routing will be significantly reflected. The experimental results show that buffer pre\|placement will avoid blind routing in a great extent and achieve the balance of sub\|tree delay and load capacitance efficiently.

Surface Structures of Silicon Nitride Thin Films on Si(111)

Abstract: After exposing Si(111) to NH\-3 at about 1075K,a 1 02nm surface periodic structure (the “8/3×8/3” reconstruction) is observed in the scanning tunneling microscopy (STM) images.When the nitridation temperature is above 1125K,a surface superstructure with a period of 3.07nm is observed. Both of the superstructures induce an “8×8” electron diffraction pattern. Our systematic analyses suggest that the 3.07nm superstructure is the 4×4 reconstruction on the Si\-3N\-4(0001) surface of the crystalline silicon nitride (β\|Si\-3N\-4) thin film formed on Si(111),while the 1.02nm periodic structure is an incomplete nitridation phase on the Si(111) surface.

A New Timing-Driven Placement Algorithm Based on Table\|Lookup Delay Model\+*

Abstract: An algorithm is presented for obtaining placements of cell\|based very large scale integrated circuits, subject to timing constraints based on table\|lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well\|known quadratic placement with bottom\|up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising.

A Quasi-Thermodynamic Model of MOVPE of InGaN

Abstract: A quasi\|thermodynamic model of MOVPE growth of In\- x Ga\-\{1- x \}N alloys has been proposed with TMGa, TMIn and ammonia as source materials. In this improved model, the effect of low decomposition rate of ammonia is considered and the number of moles is used to express the mass conservation constraints on element N, H, In and Ga. It is assumed that the alloy was synthesized by the reactions between ammonia and group III elements. The equilibrium partial pressures over the In\- x Ga\-\{1- x \}N have been calculated. For the In\- x Ca\-\{1- x \} alloys the relationship between the input vapor and the deposited solid composition has been calculated and the results compared with the literature data. The good agreement on the compositions from calculation and the experiment shows that our improved model is suitable for applying to the In\- x Ga\-\{1- x \}N alloys grown by MOVPE. It is difficult for In\- x Ga\-\{1- x \}N alloy to grow, especially for high\|indium alloys, because In\- x Ga\-\{1- x \}N is an immiscible alloy and InN has a very high In vapor pressure. It is also shown that gallium has strong tendency of preferential incorporation into the In\- x Ga\-\{1- x \}N alloy. In order to enhance the incorporation of indium into the InGaN, we should use the lower growth\|temperature,lower reactor pressure, higher input V/III ratio and higher nitrogen fraction in the carrier gas, in addition, the decomposed fraction of ammonia should also be reduced. Indium droplets would be deposed if the growing conditions were not selected properly.

High Speed Current Domain CMOS D/A Converter Design

Abstract: This paper describes a 10 bit 50MSample/s dual mode CMOS D/A Converter fabricated in a 1μm CMOS technology.One mode is normal,another is power\|save mode,in which a modified look\|ahead circuit is designed to reduce power.The D/A converter has been fabricated by using single\|poly double\|metal standard digital process.The integral non\|linearity error is less than 0 46LSB,and the differential non\|linearity error is less than 0 03LSB in the power\|saving mode.The settling time to ±0 1% is less than 20ns.This D/A converter has a single power supply of 5V,and dissipates 250mW at 50MS/s when the input is 1023,while 20mW when input is zero.The circuit chip size is 1 8mm×2 4mm.

Unified MOSFET Short Channel Factor Using Variational Method

Abstract: A new natural gate length scale for MOSFET's is presented using Variational Method. Comparison of the short channel effects is conducted for the uniform channel doping bulk MOSFET, intrinsic channel doping bulk MOSFET, SOI MOSFET and double gated MOSFET. And the results are verified by the 2D numerical simulation. Taken all the 2\|D effects on front gate dielectric, back gate dielectric and silicon film into account, the data validity of electrical equivalent oxide thickness is investigated by this model, as shows that it is valid only when the gate dielectric constant is relatively small.

Preparation of Crystal Oriented α-SiC Films by Pulsed ArF Laser Deposition on Si(111)\+*

Abstract: By ablating ceramic SiC target with pulsed ArF laser, SiC films are deposited on the Si(111) substract at temperature 800℃.After the post deposition annealing at the temperature of 920℃ in high vacuum (10 -3 Pa),crystal α SiC films are obtained.The properties of the films before and after annealing such as the surface morphology, crystal structure,composition,chemical state of the element and photoluminescence,etc. are studied by Fouriour Transform Infrared spectrum (FTIR),X\|ray photoelectron spectrum (XPS),scanning electron microscope (SEM),X\|ray diffraction (XRD),transmission electron spectrum (TEM),photoluminescence (PL) methods. From analysis it is obtained that SiC film has grown up to a highly oriented crystal α SiC(0001)∥Si(111) epitaxial film through an amorphous nucleation and growth process at the fairly low temperature of 920℃.Ratio of C and Si is about 1 01 inside the film.There are some contaminated carbon and a small quantity of oxidized Si and C on the surface.Excited by ultraviolet light with the wavelength of 280nm at room temperature,the films give out a fairly strong emission peak at 341nm,whose FWHM is 45nm,as shows rather good shortwave photoluminescence quality.The mechanism of the film lighting emission deserve further investigation.

2-D Hierarchical Compaction Algorithm for VLSI Layout Reuse

Abstract: Due to the unbalance between the development of EDA system and IC process technique,the layout reuse technique is demanded on the market.The existing layout should be compacted to fit for the new process technique. An efficient 2\|D compaction algorithm is proposed,which is based on the constraint graph expression of the figures on layout and newly designed rules.In order to do compaction on the chip level, a hierarchical strategy and the ‘fall leaves pool’ data structure are used,regarding the interconnections as soft lines it also can add to jogs automatically.From the test cases it is shown that this compaction algorithm is practical and effective.

Optimum Design of Base Region in Punch-Through Structure Used in Conductivity\|Modulated Power Devices

Abstract: Based on the critical electric field model, the optimum design theory of the base region in the punch\|through structure used in the conductivity\|modulated power devices is developed. The expressions of the optimum design are deduced by given the punch\|through factor F to be 4, as is used to calculate the optimum base region parameters of the typical breakdown voltages. The results were compared with the previous values obtained by Y.S.Kao, S.K.Ghandhi and W.Fichtner et al., respectively, which should be used directly in the optimum design of the high voltage power devices such as IGBT,MCT, FCT and rectifier diode, etc.

Influence of Electron\|Surface Phonon Strong\|Coupling on Properties of Polaron in CdF_2 Semiconductor Slab\+*

Abstract: The influences of the electron interaction with both the weak\|coupling bulk longitudinal optical phonons and the strong\|coupling surface optical phonons on the properties of the polaron in a semiconductor slab are studied by using improved Huybrechts' linear combination operator and variational method.The law of the change of the effective mass and the self\|trapping\|energy of the polaron changing with the thickness of the slab is derived.For CdF\-2 semiconductor,the contributions of different branches phonon\|electron interaction on the effective mass and self\|trapping\|energy of the polaron are calculated.

Performance Comparison of GaAs/AlGaAs Quantum Well Infrared Photodetectors Grown by MOCVD and MBE

Abstract: GaAs/AlGaAs Quantum Well Infrared Photodetector (QWIP) structure is grown by using Metal Organic Chemical Vapor Deposition (MOCVD) and Molecular Beam Epitaxy (MBE) The differences of two kinds of material are compared by photoresponse and photoluminescence spectroscopy The device performance fabricated by using them are compared from their responsivity and \%I\|V\% characteristic Peak wavelength of MOCVD QWIP is 7\^9μm and its responsivity could be 6×10\+3V/W

Strain-Compensated InGaAs/InAlAs Quantum Cascade Laser\+*

Abstract: Growth of quantum cascade lasers based on strain compensated In x Ga 1 -x As/In y Al 1- y As and operating at a wavelength λ ≈3 5—3 7 micron is reported. Quasi\|continuous wave operation at room\|temperature(RT) has been achieved. For a 1 6mm cavity length and 20 micron ridge waveguide width, quasi continuous wave lasing operation at RT persists more than 30 min.

Net Congestion Elimination for Datapaths by Placement Refinement

Abstract: The layout of datapaths is much complexer than that of a normal IC chips, because more constraints must be considered. A novel method for eliminating the net congestion of datapath chips is presented. The main idea is to modify the placement locally according to the global routing result. The problem is abstracted to a nonlinear programming problem and could be transformed to a convex one. Experimental results demonstrate that the method can eliminate the net congestion of datapath chips effectively.

Compact and Economical MMI Optical Power Splitter for Optical Communication

Abstract: A 1×8 GaAs/GaAlAs optical power splitter based on a MultiMode Interference (MMI) coupler is presented. The input and output single mode waveguides are optimized by the Discrete Spectral Index Method (DSIM) and a moderate square spot on the output in deep etched rib waveguides is obtained. The fabrication tolerance has been analyzed by the Finite Difference Beam Propagation Method (FDBPM). The device was fabricated by the dry etching technique and the near field output obtained. The device shows polarization insensitive, large fabrication tolerance, low theoretical excess loss and low power imbalance.

Forming of Very Shallow Junction for S/D Extension in Deep Sub\|Micron CMOS Devices\+*

Abstract: Very shallow junctions for S/D extension in deep sub\|micron CMOS devices are required to suppress the short channel effect as devices scaling down,and the surface concentrations ( N s) of these junctions need to be kept in a higher value to reduce the series resistance of the lightly doped drain structure.But it is very difficult for the conventional ion implantation to meet the requirement above.This article presents the results of forming very shallow and ultra\|shallow junctions used in 0.25 micron and 0.10 micron CMOS devices respectively with low energy implantation (LEI) and pre\|amorphization implantation plus low energy implantation (PAI+LEI).The LEI was performed on the modified normal ion\|implantor (IM\|200M).Using LEI only the minimum junction depth,is 61nm for NMOS and 57nm for PMOS ( N sub =1×10 18 cm\+\{-3\}) respectively after 1000℃ RTA and both N \-s are above 3×10 19 cm -3 .While using Ge PAI+LEI,under the optimized processing condition,the junction depth of 58nm for NMOS and 42nm for PMOS are obtained,with the leakage current density being 4nA/cm 2.

Boundary Element Method for Extraction Substrate Coupling Parameter in Mixed\|Signal ICs

Abstract: Boundary Element Method(BEM) is used in substrate coupling parameter extraction of mixed\|signal ICs. Green Function that satisfies the substrate boundary conditions is solved out in this paper. Using this Green Function instead of the Green Function in free space makes only the ports area on the substrate top surface need to be discretized. Discrete Cosine Transform which is based on FFT is used when determine impedance element, which improves the solution speed dramatically. Comparing to Finite Difference Method, the solution speed is improved by one order of magnitude, but the accuracy is kept. Comparing to Wemple's result where Voronoi tessellation is used to partition the layout and analytical method is used to compute substrate coupling, the accuracy of BEM is improved significantly.

Epitaxial Growth of 150mm Silicon Epi\|Wafers for Advanced IC Applications

Abstract: With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub\|micron and beyond level, the next generation of IC device requires silicon wafers with more improved electrical characteristics and reliability as well as a high perfection of the wafer surface. Compared with the polished wafer with a relatively high density of crystal originated defects (e. g. COPs), silicon epi\|wafers can meet such high requirements. The current development of researches on the 150mm silicon epi\|wafers for advanced IC applications is described. The P/P\++ CMOS silicon epi\|wafers were fabricated on a PE2061 Epitaxial Reactor (made by Italian LPE Company). The material parameters of epi\|wafers, such as epi\|defects, uniformity of thickness and resistivity, transition width, and minority carrier generation lifetime for epi\|layer were characterized in detail. It is demonstrated that the 150mm silicon epi\|wafers on PE2061 can meet the stringent requirements for the advanced IC applications.

Optimization of a 1×8 Arrayed\|Waveguide Grating Multi/Demultiplexer\+*

Abstract: Using transmission function and diffraction loss function, the crosstalk, diffraction loss and non\|uniformity of the 1×8 arrayed\|waveguide grating multi/demultiplexer are simulated and values of 2M+1 and width of the tapered waveguide are optimized The simulation results verify that the device we've designed has high performance

Characterization of Schottky Barrier Contact Between Ultra Thin Epitaxial CoSi_2/n\|Si

Abstract: The ultrathin (～10nm) epitaxial CoSi\-2/n\|Si Schottky barrier contacts are investigated. By depositing Co(3—4nm)/Ti(1nm) bilayer on Si(100) and following by rapid thermal annealing, an ultrathin epitaxial CoSi\-2 film is grown on Si substrate. X\|ray diffraction spectra and Rutherford backscattering spectra show that the film has good epitaxial quality. The properties of Schottky barrier diode are characterized by I\|V and C\|V measurements over a temperature range of 82—332K. At room temperature, the Schottky diode shows a barrier height of 0 59eV with a ideality factor close to unity by I\|V measurement. The Schottky barrier height decreases with the decreasing of the temperature, which can be explained by the Schottky barrier inhomogeneties theory with an assumption of Gauss distribution of Schottky barrier height over the interface. The fluctuation of local barrier height of the ultra\|thin TIME (Ti\|Interlayer Mediated Epitaxy)\|formed CoSi\-2/Si contact is observed by ballistic\|electron\|emission microscopy.

Super-Fast Fully Depleted CMOS/SOI Ring Oscillator with Delay Time of 45ps

Abstract: The fully depleted CMOS/SOI device and circuit with channel length of 0 8 micron are studied.The well\|behaved characteristics of device and circuit are achieved,the propagation delay per\|stage of 101\|stage 0 8 micron CMOS/SOI ring oscillator is 45ps with 5V supply voltage.As thickness of silicon and channel length reduced,the speed of circuit are increased.The 0 8 micron CMOS/FDSOI ring oscillator is 30 per cent faster than 0 8 micron CMOS/PDSOI ring oscillator,and 15 per cent faster than 1 micron CMOS/FDSOI ring oscillator.

Quantitative Investigation of Surface Layer Structure of GaAs(100) After Thermal Annealing by Angular Dependent XPS

Abstract: By employing angular dependent X\|Ray Photoelectron Spectroscopy (XPS) technique, an analysis of chemical composition/depth of GaAs(100) surface after thermal annealing ranging from 600℃ to 675℃ is achieved.A transition layer between the surface oxide layer and substrate, being As\|abundant naturally,gets Ga\|abundent after annealing above 600℃.It is found that the relative atomic concentration of Ga and the thickness of the transition layer are increasing when the annealing temperature gets higher,i.e. Ga atomic concentration is from 53 4% to 62 1% and the thickness from 1 3nm to 2 2nm at the temperature ranging from 600℃ to 675℃,while the As oxide and Ga oxide are eliminated gradually.