Showing papers in "IEEE Computer in 1987"

No Silver Bullet Essence and Accidents of Software Engineering

Abstract: But, as we look to the horizon of a decade hence, we see no silver bullet. There is no single development, in either technology or in management technique, that by itself promises even one order-of-magnitude improvement in productivity, in reliability, in simplicity. In this article, I shall try to show why, by examining both the nature of the software problem and the properties of the bullets proposed.

Hypertext: An Introduction and Survey

Abstract: This article is a survey of existing hypertext systems, their applications, and their design. It is both an introduction to the world of hypertext and, at a deeper cut, a survey of some of the most important design issues that go into fashioning a hypertext environment. The concept of hypertext is quite simple: Windows on the screen are associated with objects in a database, and links are provided between these objects, both graphically (as labelled tokens) and in the database (as pointers). But this simple idea is creating much excitement. Several universities have created laboratories for research on hypertext, many articles have been written about the concept just within the last year, and the Smithsonian Institute has created a demonstration laboratory to develop and display hypertext technologies.

Improving Software Productivity

Abstract: This article discusses avenues of improving productivity for both custom and mass-produced software. Some of the topics covered are: The importance of improving software productivity, measuring software productivity, analyzing software productivity, improving and indicating trends in software productivity

Programming for Parallelism

Abstract: In the last few years we have seen an explosion in the interest in and availability of parallel processors and a corresponding expansion in applications programming activity. Clearly, applications programmers need tools to express the parallelism, either in the form of subroutine libraries or language extensions. There has been no shortage of providers of such tools. These tools allow the applications programmer to express the parallelism explicitly. There are also projects underway to provide automatic parallelization of sequential code.

A Survey and Comparision of Fault-Tolerant Multistage Interconnection Networks

Abstract: Today all branches of engineering and a multitude of other disciplines rely firmly and increasingly on computational support. However, each discipline has important problems that, to be solved feasibly, await our ability to field computers with orders of magnitude greater performance than currently available. Consequently, the need for very high performance computing is larger than ever and growing. To date, high-performance computers have owed their speed primarily to advances in circuit and packaging technology. These technologies are subject to physical limits constraining the ultimate speed of a conventional uniprocessor computer. Parallel processing computers executing problems solutions expressed as parallel algorithms translated into parallel machine programs can exceed the single processor speed limit. The means for communication among processors, memory modules, and other devices of a parallel computer is the interconnection network.

Software Development Environments

Abstract: : The growing demand for reliable large-scale software systems cannot be met without advances in software development environments. Although promising technologies are emerging, a number of issues must be addressed to ensure the timely transition of those technologies to practice. This paper discusses issues relevant to the transition of such technologies and projects to be undertaken by the Software Engineering Institute to address those issues. The SEI'S primary mission is the transition of modern software engineering methods to practice. Software engineering environments represent a good means to support that end. They provide the means both to integrate tools and to provide a uniform conceptual framework for the user. While from one point of view an environment can enforce uniform practices, it also provides the means to maintain the rich information base that most likely will be required to support reusability of requirements and designs. The SEI's role with respect to environments is not to build a specific environment, but to help explore the validity of new concepts by building prototypes, to stimulate the research community to attack critical problems, and to refine the requirements for the next generation of large-scale environments.

The Nature and Evaluation of Commercial Expert System Building Tools

Abstract: This memorandum reviews the factors that constitute an Expert System Building Tool (ESBT) and evaluates current tools in terms of these factors. Evaluation of these tools is based on their structure and their alternative forms of knowledge representation, inference mechanisms and developer/end-user interfaces. Next, functional capabilities, such as diagnosis and design, are related to alternative forms of mechanization. The characteristics and capabilities of existing commercial tools are then reviewed in terms of these criteria.

The Performance of Multicomputer Interconnection Networks

Abstract: The interdependency of nodes and multicomputer interconnection networks is examined using simple calculations based on the asymptotic properties of queueing networks. Methods are described for choosing interconnection networks that fit individual classes of applications. It is also shown how analytic models can be extended to benchmark existing interconnection networks.

A survey and comparison of fault-tolerant multistage interconnection networks

Abstract: Intrinsically fault-tolerant multistage interconnection networks (MINs) are surveyed, categorizing the MINs by the amount of hardware modifications they use to provide redundancy. The diversity of such MINs and the scope of fault-tolerance techniques are examined. A hypothetical MIN with ideal engineering characteristics is defined, and the surveyed MINs are compared to this standard.

Optical Crossbar Networks

Abstract: With advances in technology and the declining cost of computer hardware, it is now feasible to design computer architectures consisting of large numbers of processors executing programs concurrently. Most parallel computing architectures can be generally classified into SIMD and MIMD systems. SIMD processors simultaneously and synchronously execute the same instructions on different data streams, while MIMD processors are not necessarily synchronous and execute different instructions on different data streams. In image processing, for example, low level tasks generally have an image as input and image as output. SIMD systems well suit these tasks, and most existing parallel image processing systems are of this type. An important part of a parallel processing system is the interconnection needed for the transfer of information among processors, and between processors and memories. In such systems several processors may need data from memories or other processors simultaneously; therefore, the network should be capable of providing fast parallel access to data. The interconnections designed for use in multiprocessor systems range from a common bus to a crossbar network.

Augmented Shuffle-Exchange Multistage Interconnection Networks

Abstract: Multistage interconnection networks, or MINs, have long been studied for use in telephone switching and multiprocessor systems. Since the early 70's several MINs have been proposed to meet the communication needs of multiprocessor systems in a cost-effective manner. These MINs are typically designed for N = m{sup n} inputs and N outputs and contain n stages of (N/m) crossbar switching elements of size m x m. The switches in adjacent stages are connected in such a way that a path can be found from any input to any output. Such MINs have many properties that make them attractive for multiprocessor systems, including O(NlogN) hardware cost as opposed to the O(N/sup 2/) hardware cost of crossbar switches, the ability to provide up to N simultaneous connections, and O(logN) path lengths. Moreover, they can employ simple and distributed routing algorithms - algorithms that make a central routing controller unnecessary and also result in relatively low communication latency times.

Connectionist Architectures for Artificial Intelligence

Abstract: A number of researchers have begun exploring the use of massively parallel architectures in an attempt to get around the limitations of conventional symbol processing. Many of these parallel architectures are connectionist: The system's collection of permanent knowledge is stored as a pattern of connections or connection strengths among the processing elements, so the knowledge directly determines how the processing elements interact rather that sitting passively in a memory, waiting to be looked at by the CPU. Some connectionist schemes use formal, symbolic representations, while others use more analog approaches. Some even develop their own internal representations after seeing examples of the patterns they are to recognize or the relationships they are to store. Connectionism is somewhat controversial in the AI community. It is new, still unproven in large-scale practical applications, and very different in style from the traditional AI approach. The authors have only begun to explore the behavior and potential of connectionist networks. In this article, the authors describe some of the central issues and ideas of connectionism, and also some of the unsolved problems facing this approach. Part of the motivation for connectionist research is the possible similarity in function between connectionist networks and the neutral networksmore » of the human cortex, but they concentrate here on connectionism's potential as a practical technology for building intelligent systems.« less

Applications of the Connection Machine

Abstract: The Connection Machine development effort was initiated in the belief that parallel processing and artificial intelligence could together accelerate the rate of progress toward truly intelligent machines. This progress is the result of the ease with which the machine can be programmed and the dramatic increase in compute power that the machine can bring to bear. The authors have been able to run many trials of experiments in instances where previously, running just one would have been considered an achievement and no further experimentation would have been done. This has enabled exploring a great many more hypotheses and to work on much larger problems that had been possible on previous-generation artificial intelligence workstations. The ease of programming is in part the result of a decision to use existing serial machines (the Symbolics 3600 or Digital Equipment Corporation VAX), thus leaving unchanged the operating systems, editors, file systems, debuggers, network communications systems, and so on, so as to provide familiar programming environments. The Connection Machine is programmed in conservative extensions of Common Lisp and C. Users familiar with these languages and with front-end computer systems have been able to produce results on the Connection Machine on the first day that theymore » use it.« less

Wavefront Array Processors-Concept to Implementation

Abstract: Most signal and image processing algorithms can be decomposed into computational wavefronts that can be processed on pipelined arrays. T he supervisory overhead incurred in general-purpose supercom-T puters often makes them too slow and expensive for real-time signal and image processing. To achieve a through-put rate adequate for these applications, the only feasible alternative appears to be massively concurrent processing by special-purpose hardware-by array processors. Progress in VLSI technology has lowered implementation costs for large array processors to an acceptable level, and CAD techniques have facilitated speedy prototyping and implementation of application-oriented (or algorithm-oriented) array processors. Digital signal and image processing encompasses a variety of mathematical and algorithmic techniques. Most signal and image processing algorithms are dominated by transform techniques, con-volution and correlation filtering, and certain key linear algebraic methods. These algorithms possess properties such as regularity, recursiveness, and locality, and these properties can be exploited in array processor design. With VLSI it becomes feasible to construct an array processor that closely resembles the flow graph of a particular algorithm. This type of array maximizes the main strength of VLSI-intensive computing power-and yet circumvents its main weakness-restricted communication.

Multiple Bus Architectures

Abstract: A recent study noted that for shared memory multiprocessors the single system bus typically used to connect the processor to the memory is by far the most limiting resource, and system performance can be increased considerably by increasing the capacity of the bus. One way of increasing the bus capacity, and also the system's reliability and fault tolerance, is to increase the number of buses. In this article the authors discuss using multiple buses to provide highbandwidth connections between the processors and the shared memory, thereby allowing the construction of larger and more powerful systems than currently possible.

Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors

Abstract: Many scientific and technical applications require high computing speed; those involving matrix computations are typical. For applications involving matrix computations, algorithmically specialized, high-performance, low-cost architectures have been conceived and implemented. Systolic array processors (SAPs) are a good example of these machines. An SAP is a regular array of simple processing elements (PEs) that have a nearest-neighbor interconnection pattern. The simplicity, modularity, and expandability of SAPs make them suitable for VLSI/WSI implementation. Algorithms that are efficiently executed on SAPs are called systolic algorithms (SAs). An SA uses an array of systolic cells whose parallel operations must be specified. When an SA is executed on an SAP, the specified computations of each cell are carried out by a PE of the SAP.

CAD Model-Based Localization of Parts in Manufacturing

Abstract: The authors present a solution to the problem of determining the location of a part in a robotic manufacturing situation. The problem is solved by matching a database surface description of the part with discrete points measured on its surface. The matching is accomplished through the calculation of a transformation. The transformation specifies the position and orientation of the part as it appears in front of the robot. The method was developed for use in flexible manufacturing where low precision, general purpose fixtures, and positioners are employed. Knowledge of the approximate location of the part is used. In a typical application the uncertainty in the location of the part is small relative to the dimensions of the part, but more than an order of magnitude greater than the tolerances allowed by the manufacturing operation. The introduction of a robot into a manufacturing process requires an investment in time and effort to program the robot. Consequently, industrial robots have found use in large-batch manufacturing such as the automotive industry, where a large volume of identical parts justifies the initial outlays for programming.

Fault Tolerance Techniques for Systolic Arrays

Abstract: This article describes various techniques for fault tolerance that can be applied to systolic array architectures. The approach of algorithm-based fault tolerance is shown to be the natural one for such systems. D igital systems that are operated in applications where there is a D high cost of failure require high reliability and continuous operation. Since it is impossible to guarantee that portions of a system will never fail, such systems need to be designed to tolerate failures of the system components. The discipline of fault-tolerant computing is, therefore, one which has attracted a great deal ofresearch interest. Researchers have attempted to derive highly effective and, at the same time, efficient techniques to tolerate failures in complex digital systems. The high computation needs of many applications can now be met through the use of highly parallel special-purpose systems that can be produced very cost effectively through the use of very large scale integration (VLSI) technology. Systolic arrays, such as the ESL systolic array' and the Carnegie Mellon Warp processor,2 are examples of such systems. This article deals with techniques that can be used to achieve fault tolerance in such systolic arrays. It will provide an overview of classical fault tolerance techniques, discuss their applicability to this particular problem, and discuss new, very efficient, fault tolerance techniques ideally suited for such highly parallel systems. A system is said to have failed when it no longer provides the service for which it was designed.3 The manifestation of a failure will be the errors produced by the system. The cause ofan error is denoted as a fault within the system. Faults may be permanent or transient; a permanent fault, of course, will not necessarily produce errors for all system inputs or states. Faulttolerant computing thus deals with techniques designed to prevent errors at the output of a system. Faults may be inherent in the specification or design of a system, or may have physical causes, being introduced during manufacture ofthe system or due to wear-out in the field. Tolerance of design and specification of faults is an important area of study, and problems in preventing faults in hardware and tolerating faults in software have been studied. This area is, however, beyond the scope of this article, which will consider only the problem of tolerating physical failures. Any fault tolerance technique is designed to tolerate a given class of faults within a system. A fault can be treated at any level within the system-from a very low level, such as a transistor level, to a higher, module level. Most fault tolerance techniques have been designed to tolerate faults in some module within a system. Such a module-level fault model is ideal for VLSI, where a physical failure can cause some portion of a chip to be faulty. A module fault is assumed to result in arbitrary errors at the output of the module,

P-NAC: A Systolic Array for Comparing Nucleic Acid Sequences

Abstract: T he Princeton Nucleic Acid Comparator (P-NAC) is a linear sysT tolic array for comparing DNA sequences. The architecture is a parallel realization of a standard dynamic programming algorithm. Benchmark timings of a VLSI implementation confirm that, for its dedicated application, P-NAC is two orders of magnitude faster than current minicomputers. ' Experience with the prototype is shaping the design of a second-generation device, to be known as the Brown Nucleic Acid Comparator (BNAC), that will be algorithmically flexible and more tolerant of fabrication faults. The primary structure of DNA can be specified as a string of characters chosen from the alphabet {A, C, G, T}. While there exist a number of different metrics for comparing strings in general andDNA sequences in particular, it is not yet understood which are biologically valid. Nevertheless, an intuitively satisfying measure assumes that DNA \"evolves\" by undergoing a series of three elemental steps: the deletion of a single \"character\" (nucleotide), the insertion of a single

Digit-Pipelined Arnthmetic as Illustrated by the Paste-Up System: A Tutorial

Abstract: Data transmission in bit- or digit-serial fashion results in efficient communication both within and between VLSI chips. A comparison of the two methods requires only one communication wire per data item, but requires 2p cycles to transmit the data across that wire (where 2p is the precision in bits). Digit-serial transmission requires only O(log b) communication wires per data item, and only 2p/(log b) cycles to transmit the data (where b is the base). Limiting transmission between VLSI chips is desirable because of pin limitations. Limiting transmission within each VLSI chip is important so that the chip area needed for interconnections will be minimal. The possible penalty, of course, in using bit- or digit-serial transmission is slow processing speed, since several cycles are required to transmit a full data word. However, this speed limitation can be overcome by using pipelining to its fullest extent-that is, pipelining at the digit level.

Guest Editor's Introduction Interconnection Networks for Parallel and Distributed Processing

Abstract: With the rapid advances in technology, it is now feasible to build a system consisting of hundreds or thousands of processors. Processors in such a parallel/distributed system may spend a considerable amount of time just communicating among themselves unless an efficient interconnection network (IN) connects them. A complete interconnection such as crossbar may be cost prohibitive, but a shared-bus interconnection may be inefficient and unreliable. The authors need to design INs with both cost and performance between these two extremes. Parallel or distributed computers can generally be divided into two categories: multiprocessors and multicomputers. The main difference between the two lies in the level at which interactions between the processors occur.

CAD-Based 3D Object Representation for Robot Vision

Abstract: This article explains that most existing vision systems rely on models generated in an ad hoc manner and have no explicit relation to the CAD/CAM system originally used to design and manufacture these objects. The authors desire a more unified system that allows vision models to be automatically generated from an existing CAD database. A CAD system contains an interactive design interface, graphic display utilities, model analysis tools, automatic manufacturing interfaces, etc. Although it is a suitable environment for design purposes, its representations and the models it generates do not contain all the features that are important in robot vision applications. In this article, the authors propose a CAD-based approach for building representations and models that can be used in diverse applications involving 3D object recognition and manipulation. There are two main steps in using this approach. First, they design the object's geometry using a CAD system, or extract its CAD model from the existing database if it has already been modeled. Second, they develop representations from the CAD model and construct features possibly by combining multiple representations that are crucial in 3D object recognition and manipulation.

An Overview of Some Formal Methods for Program Design

Abstract: T he code of a computer program is. a formal text, describing precisely T the actions of a computer executing that program. As in other branches of engineering, the progress of its implementation as well as its eventual quality can be promoted by additional design documents , formalized before starting to write the final code. These preliminary documents may be expressed in a variety of notations suitable for different purposes at different stages of a project, from capture of requirements through design and implementation, to delivery and long-term maintenance. These notations are derived from mathematics, and include algebra, logic, functions, and procedures. The connection between the notations is provided by mathematical calculation and proof. This article introduces and illustrates a selection of formal methods by means of a single recurring example, the design of a program to compute the greatest common divisor of two positive numbers. It is hoped that some of the conclusions drawn from analysis of this simple example will apply with even greater force to software engineering projects on a more realistic scale. Requirements Imagine that a software engineer is called upon to construct a mechanism or The design of a small program, like that of a large system, requires a variety of formal methods and notations, related by mathematical reasoning. subroutine to compute the greatest common divisor z oftwo positive integers xand y. By an even greater feat of imagination, assume no prior knowledge ofthe concept of greatest common divisor, or of how to compute it. So the first task is to ensure that the engineer and client have the same understanding of what is required. Let us suppose first that they agree to confine attention to positive whole numbers (excluding zero). The required relationship between the parameters (x, y) and the result (z) may be formalized as follows: D .I z divides x Dl.2 zdividesy Dl.3 zisthegreatestofthesetofnum-bers satisfying both these conditions Dl.4 \"p divides q\" means \"there exists a positive whole number w such that pw = q\" Dl.5 \"p is the greatest member of a set S\" means \"p is in S, and no member of S is strictly greater than p\" It is essential that the notations used for formalization of requirements should be mathematically meaningful, but it would be unwise to place any other restriction upon them. Even in this simple example we have used logic, arithmetic, and set theory. An engineer …

Using Coincident Optical Pulses for Parallel Memory Addressing

Abstract: Common-bus, shared-memory multiprocessors are the most widely used parallel processing architectures. Unfortunately, these systems suffer from a memory/bus bandwidth limitation problem. For the designer of a hybrid optical/electronic supercomputer, an immediate temptation is to replace the shared electronic bus with an optical analog of higher bandwidth, but the true bottleneck in such systems is in the address-decoding circuits of shared memory units. In this article the authors propose a new memory structure that provides for parallel access in a multiprocessor environment. The proposed system has two advantages; it distributes the address-decoding circuitry to each of the requesting units on a common bus; and it allows for parallel fetches of memory data with a level of parallelism limited only by the ratios of optical to electronic bus bandwidths and the dimensionality of the memory array.

Parallel Querying of Large Databases: A Case Study

Abstract: Parallelism by itself does not necessarily lead to higher speed. In the case study presented here, the parallel algorithm was far less efficient than a good serial algorithm. The study does, however, reveal how to best use parallelism to best use-run the more efficient serial algorithm in a parallel manner. The case study extends the work of others who presented an algorithm for high-speed querying of a large database. The results show that the throughput for parallel query analysis is high in an absolute sense. But a performance analysis of speedup or other aspects of algorithmic behavior that would reveal what factors of machine and algorithm design contribute most strongly to the performance were not provided. This article provides that analysis.

Guest Editors' Introduction: Systolic Arrays-From Concept to Implementation

Abstract: Systolic arrays are the result of advances in semiconductor technology and of applications that require extensive throughput. Their realization requires human ingenuity combined with techniques and tools for algorithm development, architecture design, and hardware implementation. Invariably, the first reaction of people who are exposed to the systolic-array concept is one of admiration for the concept's elegance and for its potential for high performance. However, those who next attempt to implement a systolic array for a specific application soon realize that a wealth of subsumed concepts and engineering solutions must be mastered and understood. This special issue attempts to provide insights into the implementation process and to illustrate the different techniques and theories that contribute to the design of systolic arrays.

Some Systolic Array Developments in the United Kingdom

Abstract: For the last five or six years, there has been an active program of research on systolic array processors (SAPs) in the United Kingdom. In this article, the authors describe two key projects initiated at the Royal Signals and Radar Establishment (RSRE) and carried out in collaboration with a number of major electronics companies and several universities. The success of these projects demonstrates clearly that the systolic approach to system design is not just an academic concept but a practical means of exploiting large amounts of parallelism and hence achieving orders of magnitude improvement in performance for digital signal processing (DSP). This type of application not only demands but also fully utilizes the SAP architecture. The first project was aimed at developing an electronic processor capable of computing the vector of complex weights required to form the receive beam for an adaptive antenna array.

Introduction to Distributed-Software Engineering

Abstract: Distributed-software is made up of a fixed set of software processes that are allocated to various interconnected computers but that closely cooperate to achieve a common goal Interconnected computers are loosely coupled in the sense that interprocessor communication is done by message passing, not by sharing memory Distributed-software engineering poses a host of new and challenging problems for software developers This article addresses several of these problems, using the software life cycle as a guide

The Saxpy Matrix-1: A General-Purpose Systolic Computer

Abstract: There has been no reduction in the demand for higher performance in scientific computation. This is especially true in digital signal processing because new algorithms for that application require much more computation than do conventional techniques. The increasing volumes of data from seismic surveys, sonar and radar systems, and imaging systems need to be processed; these applications are important sources of demand for more throughput. The analysis of data that are generated by such new imaging technologies as magnetic resonance imaging creates additional demand. In signal processing and scientific computing, parallelism is pervasive. While the granularity of the parallelism may vary, the opportunity to perform many calculations in parallel is characteristic of it. Harnessing this inherent, abundant parallelism through new computer architectures is now one of the major thrusts in computer technology.

CAD-based robot vision

Abstract: This article explains that model-based recognition, programming, and control of manipulators is one of the key paradigms in computer vision and robotics To recognize and manipulate objects, the authors concern themselves only with expected objects in the task environment of a robot They use data from multiple sensors (such as television, range, force, torque, touch, etc) and a priori knowledge (object models, strategies for sensing, recognition and manipulation, etc) to equip the robot with intelligence so that it can sense, plan, and manipulate objects in its environment As shown, the basic computational model for object recognition and manipulation is strongly goal-directed Their goal is the capability to acquire a variety of 3D object models automatically with all the desired information for recognition and manipulation CAD has provided new opportunities and challenges for the use of models of 3D objects Using the available 3D models of objects, one can plan recognition and manipulation strategies during the off-line phase and do efficient real-time recognition and manipulation during the runtime phase