Showing papers in "IEEE Computer in 1994"
TL;DR: The analogy between genetic algorithms and the search processes in nature is drawn and the genetic algorithm that Holland introduced in 1975 and the workings of GAs are described and surveyed.
Abstract: Genetic algorithms provide an alternative to traditional optimization techniques by using directed random searches to locate optimal solutions in complex landscapes. We introduce the art and science of genetic algorithms and survey current issues in GA theory and practice. We do not present a detailed study, instead, we offer a quick guide into the labyrinth of GA research. First, we draw the analogy between genetic algorithms and the search processes in nature. Then we describe the genetic algorithm that Holland introduced in 1975 and the workings of GAs. After a survey of techniques proposed as improvements to Holland's GA and of some radically different approaches, we survey the advances in GA theory related to modeling, dynamics, and deception. >
2,095Â citations
TL;DR: The people and the work found under the CSCW umbrella are described, issues considered include: research and design areas, software development, office automation, small-group versus systems approach, US and European differences; and the history of groupware.
Abstract: CSCW and groupware emerged in the 1980s from shared interests among product developers and researchers in diverse fields. Today, it must overcome the difficulties of multidisciplinary interaction. This article describes the people and the work found under the CSCW umbrella. Issues considered include: research and design areas, software development, office automation, small-group versus systems approach, US and European differences; and the history of groupware. >
1,665Â citations
TL;DR: The authors focus on the goal of large-scale, hand-held mobile computing as a way to reveal a wide assortment of issues and look at some promising approaches under investigation and also consider their limitations.
Abstract: The technical challenges that mobile computing must surmount to achieve its potential are hardly trivial. Some of the challenges in designing software for mobile computing systems are quite different from those involved in the design of software for today's stationary networked systems. The authors focus on the issues pertinent to software designers without delving into the lower level details of the hardware realization of mobile computers. They look at some promising approaches under investigation and also consider their limitations. The many issues to be dealt with stem from three essential properties of mobile computing: communication, mobility, and portability. Of course, special-purpose systems may avoid some design pressures by doing without certain desirable properties. For instance portability would be less of a concern for mobile computers installed in the dashboards of cars than with hand-held mobile computers. However, the authors concentrate on the goal of large-scale, hand-held mobile computing as a way to reveal a wide assortment of issues. >
988Â citations
TL;DR: A calibrated, high-quality disk drive model is demonstrated in which the overall error factor is 14 times smaller than that of a simple first-order model, which enables an informed trade-off between effort and accuracy.
Abstract: Although disk storage densities are improving impressively (60% to 130% compounded annually), performance improvements have been occurring at only about 7% to 10% compounded annually over the last decade. As a result, disk system performance is fast becoming a dominant factor in overall svstem behavior. Naturally, researchers want to improve overall I/O performance, of which a large component is the performance of the disk drive itself. This research often involves using analytical or simulation models to compare alternative approaches, and the quality of these models determines the quality of the conclusions: indeed, the wrong modeling assumptions can lead to erroneous conclusions. Nevertheless, little work has been done to develop or describe accurate disk drive models. This may explain the commonplace use of simple, relatively inaccurate models. We believe there is much room for improvement. This article demonstrates and describes a calibrated, high-quality disk drive model in which the overall error factor is 14 times smaller than that of a simple first-order model. We describe the various disk drive performance components separately, then show how their inclusion improves the simulation model. This enables an informed trade-off between effort and accuracy. In addition, we provide detailed characteristics for two disk drives, as well as a brief description of a simulation environment that uses the disk drive model. >
938Â citations
TL;DR: The authors describe the architectural assumptions, fault hypothesis, and objectives for the TTP protocol, and discuss TTP characteristics and compare its performance with that of other protocols proposed for control applications.
Abstract: The Time-Triggered Protocol integrates such services as predictable message transmission, clock synchronization, membership, mode change, and blackout handling. It also supports replicated nodes and replicated communication channels. The authors describe their architectural assumptions, fault hypothesis, and objectives for the TTP protocol. After they elaborate on its rationale, they give a detailed protocol description. They also discuss TTP characteristics and compare its performance with that of other protocols proposed for control applications. >
509Â citations
TL;DR: Software complexity metrics rarely measure the "inherent complexity" embedded in software systems, but they do a very good job of comparing the relative complexity of one portion of a system with another.
Abstract: Software metrics have been much criticized in the last few years, sometimes justly but more often unjustly, because critics misunderstand the intent behind the technology. Software complexity metrics, for example, rarely measure the "inherent complexity" embedded in software systems, but they do a very good job of comparing the relative complexity of one portion of a system with another. In essence, they are good modeling tools. Whether they are also good measuring tools depends on how consistently and appropriately they are applied. >
451Â citations
TL;DR: The network concepts underlying MBone, the importance of bandwidth considerations, various application tools, MBone events, interesting MBone uses, and guidance on how to connect your Internet site to the MBone are described.
Abstract: Researchers have produced the Multicast Backbone (MBone), which provides audio and video connectivity from outer space to under water/spl minus/and virtually everyplace in between. MBone is a virtual network that has been in existence since early 1992. It originated from an effort to multicast audio and video from meetings of the Internet Engineering Task Force. Today. hundreds of researchers use MBone to develop protocols and applications for group communication. Multicast provides one-to-many and many-to-many network delivery services for applications such as videoconferencing and audio where several hosts need to communicate simultaneously. This article describes the network concepts underlying MBone, the importance of bandwidth considerations, various application tools, MBone events, interesting MBone uses, and provides guidance on how to connect your Internet site to the MBone. >
423Â citations
TL;DR: This article describes a caching strategy that offers the performance of caches twice its size and investigates three cache replacement algorithms: random replacement, least recently used, and a frequency-based variation of LRU known as segmented LRU (SLRU).
Abstract: I/O subsystem manufacturers attempt to reduce latency by increasing disk rotation speeds, incorporating more intelligent disk scheduling algorithms, increasing I/O bus speed, using solid-state disks, and implementing caches at various places in the I/O stream. In this article, we examine the use of caching as a means to increase system response time and improve the data throughput of the disk subsystem. Caching can help to alleviate I/O subsystem bottlenecks caused by mechanical latencies. This article describes a caching strategy that offers the performance of caches twice its size. After explaining some basic caching issues, we examine some popular caching strategies and cache replacement algorithms, as well as the advantages and disadvantages of caching at different levels of the computer system hierarchy. Finally, we investigate the performance of three cache replacement algorithms: random replacement (RR), least recently used (LRU), and a frequency-based variation of LRU known as segmented LRU (SLRU). >
325Â citations
IBM1
TL;DR: This work restricts itself to the support provided at the server, with special emphasis on two service phases: disk scheduling and SCSI bus contention, and analyze how trade-offs that involve buffer space affect the performance of scheduling policies.
Abstract: In future computer system design, I/O systems will have to support continuous media such as video and audio, whose system demands are different from those of data such as text. Multimedia computing requires us to focus on designing I/O systems that can handle real-time demands. Video- and audio-stream playback and teleconferencing are real-time applications with different I/O demands. We primarily consider playback applications which require guaranteed real-time I/O throughput. In a multimedia server, different service phases of a real-time request are disk, small computer systems interface (SCSI) bus, and processor scheduling. Additional service might be needed if the request must be satisfied across a local area network. We restrict ourselves to the support provided at the server, with special emphasis on two service phases: disk scheduling and SCSI bus contention. When requests have to be satisfied within deadlines, traditional real-time systems use scheduling algorithms such as earliest deadline first (EDF) and least slack time first. However, EDF makes the assumption that disks are preemptable, and the seek-time overheads of its strict real-time scheduling result in poor disk utilization. We can provide the constant data rate necessary for real-time requests in various ways that require trade-offs. We analyze how trade-offs that involve buffer space affect the performance of scheduling policies. We also show that deferred deadlines, which increase buffer requirements, improve system performance significantly. >
308Â citations
TL;DR: This review classifies genetic-algorithm environments into application-oriented systems, algorithm- oriented systems, and toolkits, and presents detailed case studies of leading environments, discussing likely future developments in GA programming environments.
Abstract: This review classifies genetic-algorithm environments into application-oriented systems, algorithm-oriented systems, and toolkits. It also presents detailed case studies of leading environments. Following Holland's (1975) original genetic algorithm proposal, many variations of the basic algorithm have been introduced. However. an important and distinctive feature of all GAs is the population-handling technique. The original GA adopted a generational replacement policy, according to which the whole population is replaced in each generation. Conversely, the steady-state policy used by many subsequent GAs selectively replaces the population. After we introduce GA models and their programming, we present a survey of GA programming environments. We have grouped them into three major classes according to their objectives: application-oriented systems hide the details of GAs and help users develop applications for specific domains; algorithm-oriented systems are based on specific GA models; and toolkits are flexible environments for programming a range of GAs and applications. We review the available environments and describe their common features and requirements. As case studies, we select some specific systems for more detailed examination. To conclude, we discuss likely future developments in GA programming environments. >
306Â citations
TL;DR: It is shown that cache profiling, using the CProf cache profiling system, improves program performance by focusing a programmer's attention on problematic code sections and providing insight into appropriate program transformations.
Abstract: A vital tool-box component, the CProf cache profiling system lets programmers identify hot spots by providing cache performance information at the source-line and data-structure level. Our purpose is to introduce a broad audience to cache performance profiling and tuning techniques. Although used sporadically in the supercomputer and multiprocessor communities, these techniques also have broad applicability to programs running on fast uniprocessor workstations. We show that cache profiling, using our CProf cache profiling system, improves program performance by focusing a programmer's attention on problematic code sections and providing insight into appropriate program transformations. >
TL;DR: Basic algorithms to extract coherent amorphous regions (features or objects) from 2 and 3D scalar and vector fields and then track them in a series of consecutive time steps are described.
Abstract: We describe basic algorithms to extract coherent amorphous regions (features or objects) from 2 and 3D scalar and vector fields and then track them in a series of consecutive time steps. We use a combination of techniques from computer vision, image processing, computer graphics, and computational geometry and apply them to data sets from computational fluid dynamics. We demonstrate how these techniques can reduce visual clutter and provide the first step to quantifying observable phenomena. These results can be generalized to other disciplines with continuous time-dependent scalar (and vector) fields. >
TL;DR: This article demonstrates that simple and natural parallelizations work very well, the sequential implementations do not have to be fundamentally restructured, and the high degree of temporal locality obviates the need for explicit data distribution and communication management on the best known visualization algorithms.
Abstract: Recently, a new class of scalable, shared-address-space multiprocessors has emerged. Like message-passing machines, these multiprocessors have a distributed interconnection network and physically distributed main memory. However, they provide hardware support for efficient implicit communication through a shared address space, and they automatically exploit temporal locality by caching both local and remote data in a processor's hardware cache. In this article, we show that these architectural characteristics make it much easier to obtain very good speedups on the best known visualization algorithms. Simple and natural parallelizations work very well, the sequential implementations do not have to be fundamentally restructured, and the high degree of temporal locality obviates the need for explicit data distribution and communication management. We demonstrate our claims through parallel versions of three state-of-the-art algorithms: a recent hierarchical radiosity algorithm by Hanrahan et al. (1991), a parallelized ray-casting volume renderer by Levoy (1992), and an optimized ray-tracer by Spach and Pulleyblank (1992). We also discuss a new shear-warp volume rendering algorithm that provides the first demonstration of interactive frame rates for a 256/spl times/256/spl times/256 voxel data set on a general-purpose multiprocessor. >
TL;DR: Glyphmaker allows nonexpert users to customize their own graphical representations using a simple glyph editor and a point-and-click binding mechanism, letting them employ their specialized domain knowledge to create customized visual representations for further exploration and analysis.
Abstract: Glyphmaker allows nonexpert users to customize their own graphical representations using a simple glyph editor and a point-and-click binding mechanism. In particular, users can create and then alter bindings to visual representations, bring in new data or glyphs with associated bindings, change ranges for bound data, and do these operations interactively. They can also focus on data down to any level of detail, including individual elements, and then isolate or highlight the focused region. These features empower users, letting them employ their specialized domain knowledge to create customized visual representations for further exploration and analysis. For ease of design and use, we built Glyphmaker on top of Iris Explorer, the Silicon Graphics Inc. (SGI) dataflow visualization system. The current version of Glyphmaker has been successfully tested on a materials system simulation. We are planning a series of tests and evaluations by scientists and engineers using real data. >
TL;DR: The authors provide a CSCW taxonomy that defines and describes criteria for identifying CSCw systems and serves as a basis for defining C SCW system requirements.
Abstract: Building efficient frameworks for computer-supported cooperative work requires different approaches. The combination of CSCW transparency and awareness produces an advanced environment adaptable to specific applications. The authors provide a CSCW taxonomy that defines and describes criteria for identifying CSCW systems and serves as a basis for defining CSCW system requirements. They consider how the psychological, social, and cultural processes active within groups of collaborators are the real keys to the acceptance and success of CSCW systems. >
TL;DR: The uses of a dataflow coverage-testing tool for C programs-called ATAC for Automatic Test Analysis for C/sup 3/-in measuring, controlling, and understanding the testing process are described.
Abstract: Coverage testing helps the tester create a thorough set of tests and gives a measure of test completeness. The concepts of coverage testing are well-described in the literature. However, there are few tools that actually implement these concepts for standard programming languages, and their realistic use on large-scale projects is rare. In this article, we describe the uses of a dataflow coverage-testing tool for C programs-called ATAC for Automatic Test Analysis for C/sup 3/-in measuring, controlling,and understanding the testing process. We present case studies of two real-world software projects using ATAC. The first study involves 12 program versions developed by a university/industry fault-tolerant software project for a critical automatic-flight-control system. The second study involves a Bellcore project of 33 program modules. These studies indicate that coverage analysis of programs during testing not only gives a clear measure of testing quality but also reveals important aspects of software structure. Understanding the structure of a program, as revealed in coverage testing, can be a significant component in confident assessment of overall software quality. >
TL;DR: Providing the I/O infrastructure that will support these requirements will necessitate research in operating systems, language interfaces to high-performance storage systems, high-speed networking, graphics and visualization systems, and new hardware technology for I/o and storage systems.
Abstract: Over the past two decades (1974-94), advances in semiconductor and integrated circuit technology have fuelled the drive toward faster, ever more efficient computational machines. Today, the most powerful supercomputers can perform computation at billions of floating-point operations per second (gigaflops). This increase in capability is intensifying the demand for even more powerful machines. Computational limits for the largest supercomputers are expected to exceed the teraflops barrier in the coming years. Discussion is given on the following areas: the nature of I/O in massive parallel processing; operating and file systems; runtime system and compilers; and networking technology. The recurrent themes in the parallel I/O problem are the existence of a great variety in access patterns and the sensitivity of current I/O systems to these access patterns. An increase in the variability of access patterns is also expected, and single resource-management approaches will likely not suffice. Providing the I/O infrastructure that will support these requirements will necessitate research in operating systems (parallel file systems, runtime systems, and drivers), language interfaces to high-performance storage systems, high-speed networking, graphics and visualization systems, and new hardware technology for I/O and storage systems. >
TL;DR: The authors focus on meeting the deadlines of synchronous messages in the timed-token protocol, a token-passing protocol in which each node receives a guaranteed share of the network bandwidth.
Abstract: The timed-token protocol is a token-passing protocol in which each node receives a guaranteed share of the network bandwidth. Partly because of this property, the timed-token protocol has been incorporated into a number of network standards, including the IEEE 802.4 token bus, the Fiber Distributed Data Interface (FDDI), and the Survivable Adaptable Fiber Optic Embedded Network (Safenet). Networks based on these standards are becoming increasingly popular in new generation real-time systems. In particular, the IEEE 802.4 standard is included in the Manufacturing Automation Protocol (MAP), which has been widely used in computer-integrated manufacturing and industrial applications. Meeting message deadlines requires proper control of medium access. In the timed-token protocol, access to the communication medium is controlled by a token that is passed among the nodes in a circular fashion. Messages are segregated into two separate classes: synchronous and asynchronous. Synchronous messages, used for real-time communication, can have deadline constraints and thus are given a guaranteed share of the network bandwidth. The authors focus on meeting the deadlines of synchronous messages. >
TL;DR: Disk arrays are an essential tool for satisfying storage performance and reliability requirements, while proper selection of a data organization can tailor an array to a particular environment.
Abstract: As the performance of other system components continues to improve rapidly, storage subsystem performance becomes increasingly important. Storage subsystem performance and reliability can be enhanced by logically grouping multiple disk drives into disk arrays. Array data organizations are defined by their data distribution schemes and redundancy mechanisms. The various combinations of these two components make disk arrays suitable for a wide range of environments. Many array implementation decisions also result in trade-offs between performance and reliability. Disk arrays are thus an essential tool for satisfying storage performance and reliability requirements, while proper selection of a data organization can tailor an array to a particular environment. >
TL;DR: Two distributed visualization algorithms and the facilities that enable collaborative visualization are described, implemented on top of the distribution and collaboration mechanisms of an environment called Shastra, executing on a set of low-cost networked workstations.
Abstract: Visualization typically involves large computational tasks, often performed on supercomputers. The results of these tasks are usually analyzed by a design team consisting of several members. Our goal is to depart from traditional single-user systems and build a low-cost scientific visualization environment that enables computer-supported cooperative work in the distributed setting. A synchronously conferenced collaborative visualization environment would let multiple users on a network of workstations and supercomputers share large data sets, simultaneously view visualizations of the data, and interact with multiple views while varying parameters. Such an environment would support collaboration in both the problem-solving phase and the review phase of design tasks. In this article we describe two distributed visualization algorithms and the facilities that enable collaborative visualization. These are all implemented on top of the distribution and collaboration mechanisms of an environment called Shastra, executing on a set of low-cost networked workstations. >
TL;DR: The author first describes the organization of a typical network interface and discusses performance considerations for interfaces to high-speed networks, and discusses software optimizations that apply to simple network adapters and how more powerful adapters can improve performance on high- speed networks.
Abstract: Optical fiber has made it possible to build networks with link speeds of over a gigabit per second; however, these networks are pushing end-systems to their limits. For high-speed networks (100 Mbits per second and up), network throughput is typically limited by software overhead on the sending and receiving hosts. Minimizing this overhead improves application-level latency and throughput and reduces the number of cycles that applications lose to communication overhead. Several factors influence communication overhead: communication protocols, the application programming interface (API). and the network interface hardware architecture. The author describes how these factors influence communication performance and under what conditions hardware support on the network adapter can reduce overhead. He first describes the organization of a typical network interface and discusses performance considerations for interfaces to high-speed networks. He then discusses software optimizations that apply to simple network adapters and show how more powerful adapters can improve performance on high-speed networks. >
TL;DR: The authors assess the architectural characteristics deemed necessary for the ATM switch, providing an overview of its purpose and protocols, and summarize key ATM switch proposals, which summarize commercial market requirements and profile several commercially available systems to show the current gap between the research community and the commercial market.
Abstract: The asynchronous transfer mode (ATM) promises to be the ultimate on-premise internetworking technology. Its high-bandwidth uniform switches can transfer graphics, audio, video. and text from application to application at much higher speeds than now available. In fact, ATM may well be the technology that brings the computer and communications industries together. Because ATM as a public service offering by telecommunications companies will probably not be in place before 1996-1997, the authors focus on the ATM LAN and the corporate backbone. Most of the proposals on the internal architecture of the ATM switch are still at a research-and-evaluation stage, based on the switching architectures of the 1970s and 198Os. Various objectives, such as blocking, routing, performance and VLSI implementation, motivated past work. Although these attributes are essential, they don't address concerns important to the commercial ATM market, such as the general cost of ownership and incremental deployment, scalability, reliability, and efficient bandwidth utilization. The few ATM switches on the market today embody attributes that meet current demands but must evolve to meet the future. The authors assess the architectural characteristics deemed necessary for the ATM switch, providing an overview of its purpose and protocols, and summarize key ATM switch proposals. They summarize commercial market requirements and profile several commercially available systems to show the current gap between the research community and the commercial market, providing a model for the future. >
TL;DR: Basic measures for performance of a software-development organization are defined, limited ourselves to a small number of simple measures to reduce the complexity of collecting, analyzing, and maintaining the performance data.
Abstract: Describes an ongoing research project conducted jointly by Siemens and the Software Engineering Institute. Siemens software-development organizations in Germany and the United States are case-study sites at which we measure the effect of methods to improve the software-development process. To observe and quantify the impact of software-process improvement, we must measure the performance of a software-development organization over time. Comparison of performance across organizations is very difficult, since organizations define measures and collect performance data in different ways. However, we can separately track performance improvement in each organization if it defines measures consistently and develops similar products. We have defined basic measures for performance of a software-development organization. We limited ourselves to a small number of simple measures to reduce the complexity of collecting, analyzing, and maintaining the performance data. Improving the software-development process improves the quality of software products and the overall performance of the software-development organization. However, process is only one of several controllable factors in improving software quality and organization performance. Others include the skills and experience of the people developing the software, the technology used (e.g. CASE tools), product complexity, and environmental characteristics such as schedule pressure and communications. >
TL;DR: A parallel programming paradigm called ASC (ASsociative Computing), designed for a wide range of computing engines, that incorporates data parallelism at the base level, so that programmers do not have to specify low-level sequential tasks such as sorting, looping and parallelization.
Abstract: Today's increased computing speeds allow conventional sequential machines to effectively emulate associative computing techniques We present a parallel programming paradigm called ASC (ASsociative Computing), designed for a wide range of computing engines Our paradigm has an efficient associative-based, dynamic memory-allocation mechanism that does not use pointers It incorporates data parallelism at the base level, so that programmers do not have to specify low-level sequential tasks such as sorting, looping and parallelization Our paradigm supports all of the standard data-parallel and massively parallel computing algorithms It combines numerical computation (such as convolution, matrix multiplication, and graphics) with nonnumerical computing (such as compilation, graph algorithms, rule-based systems, and language interpreters) This article focuses on the nonnumerical aspects of ASC >
TL;DR: The author illustrates an analysis methodology, rate monotonic analysis, for managing real-time requirements in a distributed industrial computing situation, based on a comprehensive robotics example drawn from a typical industrial application.
Abstract: Issues of real-time resource management are pervasive throughout industrial computing. The underlying physical processes of many industrial computing applications impose explicit timing requirements on the tasks processed by the computer system. These timing requirements are an integral part of the correctness and safety of a real-time system. It is tempting to think that speed (for example, processor speeds or higher communication bandwidths) is the sole ingredient in meeting system timing requirements, but speed alone is not enough. Proper resource-management techniques also must be used to prevent, for example, situations in which long, low priority tasks block higher priority tasks with short deadlines. One guiding principle in real-time system resource management is predictability, the ability to determine for a given set of tasks whether the system will be able to meet all of the timing requirements of those tasks. Predictability calls for the development of scheduling models and analytic techniques to determine whether or not a real-time system can meet its timing requirements. The author illustrates an analysis methodology, rate monotonic analysis, for managing real-time requirements in a distributed industrial computing situation. The illustration is based on a comprehensive robotics example drawn from a typical industrial application. >
TL;DR: The authors present their cosynthesis approach, and specify system behavior using HardwareC, a hardware description language (HDL) that has a C-like syntax and supports timing and resource constraints and supports specification of unbounded and unknown delay operations that can arise from data-dependent decisions and external synchronization operations.
Abstract: Recent advances in the design and synthesis of integrated circuits have prompted system architects to investigate computer aided design methods for systems that contain both application-specific and predesigned reprogrammable components. For the most part, we can apply high level synthesis techniques to synthesis of systems containing processors by treating the latter as a generalized resource. However, the problem is more complex, since the software on the processor implements system functionality in an instruction-driven manner with a statically allocated memory space, whereas ASICs operate as data driven reactive elements. Due to these differences in computational models and primitive operations in hardware and software, a new formulation of the problem of cosynthesis is needed. The authors present their cosynthesis approach. They specify system behavior using HardwareC, a hardware description language (HDL) that has a C-like syntax and supports timing and resource constraints. It also supports specification of unbounded and unknown delay operations that can arise from data-dependent decisions and external synchronization operations. The particular choice of a HDL to specify system functionality is immaterial for the cosynthesis formulation here, and other HDLs such as Verilog could be used. >
TL;DR: The word success is very powerful; it creates strong, but widely varied, images that may range from the final seconds of an athletic contest to a graduation ceremony to the loss of 10 pounds.
Abstract: The word success is very powerful. It creates strong, but widely varied, images that may range from the final seconds of an athletic contest to a graduation ceremony to the loss of 10 pounds. Success makes us feel good; it's cause for celebration. All these examples of success are marked by a measurable end point, whether externally or self-created. Most of us who create software approach projects with some similar idea of success. Our feelings from project start to end are often strongly influenced by whether we spent any early time describing this success and how we might measure progress. Software metrics measure specific attributes of a software product or a software development process. In other words, they are measures of success. It's convenient to group the ways that we apply metrics to measure success into four areas. What do you need to measure and analyze to make your project a success? We show examples from many projects and Hewlett Packard divisions which may help you chart your course. >
TL;DR: Multithreading offers a viable alternative for building hybrid architectures that exploit parallelism and more research is still needed to develop compilers for conventional languages that can produce parallel code comparable to that of parallel functional languages.
Abstract: Contrary to initial expectations, implementing dataflow computers has presented a monumental challenge Now, however, multithreading offers a viable alternative for building hybrid architectures that exploit parallelism The eventual success of dataflow computers will depend on their programmability Traditionally, they've been programmed in languages such as Id and SISAL (Streams and Iterations in a Single Assignment Language) that use functional semantics These languages reveal high levels of concurrency and translate on to dataflow machines and conventional parallel machines via the Threaded Abstract Machine (TAM) However, because their syntax and semantics differ from the imperative counterparts such as Fortran and C, they have been slow to gain acceptance in the programming community An alternative is to explore the use of established imperative languages to program dataflow machines However, the difficulty will be analyzing data dependencies and extracting parallelism from source code that contains side effects Therefore, more research is still needed to develop compilers for conventional languages that can produce parallel code comparable to that of parallel functional languages >
TL;DR: Associative memory provides a naturally parallel and scalable form of data retrieval for both structured data and unstructured data, and can be easily extended to process the retrieved data in place, thus becoming an associative processor.
Abstract: Associative memory concerns the concept that one idea may trigger the recall of a different but related idea. Traditional computers, however, rely upon a memory design that stores and retrieves data by its address rather than its content. In such a search, every accessed data word must travel individually between the processing unit and the memory. The simplicity of this retrieval-by-address approach has ensured its success, but has also produced some inherent disadvantages. One is the von Neumann bottleneck, where the memory-access path becomes the limiting factor for system performance. A related disadvantage is the inability to proportionally increase the size of a unit transfer between the memory and the processor as the size of the memory scales up. Associative memory, in contrast, provides a naturally parallel and scalable form of data retrieval for both structured data (e.g. sets, arrays, tables, trees and graphs) and unstructured data (raw text and digitized signals). An associative memory can be easily extended to process the retrieved data in place, thus becoming an associative processor. This extension is merely the capability for writing a value in parallel into selected cells. >