IEEE Design & Test of Computers
Institute of Electrical and Electronics Engineers
About: IEEE Design & Test of Computers is an academic journal published by Institute of Electrical and Electronics Engineers. The journal publishes majorly in the area(s): Automatic test pattern generation & Electronic design automation. It has an ISSN identifier of 0740-7475. Over the lifetime, 1849 publications have been published receiving 63220 citations. The journal is also known as: IEEE design and test & Design and test of computers.
Topics: Automatic test pattern generation, Electronic design automation, Fault coverage, Design for testing, System on a chip
Papers published on a yearly basis
TL;DR: A classification of hardware Trojans and a survey of published techniques for Trojan detection are presented.
Abstract: Editor's note:Today's integrated circuits are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. This article presents a classification of hardware Trojans and a survey of published techniques for Trojan detection.
TL;DR: The AEthereal NoC is introduced, which provides guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs and exploits the NoC capacity unused by the GS traffic.
Abstract: The continuous advances in semiconductor technology enable the integration of increasing numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches, and networks on chips (NoCs), combine the IPs into a working SoC. Moreover, the industry expects platform-based SoC design to evolve to communication-centric design, with NoCs as a central enabling technology. In this article, we introduce the AEthereal NoC. The tenet of the AEthereal NoC is that guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs. To exploit the NoC capacity unused by the GS traffic, we provide best-effort services.
TL;DR: In this paper, the authors present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule.
Abstract: This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-/spl mu/m technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-/spl mu/m through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.
TL;DR: This article comprehensively analyzes soft-error sensitivity in modern systems and shows it to be application dependent.
Abstract: As the dimensions and operating voltages of computer electronics shrink to satisfy consumers' insatiable demand for higher density, greater functionality, and lower power consumption, sensitivity to radiation increases dramatically. In terrestrial applications, the predominant radiation issue is the soft error, whereby a single radiation event causes a data bit stored in a device to be corrupted until new data is written to that device. This article comprehensively analyzes soft-error sensitivity in modern systems and shows it to be application dependent. The discussion covers ground-level radiation mechanisms that have the most serious impact on circuit operation along with the effect of technology scaling on soft-error rates in memory and logic.
TL;DR: It is argued that power-aware methodology uses an embedded microoperating system to reduce node energy consumption by exploiting both sleep state and active power management.
Abstract: We propose an OS-directed power management technique to improve the energy efficiency of sensor nodes. Dynamic power management (DPM) is an effective tool in reducing system power consumption without significantly degrading performance. The basic idea is to shut down devices when not needed and wake them up when necessary. DPM, in general, is not a trivial problem. If the energy and performance overheads in sleep-state transition were negligible, then a simple greedy algorithm that makes the system enter the deepest sleep state when idling would be perfect. However, in reality, sleep-state transitioning has the overhead of storing processor state and turning off power. Waking up also takes a finite amount of time. Therefore, implementing the correct policy for sleep-state transitioning is critical for DPM success. It is argued that power-aware methodology uses an embedded microoperating system to reduce node energy consumption by exploiting both sleep state and active power management.