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Showing papers in "IEEE Design & Test of Computers in 1998"


Journal ArticleDOI
TL;DR: It is argued that new methodologies and AD tools support an integrated hardware software codesign process that begins before the system architecture is finalised.
Abstract: Ever increasing embedded system design complexity combined with a very tight time-to-market window has revolutionized the embedded-system design process. The concurrent design of hardware and software has displaced traditional sequential design. Further, hardware and software design now begins before the system architecture (or even the specification) is finalised. System architects, customers, and marketing departments develop requirement definitions and system specifications together. System architects define a system architecture consisting of cooperating system functions that form the basis of concurrent hardware and software design. Interface design requires the participation of both hardware and software developers. The next step integrates and tests hardware and software-this phase consists of many individual steps. Reusing components taken from previous designs or acquired from outside the design group is a main design goal to improve productivity and reduce design risk. It is argued that new methodologies and AD tools support an integrated hardware software codesign process.

199 citations


Journal ArticleDOI
TL;DR: The authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.
Abstract: Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

169 citations


Journal ArticleDOI
TL;DR: The authors review several approaches to control-oriented and dataflow-oriented software scheduling to determine whether a given technique can satisfy deadlines, throughput, and other constraints for embedded real-time systems.
Abstract: The authors review several approaches to control-oriented and dataflow-oriented software scheduling to determine whether a given technique can satisfy deadlines, throughput, and other constraints for embedded real-time systems.

138 citations


Journal ArticleDOI
TL;DR: The logic blocks of most FPGAs contain clusters of lookup tables and flip-flops yet little is known about good choices for key parameters and how many inputs should programmable routing provide each cluster.
Abstract: The logic blocks of most FPGAs contain clusters of lookup tables and flip-flops yet little is known about good choices for key parameters. How many lookup tables should a cluster contain, how should FPGA routing flexibility change as cluster size changes, and how many inputs should programmable routing provide each cluster?.

101 citations


Journal ArticleDOI
TL;DR: The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.
Abstract: Delay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.

91 citations


Journal ArticleDOI
TL;DR: A verification metric, noise stability, which guarantees functionality in the presence of noise, and a CAD technique, static noise analysis, for applying this metric on a chipwide basis are described.
Abstract: As feature sizes decrease and clock frequencies increase, noise is becoming a greater concern in digital IC design. The authors describe a verification metric, noise stability, which guarantees functionality in the presence of noise, and a CAD technique, static noise analysis, for applying this metric on a chipwide basis.

83 citations


Journal ArticleDOI
TL;DR: This work focuses on online built-in self-test and its role in a comprehensive testing approach for identifying faults that can lead to system failure.
Abstract: Embedded systems must meet increasingly high expectations of safety and high reliability. The authors survey online-testing techniques for identifying faults that can lead to system failure. They focus on online built-in self-test and its role in a comprehensive testing approach.

78 citations


Journal ArticleDOI
TL;DR: Focusing on configurable logic blocks in a lookup table FPGA, the authors present universal fault diagnosis procedures that can locate a fault to just one CLB.
Abstract: Focusing on configurable logic blocks in a lookup table FPGA, the authors present universal fault diagnosis procedures that can locate a fault to just one CLB. The complexity of the proposed procedure for FPGAs using block-sliced loading is independent of FPGA array size.

67 citations


Journal ArticleDOI
A. Carbine1, D. Feltham
TL;DR: The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led this design team to a custom, low-area DFT approach and a manually written test methodology that targeted several fault models.
Abstract: The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led this design team to a custom, low-area DFT approach and a manually written test methodology that targeted several fault models. Their approach effectively balanced testability needs with other design constraints, while enabling excellent time to market and test quality.

66 citations


Journal ArticleDOI
TL;DR: Using transferred circuits and metal interconnections placed between layers of active devices anywhere on the chip, Rothko aims at solving utilization, routing, and delay problems of existing FPGA architectures.
Abstract: Using transferred circuits and metal interconnections placed between layers of active devices anywhere on the chip, Rothko aims at solving utilization, routing, and delay problems of existing FPGA architectures. Experimental implementations have demonstrated important performance advantages.

51 citations


Journal ArticleDOI
TL;DR: Today's increased power and packaging densities demand designers' attention to the effects of heat on ICs, and the concept and techniques of design for thermal testability are reviewed.
Abstract: Today's increased power and packaging densities demand designers' attention to the effects of heat on ICs. The authors review thermal and electrothermal simulation and measurement methods, thermal package characterization, and the concept and techniques of design for thermal testability.

Journal ArticleDOI
TL;DR: This implementation of a two-dimensional discrete cosine transform demonstrates the development of a suitable architectural style for a specific technology-in this case, the Xilinx XC6200 FPGA series.
Abstract: This implementation of a two-dimensional discrete cosine transform demonstrates the development of a suitable architectural style for a specific technology-in this case, the Xilinx XC6200 FPGA series. The design exploits distributed arithmetic, parallelism, and pipelining to achieve high-performance custom-computing implementation.

Journal ArticleDOI
TL;DR: The DFT features support static voltage-level testing for wafer-sort and debug testing, application of two pattern sequences for detection of timing-related failures, scan-based BIST, and 1149.1 boundary scan.
Abstract: The AMD-K6's embedded design-for-testability structures and test pattern development methodologies provide high-quality manufacturing tests. The DFT features support static voltage-level testing for wafer-sort and debug testing, application of two pattern sequences for detection of timing-related failures, scan-based BIST, and 1149.1 boundary scan.

Journal ArticleDOI
TL;DR: This generic BIST scheme does not require DFT modifications in the multiplier structure, guarantees fault coverage higher than 99%, and can be adopted by any module generator.
Abstract: Booth multipliers, widely used as embedded cores in general-purpose data path structures and specialized digital signal processors, pose serious testability problems This generic BIST scheme does not require DFT modifications in the multiplier structure, guarantees fault coverage higher than 99%, and can be adopted by any module generator

Journal ArticleDOI
TL;DR: Matisse is an architectural design tool that increases productivity without sacrificing area, performance, or power and supports the diverse design practices required for commodity IC design by giving the designer fine-grain control of behavioral synthesis tasks.
Abstract: To accelerate industrial adoption of behavioral synthesis, we have developed Matisse, an architectural design tool that increases productivity without sacrificing area, performance, or power. Matisse's main difference from traditional behavioral synthesis tools is that it lets the designer play a key role. It allows the designer to make major decisions about styles, protocols, parallelism, delays, and partial or even complete architectures before the behavioral synthesis phase starts. Then it enables the designer to incorporate these decisions into the architecture using behavioral synthesis. Matisse supports the diverse design practices required for commodity IC design by giving the designer fine-grain control of behavioral synthesis tasks.

Journal ArticleDOI
TL;DR: Refinements to testing strategies for earlier microprocessor on-chip caches led to fast, efficient characterization and debugging of the smaller geometry PA8500 cache.
Abstract: Refinements to testing strategies for earlier microprocessor on-chip caches led to fast, efficient characterization and debugging of the smaller geometry PA8500 cache.

Journal ArticleDOI
TL;DR: The SUAVE project extends the language with object-orientation and genericity features and generalizes some existing features and adapted most of the added features from Ada-95, largely for the same reasons they were included in that language.
Abstract: Our aim in the SUAVE (SAVANT and University of Adelaide VHDL Extensions) Project is to improve support for high-level modeling and reuse in VHDL. A number of previous proposals also address these goals. SUAVE extends the language with object-orientation and genericity features and generalizes some existing features. Extending VHDL in this way has the side effect of improving its expressiveness at all abstraction levels. We adapted most of the added features from Ada-95, largely for the same reasons they are included in that language.

Journal Article

Journal ArticleDOI
TL;DR: The RPM-2 multiprocessor emulator uses this approach to achieve much greater flexibility and observability at less cost than typical hardware prototypes.
Abstract: Hardware emulation using FPGAs is an intermediate approach between software simulation and hardware prototyping. The RPM-2 multiprocessor emulator uses this approach to achieve much greater flexibility and observability at less cost than typical hardware prototypes.

Journal ArticleDOI
B. Bottoms1
TL;DR: The president and CEO of Credence Systems, Bill Bottoms, addressed the VLSI test symposium held last April in Monterey, California and covered some of the challenges test engineers must face in the future.
Abstract: The president and CEO of Credence Systems, Bill Bottoms, addressed the VLSI test symposium held last April in Monterey, California. His keynote covered some of the challenges test engineers must face in the future. Specifically, Bottoms focused on what's driving the increase in test cost and what the industry can do about it.

Journal ArticleDOI
TL;DR: The authors present a new method and self-checking circuit implementation for concurrently checking the correctness of clock distribution network signals in synchronous systems.
Abstract: Traditional concurrent-checking techniques may not detect the occurrence of the transient faults and resulting errors likely to affect clock signals in VLSI systems. The authors present a new method and self-checking circuit implementation for concurrently checking the correctness of clock distribution network signals in synchronous systems.

Journal ArticleDOI
TL;DR: Integrating packaging trade-off analysis with functional verification and architectural design results in a complete virtual prototyping solution far optimizing complex electronic systems.
Abstract: Integrating packaging trade-off analysis with functional verification and architectural design results in a complete virtual prototyping solution far optimizing complex electronic systems. The authors discuss the role of packaging costs in system design and present examples highlighting packaging design trade-offs.

Journal ArticleDOI
M. Scheffler1, D. Ammann, A. Thiel, C. Habiger, G. Troster 
TL;DR: A process-oriented, scalable cost-modeling tool, the Modular Optimization Environment (MOE), enables a continuous cost-quality-performance trade-off analysis throughout the design and manufacturing process.
Abstract: Today's high-density packaging technologies make early attention to most factors essential in the design of successful products. A process-oriented, scalable cost-modeling tool, the Modular Optimization Environment (MOE), enables a continuous cost-quality-performance trade-off analysis throughout the design and manufacturing process.

Journal ArticleDOI
TL;DR: This paper provides an approach that allows observation and control of DC voltage levels of all test points simultaneously, with a calibration process that ensures accuracy.
Abstract: No previously proposed analog built-in self-test method allows simultaneous control of all test points, the basic diagnosis capability required for analog circuits. This paper provides an approach that allows observation and control of DC voltage levels of all test points simultaneously, with a calibration process that ensures accuracy.

Journal ArticleDOI
TL;DR: It is demonstrated that an integrated synthesis and partitioning methodology is crucial to achieving high-density designs with varying structural characteristics and HDL coding styles.
Abstract: The authors examine the interaction of HDL synthesis and multi-FPGA partitioning on designs with varying structural characteristics and HDL coding styles They demonstrate that an integrated synthesis and partitioning methodology is crucial to achieving high-density designs

Journal ArticleDOI
TL;DR: Experiments on test FPGAs show that laser defect avoidance produces signal delays half those of active switches, indicating the complexity limits of field-programmable gate arrays.
Abstract: Wafer-scale techniques of defect avoidance expend the complexity limits of field-programmable gate arrays by routing around flawed blocks to build working systems. Experiments on test FPGAs show that laser defect avoidance produces signal delays half those of active switches.

Journal ArticleDOI
TL;DR: The authors propose an approach for fault analysis and simulation of networks designed to have concurrent detection properties that characterizes all faults that may affect a device and determines the coverage, extracting test vectors and other parameters for evaluating device quality.
Abstract: The authors propose an approach for fault analysis and simulation of networks designed to have concurrent detection properties. The analysis characterizes all faults that may affect a device and determines the coverage, extracting test vectors and other parameters for evaluating device quality.


Journal ArticleDOI
TL;DR: The authors present test strategies used in the space flight computer designed for NASA's Deep Space-1 mission, which poses major testing challenges for complex designs.
Abstract: Advanced packaging technologies pose major testing challenges for complex designs. The authors present test strategies used in the space flight computer designed for NASA's Deep Space-1 mission.

Journal ArticleDOI
TL;DR: A circuit used in a telephone switching unit features several test techniques, including BIST, partial scan, and boundary scan, which minimizes additional logic while achieving very high fault coverage.
Abstract: A circuit used in a telephone switching unit features several test techniques, including BIST, partial scan, and boundary scan. By sharing the same circuitry for both online and offline testing, the design minimizes additional logic while achieving very high fault coverage.