Showing papers in "IEEE Design & Test of Computers in 2010"
TL;DR: A classification of hardware Trojans and a survey of published techniques for Trojan detection are presented.
Abstract: Editor's note:Today's integrated circuits are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. This article presents a classification of hardware Trojans and a survey of published techniques for Trojan detection.
1,227Â citations
TL;DR: In this article, the authors proposed a new syndrome coding scheme that limits the amount of leaked information by the PUF error-correcting codes, which can be used in many security, protection, and digital rights management applications.
Abstract: Physical unclonable functions (PUFs) offer a promising mechanism that can be used in many security, protection, and digital rights management applications. One key issue is the stability of PUF responses that is often addressed by error correction codes. The authors propose a new syndrome coding scheme that limits the amount of leaked information by the PUF error-correcting codes.
342Â citations
TL;DR: A combinational locking scheme based on intelligent placement of the barriers throughout the design in which the objective is to maximize the effectiveness of the barrier and to minimize the overhead is proposed.
Abstract: Hardware metering to prevent IC piracy is a challenging and important problem. The authors propose a combinational locking scheme based on intelligent placement of the barriers throughout the design in which the objective is to maximize the effectiveness of the barriers and to minimize the overhead.
327Â citations
TL;DR: A taxonomy for different SBST methodologies according to their test program development philosophy is proposed, and research approaches based on SBST techniques for optimizing other key aspects are summarized.
Abstract: This article discusses the potential role of software-based self-testing in the microprocessor test and validation process, as well as its supplementary role in other classic functional- and structural-test methods. In addition, the article proposes a taxonomy for different SBST methodologies according to their test program development philosophy, and summarizes research approaches based on SBST techniques for optimizing other key aspects.
231Â citations
TL;DR: This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs that achieve up to 31% smaller channel load and up to 22% smaller packet latency than other heuristic.
Abstract: Multiprocessor-system-on-a-chip (MPSoC) applications can consist of a varying number of simultaneous tasks and can change even after system design, enforcing a scenario that requires the use of dynamic task mapping. This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs. The proposed heuristics achieve up to 31% smaller channel load and up to 22% smaller packet latency than other heuristics.
156Â citations
TL;DR: JTAG is a well-known standard mechanism for in-field test that provides high controllability and observability, but it also poses great security challenges.
Abstract: JTAG is a well-known standard mechanism for in-field test. Although it provides high controllability and observability, it also poses great security challenges. This article analyzes various attacks and proposes protection schemes.
151Â citations
TL;DR: This article provides a comprehensive view on the predominant variation sources in sub-90-nm devices, their impact on device and circuit performance, and various modeling approaches for statistical circuit analysis.
Abstract: Process variability has become a critical issue in scaled CMOS design. This article provides a comprehensive view on the predominant variation sources in sub-90-nm devices, their impact on device and circuit performance, and various modeling approaches for statistical circuit analysis.
135Â citations
TL;DR: Challenges related to detection for Trojans designed to leak secret information through the wireless channel are investigated and statistical analysis of the side-channel signals is proposed to help detect them.
Abstract: The article studies the problem of hardware Trojans in wireless cryptographic ICs. The objective is to design Trojans to leak secret information through the wireless channel. The authors investigate challenges related to detection for such Trojans and propose using statistical analysis of the side-channel signals to help detect them.
122Â citations
TL;DR: Electrical modeling and performance analysis have demonstrated the superiority of carbon nanotubes and graphene nanoribbons compared to conventional copper interconnects, as this article explains.
Abstract: Carbon nanotubes and graphene nanoribbons are two promising next-generation interconnect technologies. Electrical modeling and performance analysis have demonstrated the superiority of these emerging technologies compared to conventional copper interconnects, as this article explains.
94Â citations
TL;DR: An overview of low-power and delay testing, and ongoing research for analyzing and dealing with PSN effects during delay test and timing analysis are surveyed.
Abstract: As technology scales to 32 nm and functional frequency and density continue to rise, PSN effects, which can reduce a circuit's noise immunity and could lead to failures, pose new challenges to chip manufacturers and foundries. This article provides an overview of low-power and delay testing, and surveys ongoing research for analyzing and dealing with PSN effects during delay test and timing analysis.
79Â citations
TL;DR: Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models.
Abstract: The strategy to generate statistical model parameters is essential for variability-aware design. Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models.
TL;DR: This column examines the ITRS definitions associated with "More than Moore", along with their implications, and examines the implications of these definitions for IC design and test.
Abstract: Discerning "the road ahead" is more difficult than ever. For IC design and test, the road ahead has long involved various corollaries of the 50+-year scaling phenomenon known as Moore's law. This column examines the ITRS definitions associated with "More than Moore", along with their implications.
TL;DR: A scalable system-level, dynamic thermal management solution using an agent-based, distributed-application-mapping approach to improve variation tolerance in multi- and many-core systems is looked into.
Abstract: System-level runtime approaches provide a new dimension of variation tolerance in multi- and many-core systems. This article looks into a scalable system-level, dynamic thermal management solution using an agent-based, distributed-application-mapping approach.
TL;DR: This article advocates the use of short-range wireless communication inside a computing chassis through Ultrawideband links, which make it possible to design a within-chassis wireless interconnect.
Abstract: This article advocates the use of short-range wireless communication inside a computing chassis. Ultrawideband links make it possible to design a within-chassis wireless interconnect. In contrast to conventional, fixed, wireline connections between chips, wireless communications offer certain unique advantages, as the authors explain.
TL;DR: This article presents a low-cost, hardware-iterative technique based on a steepest-descent-based gradient search algorithm and demonstrates its utility in performance tuning of a 2.4-GHz transmitter system.
Abstract: Tuning knobs are becoming common in analog and RF devices for postsilicon calibration for variation tolerance and compensation. This article presents a low-cost, hardware-iterative technique based on a steepest-descent-based gradient search algorithm and demonstrates its utility in performance tuning of a 2.4-GHz transmitter system.
TL;DR: This article provides a comprehensive analysis of the variations in FinFet devices, their impact on SRAM stability, and a statistical design procedure for FinFET SRAM cells.
Abstract: FinFET technology is a possible solution to achieve a better power/performance trade-off for SRAM cells. This article provides a comprehensive analysis of the variations in FinFET devices, their impact on SRAM stability, and a statistical design procedure for FinFET SRAM cells.
TL;DR: This article describes a more general form of the backward propagation of variance (BPV) method, a numerical technique for iteratively solving the statistics of process parameters from theStatistics of electrical performance within the behavior of models encapsulated in Spice.
Abstract: Correlating the statistics of process parameters with the statistics of electrical performance is a vital task in statistical modeling. This article describes a more general form of the backward propagation of variance (BPV) method, a numerical technique for iteratively solving the statistics of process parameters from the statistics of electrical performance within the behavior of models encapsulated in Spice.
TL;DR: A new technique, Axiom, helps yield and product engineers determine the root cause of loss directly from diagnosis results, resulting in a higher physical-failure analysis success rate and reduced costs.
Abstract: The cost and cycle time for determining the root cause of yield loss continues to increase as semiconductor technology scales down. A new technique, Axiom, helps yield and product engineers determine the root cause of loss directly from diagnosis results. Consequently, root-cause cycle time is dramatically reduced, resulting in a higher physical-failure analysis success rate and reduced costs.
TL;DR: On-chip optical links are an efficient means of designing the communication backbone for massive multicore chips using nanophotonic technology to develop a low-power, low-latency interconnection infrastructure for many-core chips.
Abstract: On-chip optical links are an efficient means of designing the communication backbone for massive multicore chips. Using nanophotonic technology lets designers develop a low-power, low-latency interconnection infrastructure for many-core chips.
TL;DR: An analysis of ring oscillators that were designed in 180-nm and 100-nm CMOS technologies is described, and the oscillators' frequency variations as determined for different stage numbers and supply voltages are discussed.
Abstract: As transistor size scales down, unavoidable process variations are rapidly increasing. Consequently, it's essential for designers to accurately estimate within-die and interdie variations so that circuits and integrated systems can operate correctly. This article describes an analysis of ring oscillators that were designed in 180-nm and 100-nm CMOS technologies, and discusses the oscillators' frequency variations as determined for different stage numbers and supply voltages.
TL;DR: An overview of EDA, its funding history, a discussion of major challenges, related emerging technologies, and a look at how EDA experience might help in developing these technologies, along with associated educational aspects and challenges are presented.
Abstract: The July 2009 National Science Foundation workshop on EDA had two objectives: First, to reflect on EDA's success and to see if EDA practices can influence other fields of computer science and if EDA methodology can be applied to other application domains; and second, to review the progress made under the National Design Initiative and evaluate what new directions and topics should be added to the Initiative. This two-part report, part 1 of which appeared in the March/April issue, contains an overview of EDA, its funding history, a discussion of major challenges, related emerging technologies, and a look at how EDA experience might help in developing these technologies, along with associated educational aspects and challenges. The report also considers EDA's relation with computer science theorists and how this collaboration can be revived. Finally, the report presents three sets of recommendations on how to promote EDA and assist with the serious challenges it faces in the future.
TL;DR: The key characteristics of CNTs that make them so well suited for use as antennas in on-chip wireless communication are reviewed.
Abstract: Recent research has demonstrated that carbon nanotubes (CNTs) have excellent emission and absorption characteristics, leading to dipole-like radiation behavior, which makes CNTs promising alternatives for use as antennas in on-chip wireless communication. This article reviews the key characteristics of CNTs that make them so well suited for this purpose.
TL;DR: This article presents a fast parallel repair methodology for SoC memory cores and an associated automation framework for built-in-self-repair in system-on-chip designs.
Abstract: Built-in-self-repair is an enabling approach for improving memory yield in system-on-chip designs. Reducing the overhead of repair circuits while minimizing the test and repair time is of prime importance. This article presents a fast parallel repair methodology for SoC memory cores and an associated automation framework.
TL;DR: Statistical circuit simulation results indicate that the standard assumption for uncorrelated normal distribution of the statistical compact model parameters may introduce considerable errors in the statistical distribution of circuit figure of merits.
Abstract: Intrinsic statistical variability (SV) associated with discreteness of charge and granularity of matter is one of limiting factors for CMOS scaling and integration. There are several standard statistical parameter generation strategies to transfer SV information into compact models, and their accuracy is essential for achieving reliable variability aware design. We investigate the accuracy of these strategies based on the direct statistical compact model parameter extraction results for industry standard compact models BSIM4 and PSP. Statistical circuit simulation results indicate that the standard assumption for uncorrelated normal distribution of the statistical compact model parameters may introduce considerable errors in the statistical distribution of circuit figure of merits.
TL;DR: A novel approach is proposed in this article to seamlessly integrate physical models of lithography, strained Si, and ion implantation processes, with layout geometry for efficient model generation.
Abstract: Layout-dependent variations significantly affect device modeling, model extraction, and design solutions. A novel approach is proposed in this article to seamlessly integrate physical models of lithography, strained Si, and ion implantation processes, with layout geometry for efficient model generation.
TL;DR: Automatic frequency calibration and amplitude control techniques that rely on a negative feedback loop with a large emphasis on digitally assisted calibration are discussed.
Abstract: Despite their inherent self-healing nature, noise (jitter) in phase-locked loops is sensitive to process and environmental variation. This article discusses automatic frequency calibration and amplitude control techniques that rely on a negative feedback loop with a large emphasis on digitally assisted calibration.
TL;DR: An overview of EDA, its funding history, a discussion of major challenges, related emerging technologies, and a look at how EDA experience might help in developing these technologies, along with associated educational aspects and challenges are presented.
Abstract: The July 2009 National Science Foundation workshop on EDA had two objectives: First, to reflect on EDA's success and to see if EDA practices can influence other fields of computer science and if EDA methodology can be applied to other application domains; and second, to review the progress made under the National Design Initiative and evaluate what new directions and topics should be added to the Initiative. This two-part report, part 1 of which appears in this issue, contains an overview of EDA, its funding history, a discussion of major challenges, related emerging technologies, and a look at how EDA experience might help in developing these technologies, along with associated educational aspects and challenges. The report also considers EDA's relation with computer science theorists and how this collaboration can be revived. Finally, the report presents three sets of recommendations on how to promote EDA and assist with the serious challenges it faces in the future.
IBM1
TL;DR: Computer simulations let engineers accurately predict the behavior of the design while it is still represented by computer data, before it ever becomes a real physical object.
Abstract: IC engineers rarely get to crash test their designs. Instead, they take pride in getting the design right the first time—no room for iterations and redesign. This is done by performing extensive computer simulations of designs. These simulations let engineers accurately predict the behavior of the design while it is still represented by computer data, before it ever becomes a real physical object.
IBM1
TL;DR: This article presents a mixture importance sampling methodology to enable yield-driven design and extends its application beyond memories to peripheral circuits and logic blocks.
Abstract: Statistical approaches for yield estimation and robust design are vital in the current variation-dominated design era. This article presents a mixture importance sampling methodology to enable yield-driven design and extends its application beyond memories to peripheral circuits and logic blocks.
TL;DR: This article shows how such a structure utilizes the high bandwidth of the optical links through optical proximity communication that enables significant levels of device integration in large-scale chip arrays.
Abstract: Advances in silicon photonic technology have made possible the use of optical communication in large-scale chip arrays. This article shows how such a structure utilizes the high bandwidth of the optical links through optical proximity communication that enables significant levels of device integration.