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Showing papers in "IEEE Electron Device Letters in 1991"


Journal ArticleDOI
TL;DR: In this article, current densities of 0.1 to 1 A-cm/sup -2/ are estimated for a diode current of 10 mA for a Si cold cathode.
Abstract: Diamond cold cathodes have been formed by fabricating mesa-etched diodes using carbon ion implantation into p-type diamond substrates. When these diodes are forward biased, current is emitted into vacuum. The cathode efficiency (emitted current divided by diode current) varies from 2*10/sup -4/ to 1*10/sup -10/ and increases with the addition of 10/sup -2/-torr partial pressure of O/sub 2/ into the vacuum system. Current densities of 0.1 to 1 A-cm/sup -2/ are estimated for a diode current of 10 mA. This compares favorably with Si cold cathodes (not coated with Cs), which have efficiencies of approximately 2*10/sup -5/ and current densities of approximately 2*10/sup -2/ A-cm/sup -2/. It is believed that higher current densities and efficiencies can be obtained with more efficient cathode designs and an ultrahigh-vacuum environment. >

342 citations


Journal ArticleDOI
TL;DR: In this article, light-emitting porous silicon (LEPOS) is described, which is made from n-type silicon by anodization in an electrolytic cell by HF with an applied electrical current.
Abstract: Experiments with light-emitting porous silicon (LEPOS) are described. The porous silicon was made from n-type silicon by anodization in an electrolytic cell by HF with an applied electrical current. Visible light emission was achieved by irradiation with ultraviolet light. Visible electroluminescence (EL) was achieved by applying a DC or AC voltage to a solid-state contact on top of the porous layer. Optical spectra from both experiments are shown. >

313 citations


Journal ArticleDOI
TL;DR: In this article, a novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented, which switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure.
Abstract: A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V. >

281 citations


Journal ArticleDOI
TL;DR: In this article, a technique for measuring the release of minority carriers emitted from deep levels in avalanche photodiodes (APDs) at operating conditions is discussed, which can be useful in tailoring gettering processes for APDs and in studies of traps at high electric fields.
Abstract: A technique for measuring the release of minority carriers emitted from deep levels in avalanche photodiodes (APDs) at operating conditions is discussed. The method, time-correlated carrier counting (TCCC), is very sensitive and accurate. Densities of filled traps were measured down to 10/sup 9/ cm/sup -3/ and lifetimes in the nanosecond range. This technique can be useful in tailoring gettering processes for APDs and in studies of traps at high electric fields. >

280 citations


Journal ArticleDOI
I-Wei Wu1, Tiao-Yuan Huang1, Warren B. Jackson1, A.G. Lewis1, A. Chiang1 
TL;DR: In this article, the effects and kinetics of hydrogen passivation on polycrystalline-silicon thin-film transistors (poly-TFTs) are investigated.
Abstract: The effects and kinetics of hydrogen passivation on polycrystalline-silicon thin-film transistors (poly-TFTs) are investigated. Based on the response of device parameters with the progress of hydrogenation, two types of defects can be distinguished from the difference in passivation rate. The threshold voltage and subthreshold slope, which are strongly influenced by the density of dangling bond midgap states, have a faster response to hydrogenation. The off-state leakage current and field-effect mobility, related to stain-bond tail states, respond more slowly to hydrogenation, with an onset period of approximately 4 to 12 h depending on the grain size. Since the larger-grain-size samples showed a longer onset period, the contribution of intragranular defects to the strain-bond tail states appears to be significant. >

220 citations


Journal ArticleDOI
TL;DR: In this paper, the feasibility of a p-channel quantum-well MOSFET on a Ge/sub x/Si/sub 1-x/Si heterostructure was demonstrated.
Abstract: The authors demonstrate the feasibility of a p-channel quantum-well MOSFET on a Ge/sub x/Si/sub 1-x//Si heterostructure. The advantages of the enhancement-mode p-channel MOSFET device compared to GeSi MODFETs are its high impedance, channel mobility, and channel transconductance. The device shows good saturation and cutoff behaviour. A saturation transconductance of 64 mS/mm was measured for a 0.7- mu m channel device at a drain-to-source voltage of -2.5 V. The channel mobility was found to be higher than that of a similarly processed Si p-channel MOSFET. >

202 citations


Journal ArticleDOI
TL;DR: In this article, the effect of the Si-SiO/sub 2/ interface microroughness on the electron channel mobility of n-MOSFETs was investigated.
Abstract: The effect of the Si-SiO/sub 2/ interface microroughness on the electron channel mobility of n-MOSFETs was investigated The surface microroughness was controlled by changing the mixing ratio of NH/sub 4/OH in the NH/sub 4/OH-H/sub 2/O/sub 2/-H/sub 2/O solution in the RCA cleaning procedure The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO/sub 2/ interface with scanning tunneling microscopy (STM) As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower The channel mobility is around 360 cm/sup 2//V-s when the average interface microroughness is 02 nm, where the substrate impurity concentration is 45*10/sup 17/ cm/sup -3/, ie the electron bulk mobility is 400 cm/sup 2//V-s It goes down to 100 cm/sup 2//V-s when the interface microroughness exceeds 1 nm >

151 citations


Journal ArticleDOI
TL;DR: In this paper, a correlation between the leakage current and the charge-pumping current was evident in a series of voltage stress, annealing, and restress tests, suggesting that the leakage may be a result of the oxide-trap assisted tunneling.
Abstract: Voltage-stress-induced leakage in 5-nm thermal oxides was studied. A correlation between the leakage current and the charge-pumping current was evident in a series of voltage stress, annealing, and restress tests. The close correlation suggests that the leakage may be a result of the oxide-trap assisted tunneling. Data supporting a model involving trap states are presented. >

134 citations


Journal ArticleDOI
TL;DR: In this article, thermally isolated micromechanical structures capable of generating thermal radiation for dynamic thermal scene simulation (DTSS) are described, and the resulting structures are suspended plates consisting of polysilicon resistors encapsulated in the field and CVD (chemical-vapor-deposited) oxides available in the CMOS process.
Abstract: Fabrication of thermally isolated micromechanical structures capable of generating thermal radiation for dynamic thermal scene simulation (DTSS) is described. Complete compatibility with a commercial CMOS process is achieved through design of a novel, but acceptable, layout for implementation by the CMOS foundry using its regular process sequence. Following commercial production and delivery of the CMOS chips, a single maskless etch in an aqueous ethylemediamine-pyrocatechol mixture is performed to realize the micromechanical structures. The resulting structures are suspended plates consisting of polysilicon resistors encapsulated in the field and CVD (chemical-vapor-deposited) oxides available in the CMOS process. The plates are suspended by aluminum heater leads that are also encapsulated in the field and CVD oxides. Studies of the suitability of these structures for DTSS have been initiated, and early favorable results are reported. >

129 citations


Journal ArticleDOI
TL;DR: In this paper, a selfconsistent approach is proposed for extracting the minority carrier mobility from fits to experimental data for lifetime and diffusion length and then comparing the extracted mobility to experimental mobility data.
Abstract: A self-consistent approach is proposed for extracting the minority-carrier mobility from fits to experimental data for lifetime and diffusion length and then comparing the extracted mobility to experimental mobility data. A value for electron and hole lifetime is extracted using a doping-dependent Shockley-Read-Hall mechanism with an Auger process. The hole lifetime is used to extract a minority carrier hole mobility that is consistent with the reported measurements of the hole diffusion length. The good agreement between extracted and experimental mobilities justifies incorporating the results into numerical device and circuit CAD tools. >

119 citations


Journal ArticleDOI
TL;DR: In this paper, a novel subsurface SiGe-channel p-MOSFET was demonstrated in which modulation doping was used to control the threshold voltage without degrading the channel mobility.
Abstract: A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n/sup +/ polysilicon gate, and p/sup +/ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm/sup 2//V-s at 300 K and 980 cm/sup 2//V-s at 82 K were achieved in functional submicrometer p-MOSFETs. >

Journal ArticleDOI
E.J. Prinz1, P.M. Garone1, P. V. Schwartz1, X. Xiao1, James C. Sturm1 
TL;DR: In this article, the effects of base dopant outdiffusion and nominally undoped Si/Si/sub 1-x/Ge/sub x/ spacer layers at the junction interfaces of Si n-p-n heterojunction bipolar transistors have been studied.
Abstract: The effects of base dopant outdiffusion and nominally undoped Si/sub 1-x/Ge/sub x/ spacer layers at the junction interfaces of Si/Si/sub 1-x/Ge/sub x//Si n-p-n heterojunction bipolar transistors (HBTs) have been studied. It has been found that small amounts of boron outdiffusion from heavily doped bases of nonabrupt interfaces cause parasitic barriers in the conduction band, which drastically reduce the collector current enhancement in the HBTs. Undoped interface spacers can remove the parasitic barriers, resulting in a strongly improved collector current enhancement. >

Journal ArticleDOI
TL;DR: In this article, trathin (approximately 6 nm) oxynitrided SiO/sub 2/ (SiO/Sub x/N/sub y/) films have been formed on Si
Abstract: Ultrathin ( approximately=6 nm) oxynitrided SiO/sub 2/ (SiO/sub x/N/sub y/) films have been formed on Si

Journal ArticleDOI
TL;DR: In this article, the authors measured 10-pA/m/m of the charging current of Al etch process on a given antenna geometry and predicted the impact on oxide integrity and interface stability.
Abstract: CV measurement is shown to be a more sensitive technique for characterizing plasma-etching induced damage than oxide breakdown. Plasma etching of Al is shown to produce severe distortions in the oxide CV characteristics, from which one can easily deduce the plasma charging current over many orders of magnitude. A clear radial variation of stressing is found and the charging current increases in proportion to the Al peripheral length rather than the area. Using the measured 10-pA/ mu m of the charging current, one should be able to predict the impact of this etch process on oxide integrity and interface stability for a given antenna geometry. >

Journal ArticleDOI
M. Hack1, A.G. Lewis1
TL;DR: In this paper, a comparison of experimental data and two-dimensional numerical simulations of polysilicon thin-film transistors is presented, and it is shown that avalanche multiplication causes both the kink effect in the output characteristics and the reduction of threshold voltage in short-channel device.
Abstract: A comparison of experimental data and two-dimensional numerical simulations of polysilicon thin-film transistors (TFTs) is presented. It is shown that avalanche multiplication causes both the kink effect in the output characteristics and the reduction of threshold voltage in short-channel device. It is shown that exactly the same physical model for avalanche multiplication gives very good agreement between simulations and experimental data for both these effects. It is demonstrated that it is the presence of grain boundaries or traps in the polysilicon that causes avalanche effects to be much greater than in comparable single-crystal silicon devices. >

Journal ArticleDOI
TL;DR: A floating-gate MOSFET with Fowler-Nordheim tunneling is described in this article, which is programmable in both directions by FN tunneling and is fabricated using an inexpensive standard 2- mu m double-polysilicon CMOS technology.
Abstract: A floating-gate MOSFET which is programmable in both directions by Fowler-Nordheim tunneling and is fabricated using an inexpensive standard 2- mu m double-polysilicon CMOS technology is discussed. Tunneling occurs at a crossover of polysilicon 1 with polysilicon 2. Device layout and basic device characteristics are presented, and recommendations for efficient programming are given. This is the first floating-gate FET with a tunneling injector fabricated in standard technology that has close to symmetric programming characteristics for both charging and discharging of the gate. >

Journal ArticleDOI
TL;DR: In this article, the selective growth of boron-doped homoepitaxial diamond films was achieved using sputtered SiO/sub 2/ as a masking layer.
Abstract: Selective growth of boron-doped homoepitaxial diamond films was achieved using sputtered SiO/sub 2/ as a masking layer. The hole mobility of selectively grown films varied between 210 and 290 cm/sup 2//V-s for hole concentration between 1.0*10/sup 14/ and 6.9*10/sup 14/ cm/sup -3/. The technique was used to fabricate a thin-film diamond field-effect transistor operational at 300 degrees C. The channel resistance of the device is an exponential function of temperature. In combination with the selective growth method, this device can be used as a starting point for the development of high-temperature diamond-based integrated circuits. >

Journal ArticleDOI
TL;DR: In this paper, a simple analytical model explains the f/sub T/ degradation, caused by the reduction of the collector current and a pileup of minority carriers in the base.
Abstract: Parasitic energy barriers can easily be introduced during processing. Measurements and calculations of experimental n-p-n HBTs (heterojunction bipolar transistors) are presented, showing that a parasitic conduction-band barrier at the base-collector junction reduces the collector current and the cutoff frequency. A simple analytical model explains the f/sub T/ degradation, caused by the reduction of the collector current and a pileup of minority carriers in the base. With the model the effective height and width of the barrier can also be derived from the measured collector current enhancement factor I/sub C/(SiGe)/I/sub C/(Si). >

Journal ArticleDOI
TL;DR: In this paper, a high-quality dielectric system for use with Si/sub 1-x/Ge/sub x/ alloys was presented, where the buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits.
Abstract: The authors present a high-quality dielectric system for use with Si/sub 1-x/Ge/sub x/ alloys. The system employs plasma-enhanced chemical vapor deposited (PECVD) SiO/sub 2/ on a thin (6-8-nm) layer of pure silicon grown epitaxially on the Si/sub 1-x/Ge/sub x/ layer. The buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits. The Si cap layer leads to a sequential turn-on of the Si/sub 1-x/Ge/sub x/ channel and the Si cap channel as is clearly observed in the low-temperature C-V curves. The authors show that this dual-channel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets. >

Journal ArticleDOI
Abstract: A new model for gate breakdown in MESFETs and HEMTs is presented. The model is based upon a combination of thermally assisted tunneling and avalanche breakdown. When thermal effects are considered it is demonstrated that the model predicts increasing drain-source breakdown as the gate electrode is biased towards pinch-off, in agreement with experimental data. The model also predicts the gate current versus bias behavior observed in experimental data. The model is consistent with various reports of breakdown and light emission phenomena reported in the literature. >

Journal ArticleDOI
TL;DR: In this article, a p-type conducting layer has been formed in a substrate of semi-insulating natural diamond (type IIa) by boron implantation, and Silicon dioxide was deposited over this layer to make an insulated-gate field effect transistor.
Abstract: A p-type conducting layer has been formed in a substrate of semi-insulating natural diamond (type IIa) by boron implantation. Silicon dioxide was deposited over this layer to make an insulated-gate field-effect transistor. Saturation and pinch-off were both observed at room temperature. The transconductance was 3.9 mu S-mm/sup -1/ and the output conductance was 60 nS-mm/sup -1/. This is the first reported use of ion implantation to successfully fabricate a field-effect device in diamond. >

Journal ArticleDOI
TL;DR: In this paper, an 80nm-thick amorphous Ta/sub 36/Si/sub 14/N/sub 50/ film prepared by reactive RF sputtering was used to prevent the interaction between the Si substrate with the TiSi/Sub 2/ contacting layer and a 500-nm Cu overlayer.
Abstract: Electrical measurements on shallow Si n/sup +/-p junction diodes with a 30-nm TiSi/sub 2/ contacting layer demonstrate that an 80-nm-thick amorphous Ta/sub 36/Si/sub 14/N/sub 50/ film prepared by reactive RF sputtering of a Ta/sub 5/Si/sub 3/ target in an Ar N/sub 2/ plasma very effectively prevents the interaction between the Si substrate with the TiSi/sub 2/ contacting layer and a 500-nm Cu overlayer. The Ta/sub 36/Si/sub 14/N/sub 50/ diffusion barrier maintains the integrity of the I-V characteristics up to 900 C for 30-min annealing in vacuum. It is concluded that the amorphous Ta/sub 36/Si/sub 14/N/sub 50/ alloy is not only a material with a very low reactivity for copper, titanium, and silicon, but must have a small diffusivity for copper as well. >

Journal ArticleDOI
TL;DR: In this article, the threshold voltage corresponding to each of the conduction mechanisms was measured for the first time and an intuitive physical interpretation of their dependence on the front and back-gate voltages was also given.
Abstract: Accumulation-mode PMOS transistors on SOI (silicon on insulator) are characterized by several conduction mechanisms. Measurements of the threshold voltage corresponding to each of them are presented for the first time. An intuitive physical interpretation of their dependence on the front- and back-gate voltages is also given. >

Journal ArticleDOI
TL;DR: In this paper, the optical gain and small-signal frequency response of an InP/InGaAs heterojunction phototransistor with a base terminal are investigated in detail for the first time.
Abstract: The optical gain and the small-signal frequency response of an InP/InGaAs heterojunction phototransistor (HPT) with a base terminal are investigated in detail for the first time. When operated under an optimally chosen external base current, the optical gain is enhanced more than five times over that of the same device operated as a two-terminal device, over a 17-dB range of input optical power. The small-signal 3-dB bandwidth of the three-terminal device is enhanced 15 times over that of the two-terminal device over the same range of input optical power. For a pseudorandom NRZ bit stream at 100 Mb/s, a clear eye opening is observed at an incident optical power of -33 dBm (500 nW). >

Journal ArticleDOI
TL;DR: In this paper, the degradation of p-MOS transistors is shown to proceed logarithmically in time, and a simple analytic degradation model is proposed that fully accounts for this observation.
Abstract: The degradation of p-MOS transistors is shown to proceed logarithmically in time. A simple, analytic degradation model is proposed that fully accounts for this observation. The logarithmic time dependence originates from the logarithmic growth of a region of filled traps from the drain junction towards the source. On this basis, a reliable lifetime extrapolation is performed. >

Journal ArticleDOI
M. Rodder1, D. Yeakley1
TL;DR: A raised source/drain (S/D) MOSFET with sidewall spacers formed both before and after selective epitaxial silicon deposition in S/D regions is discussed in this paper.
Abstract: A raised source/drain (S/D) MOSFET with sidewall spacers formed both before and after selective epitaxial silicon deposition in S/D regions is discussed. The second spacer overlies any faceted regions of the epitaxial silicon near the gate edge and has advantages for MOSFETs with implant-doped or in-situ doped epitaxial silicon regions. In particular, the spacer can prevent S/D dopants from being implanted through any thinner faceted regions near the gate edge, which would otherwise result in a deeper than desired junction depth in the silicon substrate. Additionally, the spacer can prevent source-to-substrate salicide shorts through the thinner faceted regions. >

Journal ArticleDOI
TL;DR: In this article, a diamond p-type depletion-mode MESFET was fabricated using a novel doping technique to drive in and activate boron in type IIa diamond.
Abstract: A diamond p-type depletion-mode MESFET was fabricated using a novel doping technique to drive in and activate boron in type IIa diamond. An ultrashallow p-doped channel of less than 500 AA was created by this rapid-thermal-processing (RTP) solid-state diffusion using cubic boron nitride as the dopant source. The MESFET was observed to pinch off at high positive gate bias, and reverse-bias leakage was below 10/sup -12/ A at +5 V. The ultrashallow channel depth is believed to be a critical factor in obtaining excellent device modulation. >

Journal ArticleDOI
TL;DR: In this paper, the gate reverse breakdown and forward turn-on voltages are improved substantially by using the high-resistivity GaAs layer between the gate metal and the conducting channel, which is shown that a reverse bias of 42 V or forward bias of 9,3 V is needed to reach a gate current of 1 mA/mm of gate width.
Abstract: A GaAs layer grown by molecular beam epitaxy at 200 degrees C is used as the gate insulator for GaAs MISFETs. The gate reverse breakdown and forward turn-on voltages, are improved substantially by using the high-resistivity GaAs layer between the gate metal and the conducting channel. It is shown that a reverse bias of 42 V or forward bias of 9,3 V is needed to reach a gate current of 1 mA/mm of gate width. A MISFET having a gate of 1.5*600 mu m delivers an output power of 940 mW (1.57-W/mm power density) with 4.4-dB gain and 27.3% power added efficiency at 1.1 GHz. This is the highest power density reported for GaAs-based FETs. >

Journal ArticleDOI
TL;DR: The first n-SiGe-channel MOSFETs fabricated using high-dose germanium implantation and solid-phase epitaxy are reported in this article, and their electrical characteristics are compared.
Abstract: The first n-SiGe-channel MOSFETs fabricated using high-dose germanium implantation and solid-phase epitaxy are reported The polysilicon-gate MOSFETs were fabricated in the same chip in which conventional polysilicon-gate n-MOSFETs were made and their electrical characteristics are compared The SiGe-channel MOSFETs show some significantly better electrical characteristics as compared to the silicon-channel MOSFETs For example, the SiGe MOSFETs show higher drain conductance in the triode region and higher transconductance overall The threshold voltage of the SiGe MOSFET appears to be smaller and the carrier mobility in the channel appears to be higher >

Journal ArticleDOI
TL;DR: In this article, the fabrication of a GaAs detector which operates in the 1.3-to 1.5-mu m optical range is reported and the detector is a P-i-N photodiode with an intrinsic layer composed of undoped GaAs which was grown at 225 degrees C and subsequently annealed at 600 degrees C. This growth process has been demonstrated to produce a high density of As precipitates in the low-temperature grown region, which the authors show to exhibit absorption through internal photoemission.
Abstract: The fabrication of a GaAs detector which operates in the 1.3- to 1.5- mu m optical range is reported. The detector is a P-i-N photodiode with an intrinsic layer composed of undoped GaAs which was grown at 225 degrees C and subsequently annealed at 600 degrees C. This growth process has been demonstrated to produce a high density of As precipitates in the low-temperature grown region, which the authors show to exhibit absorption through internal photoemission. The internal Schottky barrier height of the As precipitates is found to be 0.7 eV, leading to reasonable room-temperature responsivity out to around 1.7 mu m. >