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Showing papers in "IEEE Electron Device Letters in 2000"


Journal ArticleDOI
TL;DR: In this paper, a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation is presented, which is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction.
Abstract: This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250/spl deg/C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 /spl mu/m process, the area of a bit is 0.315 /spl mu/m/sup 2/ and 0.188 /spl mu/m/sup 2/ in 0.25 /spl mu/m technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications.

1,170 citations


Journal ArticleDOI
TL;DR: In this paper, the authors reported the highest reported microwave power density for undoped sapphire substrated AlGaN/GaN HEMT's on the same wafer.
Abstract: Surface passivation of undoped AlGaN/CaN HEMT's reduces or eliminates the surface effects responsible for limiting both the RF current and breakdown voltages of the devices. Power measurements on a 2/spl times/125/spl times/0.5 /spl mu/m AlGaN/GaN sapphire based HEMT demonstrate an increase in 4 GHz saturated output power from 1.0 W/mm [36% peak power-added efficiency (PAE)] to 2.0 W/mm (46% peak PAE) with 15 V applied to the drain in each case. Breakdown measurement data show a 25% average increase in breakdown voltage for 0.5 /spl mu/m gate length HEMT's on the same wafer. Finally, 4 GHz power sweep data for a 2/spl times/75/spl times/0.4 /spl mu/m AlGaN/GaN HEMT on sapphire processed using the Si/sub 3/N/sub 4/ passivation layer produced 4.0 W/mm saturated output power at 41% PAE (25 V drain bias). This result represents the highest reported microwave power density for undoped sapphire substrated AlGaN/GaN HEMT's.

752 citations


Journal ArticleDOI
TL;DR: In this paper, the authors report on the AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor (MOS-HFET) and present the results of the comparative studies of this device and a base line AlGa n/Ga n heterostructured transistor (HFET), for a 5/spl mu/ source-to-drain opening, the maximum current was close to 600 mA/mm for both devices.
Abstract: We report on the AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor (MOS-HFET) and present the results of the comparative studies of this device and a base line AlGaN/GaN heterostructure field effect transistor (HFET). For a 5-/spl mu/ source-to-drain opening, the maximum current was close to 600 mA/mm for both devices. The gate leakage current for the MOS-HFET was more than six orders of magnitude smaller than for the HFET.

428 citations


Journal ArticleDOI
TL;DR: In this paper, a simple but powerful evanescent-mode analysis showed that the length /spl lambda/ over which the source and drain perturb the channel potential, is 1/spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the cylindrical case, in excellent agreement with PADRE device simulations.
Abstract: Short-channel effects in fully-depleted double-gate (DG) and cylindrical, surrounding-gate (Cyl) MOSFETs are governed by the electrostatic potential as confined by the gates, and thus by the device dimensions. The simple but powerful evanescent-mode analysis shows that the length /spl lambda/, over which the source and drain perturb the channel potential, is 1//spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the effective diameter in the cylindrical case, in excellent agreement with PADRE device simulations. Thus for equivalent silicon and gate oxide thicknesses, evanescent-mode analysis indicates that Cyl-MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs.

355 citations


Journal ArticleDOI
TL;DR: In this paper, a GaN high electron mobility transistors (HEMTs) were fabricated using an overlapping-gate technique in which the drain-side edge of the metal gate overlaps on a high breakdown and high dielectric constant dielectrics.
Abstract: GaN high electron mobility transistors (HEMTs) were fabricated using an overlapping-gate technique in which the drain-side edge of the metal gate overlaps on a high breakdown and high dielectric constant dielectric. The overlapping structure reduces the electric field at the drain-side gate edge, thus increasing the breakdown of the device. A record-high three-terminal breakdown figure of 570 V was achieved on a HEMT with a gate-drain spacing of 13 /spl mu/m. The source-drain saturation current was 500 mA/mm and the extrinsic transconductance 150 mS/mm.

344 citations


Journal ArticleDOI
Yuan Taur1
TL;DR: In this paper, a 1D analytical solution for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation was derived, giving closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage.
Abstract: A one-dimensional (1-D) analytical solution is derived for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution gives closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage. A threshold criterion is derived which serves to quantify the gate work function requirements for a double-gate CMOS.

333 citations


Journal ArticleDOI
Tomohisa Mizuno1, Shinichi Takagi1, Naoharu Sugiyama1, H. Satake1, Atsushi Kurobe1, A. Toriumi1 
TL;DR: In this article, a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology is presented, and electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's.
Abstract: We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si/sub 0.9/Ge/sub 0.1/ layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer.

274 citations


Journal ArticleDOI
TL;DR: In this paper, the leakage current of the 45/spl Aring/HfO/sub 2/ sample was about 1/spl times/10/sup -4/ A/cm/sup 2/ at +1.0 V with a breakdown field /spl sim/8.5 MV/cm.
Abstract: Electrical and reliability properties of ultrathin HfO/sub 2/ have been investigated. Pt electroded MOS capacitors with HfO/sub 2/ gate dielectric (physical thickness /spl sim/45-135 /spl Aring/ and equivalent oxide thickness /spl sim/13.5-25 /spl Aring/) were fabricated. HfO/sub 2/ was deposited using reactive sputtering of a Hf target with O/sub 2/ modulation technique. The leakage current of the 45 /spl Aring/ HfO/sub 2/ sample was about 1/spl times/10/sup -4/ A/cm/sup 2/ at +1.0 V with a breakdown field /spl sim/8.5 MV/cm. Hysteresis was <100 mV after 500/spl deg/C annealing in N/sub 2/ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO/sub 2/ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V/sub DD/=2.0 V.

237 citations


Journal ArticleDOI
TL;DR: The first reported dynamic results for organic circuits fabricated on polyester substrates were reported in this paper, where the high-performance pentacene transistors yield circuits with the highest reported clock frequencies.
Abstract: We have fabricated and characterized analog and digital circuits using organic thin-film transistors on polyester film substrates. These are the first reported dynamic results for organic circuits fabricated on polyester substrates. The high-performance pentacene transistors yield circuits with the highest reported clock frequencies for organic circuits.

227 citations


Journal ArticleDOI
TL;DR: In this article, the electrical and reliability properties of ultrathin La/sub 2/O/sub 3/ gate dielectric have been investigated and the measured capacitance of 33 /spl Aring/La/sub 1/2O/Sub 3/3/ gate is 7.2 /spl mu/F/cm/sup 2/ that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 /spl aring.
Abstract: Electrical and reliability properties of ultrathin La/sub 2/O/sub 3/ gate dielectric have been investigated. The measured capacitance of 33 /spl Aring/ La/sub 2/O/sub 3/ gate dielectric is 7.2 /spl mu/F/cm/sup 2/ that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 /spl Aring/. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm/sup 2/ at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3/spl times/10/sup 10/ eV/sup -1//cm/sup 2/, and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO/sub 2/.

202 citations


Journal ArticleDOI
TL;DR: In this paper, a 40nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide.
Abstract: A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.

Journal ArticleDOI
TL;DR: In this article, a four thin-film transistor (TFT) circuit based on hydrogenated amorphous silicon (a-Si:H) technology was proposed to provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations.
Abstract: In this letter, we describe a four thin-film-transistor (TFT) circuit based on hydrogenated amorphous silicon (a-Si:H) technology. This circuit can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The experimental results indicated that, for TFT threshold voltage shift as large as /spl sim/3 V, the output current variations can be less than 1 and 5% for high (/spl ges/0.5 /spl mu/A) and low (/spl les/0.1 /spl mu/A) current levels, respectively. This circuit can potentially be used for the active-matrix organic light-emitting displays (AM-OLEDs).

Journal ArticleDOI
TL;DR: In this paper, the authors present a study on the characterization and modeling of direct tunneling gate leakage current in both N and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric formed by the jet-vapor deposition (JVD) technique.
Abstract: We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si/sub 3/N/sub 4/ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications.

Journal ArticleDOI
TL;DR: In this article, the characteristics of two organic electronic devices-monolithically integrated transistors and light emitting diodes (e.g. smart pixels), and complementary inverter circuits-that are fabricated on flexible plastic substrates with low cost, lowtemperature casting and microcontact printing techniques are described.
Abstract: This letter describes the characteristics of two organic electronic devices-monolithically integrated transistors and light emitting diodes (e.g. smart pixels), and complementary inverter circuits-that are fabricated on flexible plastic substrates with low cost, low-temperature casting and microcontact printing techniques. Both devices incorporate micron-sized features and have geometries and performance comparable to similar components produced with photolithographic techniques on rigid, inorganic supports.

Journal ArticleDOI
TL;DR: In this article, the effects of quantum tunneling along the channel and through the gate oxide were modeled for dual-gate ballistic n-MOSFETs with ultrathin undoped channel and the results showed that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS/mm or gate modulation of current by more than 8 orders of magnitude.
Abstract: We have performed numerical modeling of nanoscale dual-gate ballistic n-MOSFET's with ultrathin undoped channel, taking into account the effects of quantum tunneling along the channel and through the gate oxide. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the sub-10-nm devices potentially suitable for logic and memory applications, though their parameters are rather sensitive to size variations.

Journal ArticleDOI
Myung Kwan Cho1, D.M. Kim
TL;DR: Nonvolatile SONOS memory cells, fabricated by standard flash EEPROM technology are characterized, in comparison with floating gate memory devices, making it possible to perform parallel multi bit-line programming and to achieve tighter distributions of programmed and erased threshold voltages.
Abstract: Nonvolatile SONOS memory cells, fabricated by standard flash EEPROM technology are characterized, in comparison with floating gate memory devices. Its programming speed is comparable with the state-of-the-art flash EEPROM cells, while the erase speed is faster and over-erase-free. The SONOS cells do not suffer from the drain turn-on effect, making it is possible to perform parallel multi bit-line programming and to achieve tighter distributions of programmed and erased threshold voltages. These features render SONOS cells attractive for direct utilization in existing flash EEPROM technology with its forward reading scheme.

Journal ArticleDOI
TL;DR: In this paper, the deuterium isotope effect was used to probe the mechanism for interface trap generation in n-MOS transistors in the presence of hot hole and electron injection.
Abstract: The classical concept and theory suggest that the degradation of MOS transistors is caused by interface trap generation resulting from "hot carrier injection." We report three new experiments that use the deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS transistors in the presence of hot hole and electron injection. These experiments show clearly that hot carrier injection into the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons, not carriers injected into the gate oxide, are primarily responsible for interface trap generation for standard hot carrier stressing.

Journal ArticleDOI
TL;DR: In this article, the Sb-heterostructure-based backward diodes are grown by molecular beam epitaxy and shown to have superior figures of merit compared to Ge-diodes, especially the current density and junction resistance.
Abstract: Backward diodes are a version of Esaki tunnel diodes that are useful for mixing and detection. Ge backward diodes in particular have been used as temperature insensitive, zero bias square law detectors, capable of translating low level RF power into DC voltage or current with extreme linearity and low noise. However, Ge diodes are difficult to reproducibly manufacture and are physically fragile. Here we demonstrate specially designed Sb-heterostructure-based backward diodes grown by molecular beam epitaxy. These diodes have superior figures of merit compared to Ge diodes, especially the current density and junction resistance, and are reproducible and physically rugged. In addition, the flexibility of MBE growth allows easy tailoring of the layer structure to maximize the desired figure of merit for a given application.

Journal ArticleDOI
TL;DR: In this paper, the geometric effect of multiple-bit soft error (SE) induced by neutrons in 16 Mb DRAM's is investigated and their geometric effects on high reliability systems are discussed.
Abstract: Although it has been shown that cosmic ray neutrons play an important role in soft error (SE) phenomena, some important issues remain to be clarified in neutron-induced SE phenomena. This letter reports the geometric effect of multiple-bit SE's induced by neutrons. Multiple-bit SE's in 16 Mb DRAM's are investigated and their geometric effects on high reliability systems are discussed.

Journal ArticleDOI
Cheong Min Hong1, S. Wagner
TL;DR: In this paper, the copper contacts were used as the mask for back-channel etch and laser printed toner was used for all other mask levels in a photoresist-free fabrication process.
Abstract: Source/drain metallization to amorphous silicon thin-film transistors has been made by inkjet printing. Contact pads of a metal organic copper precursor were inkjet printed, and then converted to copper metal at a maximum process temperature of 200/spl deg/C. The copper contacts were used as the mask for back-channel etch. Laser printed toner was used for all other mask levels in a photoresist-free fabrication process. The inkjet printing of copper contacts represents a further step toward an all-printed thin-film transistor technology.

Journal ArticleDOI
TL;DR: In this paper, the authors describe a new narrow channel effect by quantum mechanical effects in ultra-narrow MOSFET's and show that the increase in threshold voltage is caused by the quantum mechanical narrow channel effects.
Abstract: The authors describe a new narrow channel effect by quantum mechanical effects in ultra-narrow MOSFET's. Threshold voltage increase is observed at room temperature in ultra-narrow MOSFET's whose channel width is less than 10 nm. This result is in excellent agreement with simulation that takes account of quantum confinement in the silicon narrow channel, indicating that the increase in threshold voltage is caused by the quantum mechanical narrow channel effect.

Journal ArticleDOI
S.J. Koester1, R. Hammond1, J. O. Chu1
TL;DR: In this article, a Ge/Si/sub 0.4/Ge/Sub 0.6/Heterostructure with a Hall mobility of 1750 cm/sup 2/Vs (30,900 cm/Sup 2/V) at room temperature (77 K) was reported.
Abstract: Ge-channel modulation-doped field-effect transistors (MODFET's) with extremely high transconductance are reported. The devices were fabricated on a compressive-strained Ge/Si/sub 0.4/Ge/sub 0.6/ heterostructure with a Hall mobility of 1750 cm/sup 2//Vs (30,900 cm/sup 2//Vs) at room temperature (77 K). Self-aligned, T-gate p-MODFET's with L/sub g/=0.1 /spl mu/m displayed an average peak extrinsic transconductance (g(m/sub ext/)) of 439 mS/mm, at a drain-to-source bias voltage (V/sub ds/) of -0.6 V, with the best device having a value of g(m/sub ext/)=488 mS/mm. At 77 K, values as high as g(m/sub ext/)=687 mS/mm were obtained at a bias voltage of only V/sub ds/=-0.2 V. These devices also displayed a unity current gain cutoff frequency (f/sub T/) of 42 GHz and maximum frequency of oscillation (f/sub max/) of 86 GHz at V/sub ds/=-0.6 V and -1.0 V, respectively.

Journal ArticleDOI
TL;DR: In this article, the concept and demonstration of a nanoscale ultra-thin-body silicon on-insulator (SOI) P-channel MOSFET with a Si/sub 1-x/Ge/sub x/Si heterostructure channel was presented.
Abstract: We report the concept and demonstration of a nanoscale ultra-thin-body silicon on-insulator (SOI) P-channel MOSFET with a Si/sub 1-x/Ge/sub x//Si heterostructure channel. First, a novel lateral solid-phase epitaxy process is employed to form an ultra-thin-body that suppresses the short-channel effects. Negligible threshold voltage roll-off is observed down to a channel length of 50 nm. Second, a selective silicon implant that breaks up the interfacial oxide is shown to facilitate unilateral crystallization to form a single crystalline channel. Third, the incorporation of SiGe in the channel resulted in a 70% enhancement in the drive current.

Journal ArticleDOI
TL;DR: In this paper, for the first time, N/sub 2/O-grown oxides on both n-type and p-type 6H-SiC wafers were reported.
Abstract: This letter reports, for the first time, N/sub 2/O-grown oxides on both n-type and p-type 6H-SiC wafers. It is demonstrated that the N/sub 2/O-grown technique leads to not only greatly improved SiC/SiO/sub 2/ interface and oxide qualities, but also considerably enhanced device reliabilities as compared to N/sub 2/O-nitrided and conventional thermally oxidized devices. These improvements are especially obvious for p-type SiC MOS devices, indicating that N/sub 2/O oxidation could be a promising technique for fabricating enhancement-type n-channel SiC MOSFETs.

Journal ArticleDOI
TL;DR: In this paper, a new measurement setup is presented that allows the observation of 1/f noise spectra in MOSFETs under switched bias conditions in a wide frequency band (10 Hz-100 kHz).
Abstract: A new measurement setup is presented that allows the observation of 1/f noise spectra in MOSFET's under switched bias conditions in a wide frequency band (10 Hz-100 kHz). When switching between inversion and accumulation, MOSFET's of different manufacturers invariably show reduced 1/f noise power density for frequencies below the switching frequency. At low frequencies (10 Hz), a 5-8 dB reduction in intrinsic 1/f noise power density is found for different devices, largely independent of the switching frequency (up to 1 MHz). The switched bias measurements render detailed wideband 1/f noise spectra of switched MOSFET's, which is useful for 1/f noise model validation and analog circuit design.

Journal ArticleDOI
TL;DR: In this paper, the soft breakdown and hard breakdown of thin gate SiO/sub 2/ films in MOS devices are shown to have a common physical origin, being triggered by identical microscopic defects, and these breakdown modes can be considered to be the same failure mechanism.
Abstract: By means of a statistical analysis, the soft breakdown and hard breakdown of thin gate SiO/sub 2/ films in MOS devices are shown to have a common physical origin. Being triggered by identical microscopic defects, these breakdown modes can be actually considered to be the same failure mechanism. In particular, it is shown that the soft breakdown conduction path is not precursor of the final hard breakdown event, which generally appears at a different spatial location. The huge differences between the soft and hard post-breakdown current-voltage (I-V) characteristics are attributed to differences in the breakdown spot area and to point contact energy funneling effects.

Journal ArticleDOI
TL;DR: In this paper, a distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip, which is compatible with high-speed layout guidelines.
Abstract: Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and bandwidth degradation. A distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip. A simple resistive model adequately predicts the ESD behavior under stress according to the charged device and human body models. The large area of the distributed ESD scheme could limit its application to designs such as distributed amplifiers, rf transceivers, A/D converters, and serial links with only a few dedicated high-speed interfaces. The distributed ESD protection is compatible with high-speed layout guidelines, requiring only low-loss transmission lines in addition to a conventional ESD device.

Journal ArticleDOI
TL;DR: A quantitative analysis of the Si/SiO/sub 2/interface roughness based on atomic force microscope (AFM) and mobility measurements is presented in this article, which shows that the spatial components of the roughness affecting the carrier transport lie outside the range probed by AFM, thus making questionable the validity of previously published correlations between AFM measurements and carrier mobility.
Abstract: A quantitative analysis of the Si/SiO/sub 2/ interface roughness based on atomic force microscope (AFM) and mobility measurements is presented. Our results show that the spatial components of the roughness affecting the carrier transport lie outside the range probed by AFM, thus making questionable the validity of previously published correlations between AFM measurements and carrier mobility. Based on a numerical model of the roughness scattering, a new physically-based correlation is proposed, highlighting the impact, so far overlooked, of the roughness correlation length on the carrier mobility.

Journal ArticleDOI
TL;DR: In this paper, a relationship is established between experimentally measured excess gate current and the tunneling of holes from the quantum well formed in the channel, and the channel hole current is then obtained as the quotient of the extra gate current to the gatevoltage-dependent transmission probability.
Abstract: The kink effect and excess gate current in InAlAs/InGaAs/InAlAs HEMT's have been linked to impact ionization in the high field region of the channel. In this letter, a relationship is established between experimentally measured excess gate current and the tunneling of holes from the quantum well formed in the channel. The channel hole current is then obtained as the quotient of the excess gate current to the gate-voltage-dependent transmission probability. This channel hole current follows the exponential dependence of the ionization constant on the inverse electric field.

Journal ArticleDOI
Chee-Wee Liu1, W.T. Liu1, M. H. Lee1, W.S. Kuo1, Bang-Gee Hsu1 
TL;DR: In this paper, a metal/oxide/p-Si structure with ultrathin oxide is utilized as a photodetector, which works in the deep depletion region with soft pinning of oxide voltage.
Abstract: A metal/oxide/p-Si structure with ultrathin oxide is utilized as a photodetector. At positive gate bias, the dark current of the photodetector is limited by the thermal generation of minority carriers in the inversion layer. The high growth temperature (1000/spl deg/C) of the gate oxide can reduce the dark current to a level as low as 3 nA/cm/sup 2/. As biased in the inversion layer, the tunneling diode works in the deep depletion region with soft pinning of oxide voltage, instead of the pinning of surface potential, very different from the conventional MOS diode with thick oxide.