Showing papers in "IEEE Electron Device Letters in 2001"
TL;DR: In this article, the authors demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO/sub 2/ interface states near the conduction band edge by high temperature anneals in nitric oxide.
Abstract: Results presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO/sub 2/ interface states near the conduction band edge by high temperature anneals in nitric oxide. Hi-lo capacitance-voltage (C-V) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2/spl times/10/sup 13/ to 2/spl times/10/sup 12/ eV/sup -1/ cm/sup -2/ following anneals in nitric oxide at 1175/spl deg/C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 30-35 cm/sup 2//V-s following the passivation anneals.
590 citations
TL;DR: In this article, the authors compared basic physical parameters of Al/sub 0.2/Ga/sub0.8/N-GaN quantum well with InAlN/(In)GaN HEMTs.
Abstract: We compare basic physical parameters of Al/sub 0.2/Ga/sub 0.8/N-GaN quantum well with In/sub 0.17/Al/sub 0.83/N/GaN and In/sub 0.17/Al/sub 0.83/N/In/sub 0.10/Ga/sub 0.90/N quantum well parameters, respectively. It is shown that in comparison to conventional AlGaN/GaN approach, structures based on InAlN/(In)GaN should exhibit two to three times higher quantum well polarization-induced charge. We use high electron mobility transistors (HEMT) analytical model to calculate InAlN(In)GaN HEMTs drain currents and transconductances. A 3.3 A/mm and 2.2 A/mm drain current was calculated for In/sub 0.17/Al/sub 0.83/N/In/sub 0.10/Ga/sub 0.90/N and In/sub 0.17/Al/sub 0.83/N/GaN HEMTs, respectively. This represents up to 205% current increase if compared with AlGaN/GaN HEMT and a record power performance can be expected for new structures.
538 citations
TL;DR: In this paper, a novel heterojunction AlGaN/AlN/GaN high-electron mobility transistor (HEMT) is discussed, where the insertion of the very thin AlN interfacial layer (/spl sim/1 nm) maintains high mobility at high sheet charge densities by increasing the effective /spl Delta/E/sub C/ and decreasing alloy scattering.
Abstract: In this letter, a novel heterojunction AlGaN/AlN/GaN high-electron mobility transistor (HEMT) is discussed. Contrary to normal HEMTs, the insertion of the very thin AlN interfacial layer (/spl sim/1 nm) maintains high mobility at high sheet charge densities by increasing the effective /spl Delta/E/sub C/ and decreasing alloy scattering. Devices based on this structure exhibited good DC and RF performance. A high peak current 1 A/mm at V/sub GS/=2 V was obtained and an output power density of 8.4 W/mm with a power added efficiency of 28% at 8 GHz was achieved.
418 citations
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TL;DR: In this paper, the concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced, the proposed device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFLET.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced, The proposed device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET.
303 citations
TL;DR: In this paper, a cell-based approach to the modeling of the oxide breakdown statistics is presented, which has the same predictive power as the standard percolation approach and the advantage of providing simple analytic results.
Abstract: A new analytic cell-based approach to the modeling of the oxide breakdown statistics is presented. The new model has the same predictive power as the standard percolation approach and the advantage of providing simple analytic results. The scaling with oxide thickness of the Weibull slope and the mean critical density of defects at breakdown are accounted for correctly.
256 citations
TL;DR: The dependence of the linear and saturated drain current of a nanoscale MOSFET on the near-equilibrium, inversion layer mobility of a long-channel device from the same technology is examined in this article.
Abstract: The dependence of the linear and saturated drain current of a nanoscale MOSFET on the near-equilibrium, inversion layer mobility of a long-channel device from the same technology is examined. Simple expressions developed from a scattering theory of the MOSFET provide a quantitative relation between the long-channel mobility and the short-channel drain current. The theory explains the commonly observed mobility-dependence of the linear and saturated drain currents in present-day deep submicron MOSFETs, and the results can be extrapolated all the way to the ballistic limit.
228 citations
TL;DR: In this paper, a pentacene active layer organic thin film transistors (OTFTs) were fabricated on heavily doped, thermally oxidized single-crystal silicon substrates with linear field effect mobility greater than 0.5 cm/sup 2/V-s at a drain-source voltage of -0.1 V.
Abstract: We have fabricated pentacene active layer organic thin film transistors (OTFTs) using chemically-modified source and drain contacts with improved contact and linear region characteristics. OTFTs fabricated on heavily doped, thermally oxidized single-crystal silicon substrates have linear field-effect mobility greater than 0.5 cm/sup 2//V-s at a drain-source voltage of -0.1 V, on/off current ratio greater than 10/sup 7/, and subthreshold slope as low as 0.7 V/decade.
214 citations
TL;DR: In this article, the authors demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si/sub 1-x/Ge/sub x/-on-insulator (SGOI) substrates with a high Ge content of 25%.
Abstract: We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si/sub 1-x/Ge/sub x/-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si/sub 0.75/Ge/sub 0.26/ and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si/sub 1-x/Ge/sub x/ layer.
209 citations
TL;DR: In this article, a metal-gate CMOS technology was proposed that uses a combination of two metals to achieve low threshold voltages for both n- and p-MOSFET's.
Abstract: In this letter, we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve low threshold voltages for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not disturb the delicate thin gate dielectric and preserves its uniformity and integrity. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.
194 citations
TL;DR: In this paper, the dependence of current slump in AlGaN/GaN HEMTs on the thickness of the barrier was observed, with the effect being more pronounced in thin barrier samples.
Abstract: The dependence of current slump in AlGaN/GaN HEMTs on the thickness of the AlGaN barrier was observed. Power measurements on a 2/spl times/125/spl times/0.3 /spl mu/m AlGaN/GaN HEMT made on Silicon Carbide (SiC) substrates with an AlGaN thickness of 10 nm gave a saturated output power of 1.23 W/mm at 8 GHz whereas a device with the same dimensions fabricated on samples with an AlGaN barrier of 20 nm gave a saturated output power of 2.65 W/mm at the same frequency. RF load line measurements clearly show the reduction of RF full channel current as compared to dc full channel current and the increase in the RF knee voltage compared to the dc knee voltage, with the effect being more pronounced in thin barrier samples. Passivation improved the large signal performance of these devices. A 1/spl times/150/spl times/0.3 /spl mu/m transistor made on AlGaN(20 nm)/GaN structure gave a saturated output power of 10.7 W/mm (40% power added efficiency) at 10 GHz after passivation. This represents the state of the art microwave power density for AlGaN/GaN HEMTs. Heating of the transistors during high-power operation of these devices becomes the important factor in limiting their performance after passivation.
182 citations
TSMC1
TL;DR: In this article, an analytical model to represent line edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices is presented.
Abstract: This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into small unit cells along its width, each unit cell assumes a constant gate length (i.e., cell's width is small compared to LER spatial frequency). An analytical model is used to represent saturated threshold voltage dependency on the unit cell's gate length. Using this technique, an efficient and accurate model for LER effects (through V/sub ts/ variations) on off-state leakage and drive current is proposed and experimentally validated using 193 and 248 nm lithography for devices with 80-nm nominal gate lengths. Assuming that the deviation from the ideal 0-LER case remains constant from generation to generation, the model predicts that 3 nm or less LER is required for 50-60-nm state-of-the-art devices in the 0.1-/spl mu/m technology node. Based on data presented, we suggest that the LER requirement for this technology node is attainable with an alternated phase-shift type of patterning process.
TL;DR: In this paper, the frequency dependence of PECVD nitride and LPCVD oxide metal-insulator-metal (MIM) capacitors is investigated with special attention for precision analog applications.
Abstract: The frequency dependence of PECVD nitride and LPCVD oxide metal-insulator-metal (MIM) capacitors is investigated with special attention for precision analog applications. At measurement frequencies of 1.0 MHz, nitride MIM capacitors show capacitance linearity close to that of oxide MIM capacitors, indicating potential for precision analog circuit applications. Due to dispersion effects, however, nitride MIM capacitors show significant degradation in capacitor linearity as the frequency is reduced, which leads to accuracy limitations for precision analog circuits. Oxide MIM capacitors are essentially independent of frequency.
TL;DR: In this article, MOCVD-grown NpN InP/GaAsSb/InP abrupt double heterojunction bipolar transistors (DHBTs) with simultaneous values of f/sub T/ and F/sub MAX/ as high as 300 GHz at V/sub CE/=1.8 V were reported.
Abstract: We report MOCVD-grown NpN InP/GaAsSb/InP abrupt double heterojunction bipolar transistors (DHBTs) with simultaneous values of f/sub T/ and f/sub MAX/ as high as 300 GHz for J/sub C/=410 kA/cm/sup 2/ at V/sub CE/=1.8 V. The devices maintain outstanding dynamic performances over a wide range of biases including the saturation mode. In this material system the p+ GaAsSb base conduction band edge lies 0.10-0.15 eV above the InP collector conduction band, thus favoring the use of nongraded base-collector designs without the current blocking effect found in conventional InP/GaInAs-based DHBTs. The 2000 /spl Aring/ InP collector provides good breakdown voltages of BV/sub CEO/=6 V and a small collector signal delay of /spl sim/0.23 ps. Thinner 1500 /spl Aring/ collectors allow operation at still higher currents with f/sub T/>200 GHz at J/sub C/=650 kA/cm/sup 2/.
TL;DR: In this paper, the authors show that commonly used techniques for experimentally determining carrier velocity are insufficient to determine how close modern MOSFETs operate to the ballistic or "thermal limit."
Abstract: Continued success in scaling bulk MOSFETs has brought increasing focus on fundamental performance limits. It has been proposed that drain current is ultimately limited by the rate at which carriers can be thermally injected from the source into the channel. In this work, we show that commonly used techniques for experimentally determining carrier velocity are insufficient to determine how close modern MOSFETs operate to the ballistic or "thermal limit." We propose a new technique and show that an advanced 1 V NMOS technology with L/sub eff/<50 nm operates at no more than /spl sim/40% of the limiting thermal velocity.
TL;DR: In this article, double-gate MOSFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process, and the electrical gate oxide thickness in these devices is determined from the first FinFET capacitance-versus-voltage characteristics obtained to date.
Abstract: N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 /spl mu/A//spl mu/m (or 1 mA//spl mu/m, depending on the definition of the width of the double-gate device) for V/sub g/-V/sub t/=V/sub d/=1 V. The electrical gate oxide thickness in these devices is 21 /spl Aring/, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness.
TL;DR: The first high voltage npn bipolar junction transistors (BJTs) in 4H-SiC have been demonstrated in this article, where the BJTs were able to block 1800 V in common emitter mode and showed a peak current gain of 20 and an on-resistance of 10.8 m/spl Omega/spl middot/cm/sup 2/ at room temperature (I/sub C/=2.7 A @ V/sub CE/= 2 V for a 1 mm/spl times/1.4 mm active area).
Abstract: The first high voltage npn bipolar junction transistors (BJTs) in 4H-SiC have been demonstrated. The BJTs were able to block 1800 V in common emitter mode and showed a peak current gain of 20 and an on-resistance of 10.8 m/spl Omega//spl middot/cm/sup 2/ at room temperature (I/sub C/=2.7 A @ V/sub CE/=2 V for a 1 mm/spl times/1.4 mm active area), which outperforms all SiC power switching devices reported to date. Temperature-stable current gain was observed for these devices. This is due to the higher percent ionization of the deep level acceptor atoms in the base region at elevated temperatures, which offsets the effects of increased minority carrier lifetime at high temperatures. These transistors show a positive temperature coefficient in the on-resistance characteristics, which will enable easy paralleling of the devices.
TL;DR: In this paper, the full channel charge of an AlGaN/GaN heterostructure FET may be completely depleted under specific bias conditions, where the output current amplitude is drastically reduced.
Abstract: Current dispersion effects have been experimentally investigated in a variety of AlGaN/GaN heterostructure FETs with large signal and switching measurements including HEMTs with doped and undoped barrier layer. A range of dispersion frequencies from 10/sup -3/ Hz to 10 GHz were observed, where the output current amplitude is drastically reduced. Through this effect the full channel charge of an AlGaN/GaN heterostructure FET may be completely depleted under specific bias conditions. This indicates that this phenomena cannot be related to deep traps alone, but is also connected to piezorelated charge states and conduction to these states.
TL;DR: In this article, a Si-doped In/sub 0.23/N/GaN short-period superlattice (SPS) tunneling contact was grown by metalorganic vapor phase epitaxy.
Abstract: InGaN/GaN multiple-quantum-well light-emitting diode (LED) structures including a Si-doped In/sub 0.23/Ga/sub 0.77/N/GaN short-period superlattice (SPS) tunneling contact were grown by metalorganic vapor phase epitaxy. In/sub 0.23/Ga/sub 0.77/N/GaN(n/sup +/)-GaN(p) tunneling junction, the low-resistivity n/sup +/-In/sub 0.3/Ga/sub 0.77/N/GaN SPS instead of high-resistivity p-type GaN as a top contact layer, allows the reverse-biased tunnel junction to form an "ohmic" contact. In this structure, the sheet electron concentration of Si-doped In/sub 0.23/Ga/sub 0.77/N/GaN SPS is around 1/spl times/10/sup 14//cm/sup 2/, leading to an averaged electron concentration of around 1/spl times/10/sup 20//cm/sup 3/. This high-conductivity SPS would lead to a low-resistivity ohmic contact (Au/Ni/SPS) of LED. Experimental results indicate that the LEDs can achieve a lower operation voltage of around 2.95 V, i.e., smaller than conventional devices which have an operation voltage of about 3.8 V.
TL;DR: In this article, a simple measurement technique to spatially characterize channel hot electron injection is presented, and it is shown that subthreshold slope degradation during programming of NROM/sup TM/device provides the location and distribution of injected electrons.
Abstract: Channel hot electron (CHE) injection, is widely used as main programming method in flash products. The spatial distribution could only be measured indirectly through stress-based experiments. A simple measurement technique to spatially characterize CHE injection is presented. It is shown that subthreshold slope degradation during programming of NROM/sup TM/ device provides the location and distribution of the injected electrons. It is shown that injection takes place mostly above the drain region and thus, results in subthreshold slope degradation. It is further shown, based on two-dimensional modeling, that charge distribution width is narrower than 40 nm.
TL;DR: In this article, a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide field effect transistors (N-MOSFETs) was presented.
Abstract: We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.
TL;DR: In this paper, the authors investigate how effective electron mobility at low lateral electric fields relates to velocity in the MOSFET saturation regime, where lateral fields in the channel are high.
Abstract: The importance of low-field mobility to the performance of deep-sub-100-nm bulk MOSFETs is not well understood. In this work, we investigate experimentally how effective electron mobility at low lateral electric fields relates to velocity in the MOSFET saturation regime, where lateral fields in the channel are high. For short (L/sub eff//spl ap/45 nm) NMOS devices, mobility is modified by externally applying uniaxial stress and the corresponding shifts in electron velocity are found to be significant.
TL;DR: In this paper, a novel HEMT configuration based on the RESURF technique was proposed for very high voltage power switching applications, which employs a p-n junction below the 2-DEG channel and two field plates, one extending from the gate and the other from the drain, to distribute the electric field over the gate to drain separation.
Abstract: A novel HEMT configuration based on the RESURF technique is proposed for very high voltage power switching applications. It employs a p-n junction below the 2-DEG channel and two field plates, one extending from the gate and the other from the drain, to distribute the electric field over the gate to drain separation. 2-D simulations indicate a breakdown voltage >1 KV at on-resistance of /spl sim/1 m/spl Omega//spl middot/cm/sup 2/ (neglecting contact resistances) for the device.
TL;DR: In this article, the oxide-bypassed VDMOS (OBVDMOS) was proposed to overcome the charge balance requirement and inter-diffusion problem of superjunction.
Abstract: The superjunction concept has been proposed to overcome the ideal silicon MOSFET limit, but its fabrication was handicapped by the precise charge balance requirement and inter-diffusion problem. We report a novel device structure termed oxide-bypassed VDMOS (OBVDMOS) that requires the well-established oxide thickness control instead of the difficult doping control in translating the limit to a higher blocking voltage. This is done by using metal-thick-oxide (MTO) at the sidewalls of drift region. One can choose to have a higher blocking voltage or increase the background doping. A PiN structure, essentially identical to MOSFET during off state, was fabricated to demonstrate the proposed concept. Its measured BV/sub dss/ of 170 V is 2.5 times higher than measured conventional device BV/sub dss/ of 67 V on the same silicon wafer.
TL;DR: In this article, the microwave performance of a diamond metal-semiconductor field effect transistor (MESFET) was reported for the first time, with a gate length of 2-3 /spl mu/m and a source-gate spacing of 0.1 /spl µ/m.
Abstract: The microwave performance of a diamond metal-semiconductor field-effect transistor (MESFET) is reported for the first time. MESFETs with a gate length of 2-3 /spl mu/m and a source-gate spacing of 0.1 /spl mu/m were fabricated on the hydrogen-terminated surface of an undoped diamond film grown by microwave plasma chemical vapor deposition (CVD) utilizing a self-aligned gate fabrication process. A maximum transconductance of 70 mS/mm was obtained on a 2 /spl mu/m gate MESFET at V/sub GS/=-1.5 V and V/sub DS/=-5 V,for which a cutoff frequency f/sub T/ and a maximum oscillating frequency f/sub max/ of 2.2 GHz and 7 GHz were obtained, respectively.
IBM1
TL;DR: In this paper, a 210 GHz f/sub T/SiGe heterojunction bipolar transistor at a collector current density of 6-9 mA/spl mu/m/sup 2/ is fabricated with a new non-self-aligned (NSA) structure based on 0.18 /spl µ/m technology.
Abstract: A record 210-GHz f/sub T/ SiGe heterojunction bipolar transistor at a collector current density of 6-9 mA//spl mu/m/sup 2/ is fabricated with a new nonself-aligned (NSA) structure based on 0.18 /spl mu/m technology. This NSA structure has a low-complexity emitter and extrinsic base process which reduces overall thermal cycle and minimizes transient enhanced diffusion. A low-power performance has been achieved which requires only 1 mA collector current to reach 200-GHz f/sub T/. The performance is a result of narrow base width and reduced parasitics in the device. Detailed comparison is made to a 120-GHz self-aligned production device.
TL;DR: In this article, a novel salicide technology to improve the thermal stability of the conventional Ni silicide has been developed by employing Ni(Pt) alloy salicidation, which provides an effective avenue to overcome the low thermal budget (<700/spl deg/C) of the traditional Ni silicidation by forming NiSiSi.
Abstract: A novel salicide technology to improve the thermal stability of the conventional Ni silicide has been developed by employing Ni(Pt) alloy salicidation. This technique provides an effective avenue to overcome the low thermal budget (<700/spl deg/C) of the conventional Ni salicidation by forming Ni(Pt)Si. The addition of Pt has enhanced the thermal stability of NiSi. Improved sheet resistance of the salicided narrow poly-Si and active lines was achieved up to 750/spl deg/C and 700/spl deg/C for as-deposited Ni(Pt) thickness of 30 nm and 15 nm, respectively. This successfully extends the rapid thermal processing (RTP) window by delaying the nucleation of NiSi/sub 2/ and agglomeration. Implementation of Ni(Pt) alloyed silicidation was demonstrated on PMOSFETs with high drive current and low junction leakage.
TL;DR: In this article, the saturation current was as high as 5.1 A for a 6 mm wide device with a gate leakage of 1 /spl mu/A/cm/sup 2/ for 1.5 /spl µ/m gate length.
Abstract: We report on AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor (HFET) over SiC substrates with peripheries from 0.15 to 6 mm. These multigate devices with source interconnections were fabricated using a novel oxide-bridging approach. The saturation current was as high as 5.1 A for a 6 mm wide device with a gate leakage of 1 /spl mu/A/cm/sup 2/ for 1.5 /spl mu/m gate length in a 5 /spl mu/m source-drain opening. The cutoff frequency of around 8 GHz was practically independent of the device periphery. Large-signal output rf-power as high as 2.88 W/mm was measured at 2 GHz. Both the saturation current and the rf-power scaled nearly linearly with the gate width.
TL;DR: In this article, an excellent cutoff frequency (f/sub t/) as high as 400 GHz was achieved in 45nm-gate pseudomorphic InGaAs/InAlAs high electron mobility transistors (HEMTs).
Abstract: An excellent cutoff frequency (f/sub t/) as high as 400 GHz was successfully realized in 45-nm-gate pseudomorphic InGaAs/InAlAs high electron mobility transistors (HEMTs). An additional vertical gate-recess suppressed short-channel effects, while keeping good pinchoff characteristics. Gate length (L/sub g/) dependence of electron transit time (/spl tau//sub transit/) implied an increased saturation velocity (/spl upsi//sub s/) of 3.6/spl times/10/sup 7/ cm/s in the developed pseudomorphic HEMTs. This f/sub t/ is the highest value ever reported for any transistors to date.
TL;DR: In this article, the authors have succeeded in fabricating ultra-short 25-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates.
Abstract: We have succeeded in fabricating ultra-short 25-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates. The two-step-recessed gate technology and low temperature processing at below 300/spl deg/C allowed the fabrication of such ultra-short gates. DC measurements showed that the 25-nm-gate HEMT had good pinchoff behavior. We obtained a cutoff frequency f/sub T/ of 396 GHz, within the range of 400 GHz f/sub T/, for the 25-nm-gate HEMT. This f/sub T/ is the highest value get reported for any type of transistor, and the gate length of 25 nm is the shortest value ever reported for any compound semiconductor transistor that exhibits device operation.
TL;DR: In this paper, the results of an extensive ensemble of the most advanced available quantum-mechanical capacitancevoltage (C-V) simulation and analysis packages for a range of metal-oxide-semiconductor device parameters were systematically compared.
Abstract: We have systematically compared the results of an extensive ensemble of the most advanced available quantum-mechanical capacitance-voltage (C-V) simulation and analysis packages for a range of metal-oxide-semiconductor device parameters. While all have similar trends accounting for polysilicon depletion and quantum-mechanical confinement, quantitatively, there is a difference of up to 20% in the calculated accumulation capacitance for devices with ultrathin gate dielectrics. This discrepancy leads to large inaccuracies in the values of dielectric thickness extracted from capacitance measurements and illustrates the importance of consistency during C-V analysis and the need to fully report how such analysis is done.