Showing papers in "IEEE Electron Device Letters in 2005"

High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment

Abstract: We report a novel approach in fabricating high-performance enhancement mode (E-mode) AlGaN/GaN HEMTs. The fabrication technique is based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing with an annealing temperature lower than 500/spl deg/C. Starting with a conventional depletion-mode HEMT sample, we found that fluoride-based plasma treatment can effectively shift the threshold voltage from -4.0 to 0.9 V. Most importantly, a zero transconductance (g/sub m/) was obtained at V/sub gs/=0 V, demonstrating for the first time true E-mode operation in an AlGaN/GaN HEMT. At V/sub gs/=0 V, the off-state drain leakage current is 28 /spl mu/A/mm at a drain-source bias of 6 V. The fabricated E-mode AlGaN/GaN HEMTs with 1 /spl mu/m-long gate exhibit a maximum drain current density of 310 mA/mm, a peak g/sub m/ of 148 mS/mm, a current gain cutoff frequency f/sub T/ of 10.1 GHz and a maximum oscillation frequency f/sub max/ of 34.3 GHz.

High-power AlGaN/GaN HEMTs for Ka-band applications

Abstract: We report on the fabrication and high-frequency characterization of AlGaN/GaN high-electron mobility transistors (HEMTs) grown by molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD). In devices with a gate length of 160 nm, a record power density of 10.5 W/mm with 34% power added efficiency (PAE) has been measured at 40 GHz in MOCVD-grown HEMTs biased at V/sub DS/=30 V. Under similar bias conditions, more than 8.6 W/mm, with 32% PAE, were obtained on the MBE-grown sample. The dependence of output power, gain, and PAE on gate and drain voltages, and frequency have also been analyzed.

Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)

Abstract: Physical models are used to determine the ultimate potential performance of carbon nanotube interconnects and compare them with minimum-size copper wires implemented at various technology generations. Results offer important guidance regarding the nature of carbon nanotube technology development needed for improving interconnect performance. Since wave propagation is slow in a single nanotube, nanotube bundles with larger wave speeds must be used. At the 45-nm node (year 2010), the performance enhancement that can be achieved by using nanotube bundles is negligible, and at the 22-nm node (year 2016) it can be as large as 80%.

Impact of NBTI on the temporal performance degradation of digital circuits

Abstract: Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.

Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs

Abstract: Quantum-mechanical (QM), or carrier energy-quantization, effects on the subthreshold characteristics, including the threshold voltage (V/sub t/), of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled. The analytic model, with dependences on the UTB thickness (t/sub Si/), the transverse electric field, and the UTB surface orientation, shows how V/sub t/ is increased, and reveals that 1) the subthreshold carrier population in higher-energy subbands is significant, 2) the QM effects in DG devices with {110}-Si surfaces, common in FinFETs, are comparable to those for {100}-Si surfaces for t/sub Si/>/spl sim/4 nm, 3) the QM effects can increase the gate swing, and (iv) the QM effects, especially for t/sub Si/

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

Abstract: We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

Abstract: High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm/sup 2//V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1/spl times/10/sup -14/ A//spl mu/m when V/sub d/ equals -0.1 V.

Resistance switching of the nonstoichiometric zirconium oxide for nonvolatile memory applications

Abstract: The resistance switching behavior and switching mechanism of nonstoichiometric zirconium oxide thin films were investigated for nonvolatile memory application. The Pt/ZrO/sub x//p/sup +/-Si sandwich structure fabricated by reactive sputtering shows two stable resistance states. By applying proper bias, resistance switching from one to another state can be obtained. The composition in ZrO/sub x/ thin films were confirmed from X-ray photoelectron spectroscope (XPS) analysis, which showed three layers such as top stoichiometric ZrO/sub 2/ layer with high resistance, transition region with medium resistance, and conducting ZrO/sub x/ bulk layer. The resistance switching can be explained by electron trapping and detrapping of excess Zr/sup +/ ions in transition layer which control the distribution of electric field inside the oxide, and, hence the current flow.

Schottky barrier diodes for millimeter wave detection in a foundry CMOS process

Abstract: CoSi/sub 2/-Si Schottky barrier diodes on an n-well and on a p-well/substrate are fabricated without a guard ring in a 130-nm foundry CMOS process. The nand p-type diodes with an area of 16/spl times/0.32/spl times/0.32 /spl mu/m/sup 2/ achieve cutoff frequencies of /spl sim/1.5 and /spl sim/1.2 THz at 0-V bias, respectively. These are the highest cutoff frequencies for Schottky diodes fabricated in foundry silicon processes. The leakage currents at 1.0-V reverse bias vary between 0.4 to 10 nA for the n-type diodes. The break down voltage for these diodes is around 15 V. It should be possible to use these in millimeter wave and far infrared detection.

High-performance dual-gate carbon nanotube FETs with 40-nm gate length

Abstract: We report on a high-performance back-gated carbon nanotube field-effect transistor (CNFET) with a peak transconductance of 12.5 /spl mu/S and a delay time per unit length of /spl tau//L=19 ps//spl mu/m. In order to minimize the parasitic capacitances and optimize the performance of scaled CNFETs, we have utilized a dual-gate design and have fabricated a 40-nm-gate CNFET possessing excellent subthreshold and output characteristics without exhibiting short-channel effects.

High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide Schottky source/drain

Abstract: We demonstrate, for the first time, successful operation of Schottky-barrier source/drain (S/D) germanium-on-insulator (GOI) MOSFETs, where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. Excellent performance of p-type MOSFETs using Pt germanide S/D is presented in the accumulation mode. The hole mobility enhancement of 50%/spl sim/40% against the universal hole mobility of Si MOSFETs is obtained for the accumulated GOI channel with the SiO/sub 2/-Ge interface.

Improved reliability of AlGaN-GaN HEMTs using an NH/sub 3/ plasma treatment prior to SiN passivation

Abstract: A passivation method has been developed which reduces the degradation of AlGaN-GaN high electron mobility transistor (HEMT) electrical properties caused by extended dc bias or microwave power operation. The key aspect of this passivation technique is exposure to a low-power NH/sub 3/ plasma prior to SiN deposition. Devices fabricated with the NH/sub 3/ treatment prior to SiN passivation show minimal gate lag and current collapse after extended dc bias operation. In addition, the rate of degradation of the microwave power output while under continuous microwave operation is improved by at least 100 times as compared to SiN passivated HEMTs that were not treated with the NH/sub 3/ plasma.

Resistance-switching Characteristics of polycrystalline Nb/sub 2/O/sub 5/ for nonvolatile memory application

Abstract: The resistance switching characteristics of polycrystalline Nb/sub 2/O/sub 5/ film prepared by pulsed-laser deposition (PLD) were investigated for nonvolatile memory application. Reversible resistance-switching behavior from a high resistance state to a lower state was observed by voltage stress with current compliance. The reproducible resistance-switching cycles were observed and the resistance ratio was as high as 50-100 times. The resistance switching was observed under voltage pulse as short as 10 ns. The estimated retention lifetime at 85/spl deg/C was sufficiently longer than ten years. Considering its excellent electrical and reliability characteristics, Nb/sub 2/O/sub 5/ shows strong promise for future nonvolatile memory applications.

Bonded planar double-metal-gate NMOS transistors down to 10 nm

Abstract: Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

Gate-recessed AlGaN-GaN HEMTs for high-performance millimeter-wave applications

Abstract: We report deep-submicrometer gate-recessed and field-plated AlGaN-GaN HEMTs and their state-of-the-art continuous wave (CW) power performance measured at 30 GHz. The AlGaN-GaN HEMTs exhibit a CW power density of 5.7 W/mm with a power-added efficiency (PAE) of 45% and drain-efficiency of 58% at V/sub ds/=20 V. At V/sub ds/=28 V, the output power density is measured as high as 6.9 W/mm with both PAE and output power increasing with input power level. Compared to conventional T-gated AlGaN-GaN HEMTs, the output power density and PAE of gate-recessed AlGaN-GaN HFETs are improved greatly, along with the excellent pulsed IVs. We attribute the improvement to both a field-plating effect and a vertical separation of the gate plane from surface states.

Ion implanted AlGaN-GaN HEMTs with nonalloyed Ohmic contacts

Abstract: In this letter, the incorporation of Si implantation into AlGaN-GaN high-electron mobility transistor (HEMT) processing has been demonstrated. An ultrahigh-temperature (1500/spl deg/C) rapid thermal annealing technique was developed for the activation of Si dopants implanted in the source and drain. In comparison to control devices processed by conventional fabrication, the implanted device with nonalloyed ohmic contact showed comparable device performance with a contact resistance of 0.4 /spl Omega//spl middot/mm, I/sub max/ of 730 mA/mm, f/sub t//f/sub max/ of 26/62 GHz, and a power of 3.4 W/mm on sapphire. These early results demonstrate the feasibility of implantation incorporation into GaN-based device processing as well as the potential to increase yield, reproducibility, and reliability in AlGaN-GaN HEMTs.

Bistable resistive switching of a sputter-deposited Cr-doped SrZrO/sub 3/ memory film

Abstract: Sputter-deposited Cr-doped SrZrO/sub 3/-based metal-insulator-metal structures exhibited bistable resistive reversible switching as observed under bias voltage and voltage pulse. The ratio of resistance of the two leakage states (high-H, low-L) was about five orders of magnitude. The conduction of the L-state satisfied Frenkel-Poole emission and that of the H-state followed ohmic mechanism, causing the resistance ratio to decrease with increasing bias voltage. The transition time of H- to L-state was five orders of magnitude higher than that of L- to H-state. The transition from H- to L-state was the restricted part for reversible switching operation. The difference in transition time of the two states should be related to the respective conduction mechanisms.

A spintronics full adder for magnetic CPU

Abstract: Spintronics devices are based on the up or down spin of the electrons rather than on electrons or holes as in the traditional semiconductor electronics devices. Magnetic processors using spintronics devices in principle are much faster and with the potential features of nonvolatile, lower power consumption and higher integration density compared with transistor-based microprocessor. Full adder is one of the most important basic units of the arithmetic/logic unit for any processors. The design of the full adder determines the speed and chip-density of a processor. In this paper, a novel spintronics full adder is proposed based on novel programmable spintronics logic devices. Only seven magnetic tunnel junction elements are needed for this full adder design.

Germanium pMOSFETs with Schottky-barrier germanide S/D, high-/spl kappa/ gate dielectric and metal gate

Abstract: Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as /spl sim/5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.

Pentacene TFT driven AM OLED displays

Abstract: Pentacene organic thin-film transistors (TFTs)-driven active matrix organic light-emitting diode (OLED) displays has been investigated. This letter addresses several process issues unique to this type of display which are important in achieving bright and uniform displays. A bottom contact structure was used to fabricate the pentacene TFT backplane. Polyvinyl alcohol and parylene were used to isolate the pentacene active layer and passivate the backplane. The low processing temperature may allow the use of polymeric substrates and lower cost processing. Uniform TFT performance is achieved with reasonably good mobility and on/off ratio on the backplane. The initial OLED display performance is also presented.

A new a-Si:H TFT pixel circuit compensating the threshold voltage shift of a-Si:H TFT and OLED for active matrix OLED

Abstract: We propose a new hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel circuit for an active matrix organic light-emitting diode (AMOLED) employing a voltage programming. The proposed a-Si:H TFT pixel circuit, which consists of five switching TFTs, one driving TFT, and one capacitor, successfully minimizes a decrease of OLED current caused by threshold voltage degradation of a-Si:H TFT and OLED. Our experimental results, based on the bias-temperature stress, exhibit that the output current for OLED is decreased by 7% in the proposed pixel, while it is decreased by 28% in the conventional 2-TFT pixel.

High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

Abstract: A new approach to form strained SiGe-on-insulator (SGOI) channel transistors, allowing fabrication of MOSFETs with very high Ge fraction in selected areas on a silicon-on-insulator substrate, is demonstrated. This method consists of epitaxial growth of an SiGe layer with a low Ge fraction and local oxidation processes. An obtained SGOI pMOSFET with a Ge fraction of 0.93 exhibits up to a tenfold enhancement in mobility. It is also found that MOSFETs having strained SGOI channels with thicknesses of less than 5 nm exhibit hole-mobility enhancement factors of over two. These results indicate that the local SGOI channels fabricated by the proposed technique are promising for implementation of high-mobility SiGe or Ge-channel MOSFETs in system-on-chip (SoC) devices.

Monolayer metallic nanotube interconnects: promising candidates for short local interconnects

Abstract: Mono- or bi-layer metallic single-wall carbon nanotube interconnects have lateral capacitances more than four times smaller than those of copper interconnects. The resistance and time-of-flight of these monolayer nanotubes would be larger than that of copper interconnects. For short lengths, however, driver resistance is quite dominant, and latency is determined by interconnect capacitance. Monolayer nanotube interconnects are therefore promising candidates for local interconnects. The average capacitance per unit length of these nanotube interconnects can be 50% smaller than that of copper interconnects and that leads to significant saving in power dissipation.

1000-V, 30-A 4H-SiC BJTs with high current gain

Abstract: This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.

Mechanism of current collapse removal in field-plated nitride HFETs

Abstract: An experimental study of the mechanism of RF current collapse removal in high-power nitride-based HFETs is presented. The results show that the conductivity of the dielectric material under the field plate plays a crucial role in the current collapse removal. Identical geometry field plated HFETs differing only in the FP dielectric conductivity show varying degree of current collapse removal. Devices with semiconducting dielectric layers exhibit perfectly linear RF power - drain bias dependence with the output powers of 20 W/mm at 55 V drain bias with essentially no current collapse. A trapped charge discharging model is presented to explain the removal of current collapse in FPd devices.

Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si

Abstract: We have successfully demonstrated high-performance p-MOSFETs in germanium grown directly on Si using a novel heteroepitaxial growth technique, which uses multisteps of hydrogen annealing and growth to confine misfit dislocations near the Ge-Si interface, thus not threading to the surface as expected in this 4.2% lattice-mismatched system. We used a low thermal budget process with silicon dioxide on germanium oxynitride (GeO/sub x/N/sub y/) gate dielectric and Si/sub 0.75/Ge/sub 0.25/ gate electrode. Characterization of the device using cross-sectional transmission electron microscopy and atomic force microscopy at different stages of the fabrication illustrates device-quality interfaces that yielded hole effective mobility as high as 250 cm/sup 2//Vs.

A novel a-Si:H AMOLED pixel circuit based on short-term stress stability of a-Si:H TFTs

Abstract: This letter presents a novel pixel circuit for hydrogenated amorphous silicon (a-Si:H) active matrix organic light-emitting diode displays employing the short-term stress stability characteristics of a-Si:H thin film transistors (TFTs). The pixel circuit uses a programming TFT that is under stress during the programming cycle and unstressed during the drive cycle. The threshold voltage shift (V/sub T/-shift) of the TFT under these conditions is negligible. The programming TFT in turn regulates the current of the drive TFT, and the pixel current therefore becomes independent of the threshold voltage of the drive TFT.

Direct extraction of mobility in pentacene OFETs using C-V and I-V measurements

Abstract: Mobility was extracted from top-contact pentacene organic field effect transistors with minimal assumptions. Low-frequency capacitance-voltage (C-V) measurements were used to calculate the sheet charge density of the channel, and current-voltage measurements with low drain-to-source voltage were used to extract mobility. The separation of charge and mobility with the use of C-V measurements illustrates that the mobility increases with gate voltage, differing significantly from mobility dependence on gate voltage in crystal silicon MOSFETs. The physical meaning of this mobility and the possible mechanism for the increase in mobility as a function of gate bias are discussed.

A new Pd-InP Schottky hydrogen sensor fabricated by electrophoretic deposition with Pd nanoparticles

Abstract: In this letter, a new Pd-InP Schottky diode hydrogen sensor fabricated by electrophoretic deposition (EPD) combined with nanosized Pd particles is first proposed and demonstrated. Experimentally, the studied device exhibited excellent current-voltage rectifying characteristics with a large Schottky barrier height (SBH) of 829 meV. At 303 K, a high saturation sensitivity ratio of 38 was found under a very low hydrogen concentration of 15 ppm H/sub 2//air. As raising the hydrogen concentration to 1.0% H/sub 2//air, the SBH lowering of the studied devic"dq"e reached to 307 meV and the sensitivity ratio was high as 1.29/spl times/10/sup 5/ with a very rapid response, which far prevailed over those fabricated by the conventional thermal evaporation and electroless plating techniques. Consequentially, the EPD Pd-InP Schottky diode with extremely effective Pd gate is promising for the fabrication of high-performance hydrogen sensors.

Experimental study on superior mobility in [110]-oriented UTB SOI pMOSFETs

Abstract: The superior mobility in [110]-oriented ultrathin body (UTB) pMOSFETs with silicon-on-insulator (SOI) thickness (t/sub SOI/) ranging from 32 down to 2.3 nm is experimentally examined for the first time. It is shown that the mobility in [110] UTB pMOSFETs, which is much higher than the universal curve in conventional (100) pMOSFETs, is not degraded until t/sub SOI/ is thinned to 3 nm. Scattering mechanisms in [110] UTB pMOSFETs are discussed on the basis of the temperature dependence of the mobility. The high mobility in the UTB regime in [110] pMOSFET is attributed to subband modulation by carrier confinement and heavier hole effective mass normal to the channel surface.