Showing papers in "IEEE Electron Device Letters in 2007"

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

A Graphene Field-Effect Device

Abstract: In this letter, a top-gated field-effect device (FED) manufactured from monolayer graphene is investigated. Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from the top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-insulator MOSFETs

Simulation of Graphene Nanoribbon Field-Effect Transistors

Abstract: We present an atomistic 3-D simulation of graphene nanoribbon field-effect transistors (GNR-FETs), based on the self consistent solution of the 3-D Poisson and Schrodinger equations with open boundary conditions within the nonequilibrium Green's function formalism and a tight-binding Hamiltonian. With respect to carbon nanotube FETs, GNR-FETs exhibit comparable performance, reduced sensitivity to the variability of channel chirality, and similar leakage problems due to band-to-band tunneling. Acceptable transistor performance requires prohibitive effective nanoribbon width of 1-2 nm and atomistic precision that could in principle be obtained with periodic etch patterns or stress patterns.

Effect of Top Electrode Material on Resistive Switching Properties of $\hbox{ZrO}_{2}$ Film Memory Devices

Abstract: The influence of top electrode material on the resistive switching properties of ZrO2-based memory film using Pt as a bottom electrode was investigated in this letter. In comparison with Pt/ZrO2/Pt and Al/ZrO2/Pt devices, the Ti/ZrO2/Pt device exhibits different resistive switching current-voltage (I- V) curve, which can be traced and reproduced by a dc voltage more than 1000 times only showing a little decrease of resistance ratio between high and low resistance states. Furthermore, the broad dispersions of resistive switching characteristics in the Pt/ZrO2/Pt and Al/ZrO2/Pt devices are generally observed during successive resistive switching, but those dispersions are suppressed by the device using Ti as a top electrode. The reliability results, such as cycling endurance and continuous readout test, are also presented. The write-read-erase-read operations can be over 104 cycles without degradation. No data loss is found upon successive readout after performing various endurance cycles

Conductance Modeling for Graphene Nanoribbon (GNR) Interconnects

Abstract: Graphene nanoribbons (GNRs), which are single graphene sheets, share many of the fascinating electronic, mechanical, and thermal properties of carbon nanotubes. Compact physical models for conductance of GNRs as functions of chirality, width, Fermi level, and the type of electron scatterings at the edges are presented. For widths below 8 nm, the models demonstrate that single-layer GNRs can potentially outperform copper wires with unity aspect ratio

A New Degradation Mechanism in High-Voltage SiC Power MOSFETs

Abstract: The phenomenon of recombination-induced stacking faults in high-voltage p-n diodes in SiC has been previously shown to increase the forward voltage drop due to reduction of minority carrier lifetime. In this paper, it has been shown that, for the first time, this effect is equally important in unipolar devices such as high-voltage MOSFETs. If the internal body diode is allowed to be forward biased during the operation of these devices, then the recombination-induced SFs will reduce the majority carrier conduction current and increase the leakage current in blocking mode. The effect is more noticeable in high-voltage devices where the drift layer is thick and is not expected to impact 600-1200-V devices.

Design and Fabrication of Elastic Interconnections for Stretchable Electronic Circuits

Abstract: For biomedical and textile applications, the comfort of the user will be enhanced if the electronic circuits are not only flexible but also elastic. This letter reveals a simple moulded-interconnect-device technology for the construction of elastic point-to-point interconnections, based on 2-D spring-shaped metallic tracks, which are embedded in a highly elastic silicone film. Metal interconnections of 3-cm long were constructed with an initial resistance of about 3Omega , which did not significantly increase (<5%) when stretched. A stretchability above 100% in one direction has been demonstrated.

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Gate Dielectric

Abstract: High-performance inversion-type enhancement-mode n-channel In053Ga047As MOSFETs with atomic-layer-deposited (ALD) Al2O3 as gate dielectric are demonstrated The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general A 05-mum gate-length MOSFET with an Al2O3 gate oxide thickness of 8 nm shows a gate leakage current less than 10-4 A/cm2 at 3-V gate bias, a threshold voltage of 025 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V The midgap interface trap density of regrown Al2O3 on In053Ga047As is ~14 x 1012/cm2 ldr eV which is determined by low-and high-frequency capacitance-voltage method The peak effective mobility is ~1100 cm2 / V ldr s from dc measurement, ~2200 cm2/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 05-10-MV/cm effective electric field

Enhancement-Mode GaAs MOSFETs With an $\hbox{In}_{0.3} \hbox{Ga}_{0.7}\hbox{As}$ Channel, a Mobility of Over 5000 $ \hbox{cm}^{2}/\hbox{V} \cdot \hbox{s}$ , and Transconductance of Over 475 $\mu\hbox{S}/\mu\hbox{m}$

Abstract: We present metal-gate high-k-dielectric enhancement-mode (e-mode) III-V MOSFETs with the highest reported effective mobility and transconductance to date. The devices employ a GaGdO high-k (k = 20) gate stack, a Pt gate, and a delta-doped InGaAs/AlGaAs/GaAs hetero-structure. Typical 1-mum gate length device figures of merit are given as follows: saturation drive current, Id,sat = 407 muA/mum; threshold voltage, Vt = +0.26 V; maximum extrinsic transconductance, gm = 477 muS/mum (the highest reported to date for a III-V MOSFET); gate leakage current, Ig = 30 pA; subthreshold swing, S = 102 mV/dec; on resistance, Ron = 1920 Omega-mum; Ion/Ioff ratio = 6.3 x 104; and output conductance, gd = 11 mS/mm. A peak electron mobility of 5230 cm2/V. s was extracted from low-drain-bias measurements of 20 mum long-channel devices, which, to the authors' best knowledge, is the highest mobility extracted from any e-mode MOSFET. These transport and device data are highly encouraging for future high-performance n-channel complementary metal-oxide-semiconductor solutions based on III-V MOSFETs.

Physical Modeling of Temperature Coefficient of Resistance for Single- and Multi-Wall Carbon Nanotube Interconnects

Abstract: Equivalent circuit models are presented for the resistance of single- and multi-wall carbon nanotubes (MWCNs) that capture various electron-phonon scattering mechanisms as well as changes in the number of conduction channels as a function of temperature. For single- and few-wall nanotubes, the temperature coefficient of resistance (TCR) is always positive and increases with length. It reaches 1/(T-200 K) for lengths much larger than the electron mean free path, where T is the temperature in kelvin. For MWCNs with large diameters (>20 nm), TCR varies from -1/T to +0.66/(T-200 K) as the length varies from zero to very large values

AlGaN/GaN HEMTs With Thin InGaN Cap Layer for Normally Off Operation

Abstract: AlGaN/GaN HEMTs with a thin InGaN cap layer have been proposed to implement the normally off HEMTs. The key idea is to employ the polarization-induced field in the InGaN cap layer, by which the conduction band is raised, which leads to the normally off operation. The fabricated HEMT with an In0.2Ga0.8N cap layer with a thickness of 5 nm showed normally off operation with a threshold voltage of 0.4 V and a maximum transconductance of 85 mS/mm for the device with a 1.9-mum-long gate. By etching off the In0.2Ga0.8N cap layer at the access region using gate electrode as an etching mask, the maximum transconductance has increased from 85 to 130 mS/mm due to a reduction of the parasitic source resistance.

Comparison of GaN HEMTs on Diamond and SiC Substrates

Abstract: The performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) on diamond and SiC substrates is examined. We demonstrate GaN-on-diamond transistors with periphery WG = 250 mum, exhibiting ft = 27.4 GHz and yielding a power density of 2.79 W/mm at 10 GHz. Additionally, the temperature rise in similar devices on diamond and SiC substrates is reported. To the best of our knowledge, these represent the highest frequency of operation and first-reported thermal and X -band power measurements of GaN-on-diamond HEMTs.

Time-Resolved Temperature Measurement of AlGaN/GaN Electronic Devices Using Micro-Raman Spectroscopy

Abstract: We report on the development of time-resolved Raman thermography to measure transient temperatures in semiconductor devices with submicrometer spatial resolution. This new technique is illustrated for AlGaN/GaN HFETs and ungated devices grown on SiC and sapphire substrates. A temporal resolution of 200 ns is demonstrated. Temperature changes rapidly within sub-200 ns after switching the devices on or off, followed by a slower change in device temperature with a time constant of ~10 and ~140 mus for AlGaN/GaN devices grown on SiC and sapphire substrates, respectively. Heat diffusion into the device substrate is also demonstrated

A Novel LTPS-TFT Pixel Circuit Compensating for TFT Threshold-Voltage Shift and OLED Degradation for AMOLED

Abstract: This letter presents a novel pixel circuit that uses low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) composed of one driving and four switching TFTs for active-matrix organic light-emitting diodes (AMOLEDs) with a voltage-source method. The proposed circuit effectively enables threshold-voltage-shift correction of the drive TFT and compensates for degradation of the OLED using a feedback structure

Ultrahigh-Speed 0.5 V Supply Voltage $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ Quantum-Well Transistors on Silicon Substrate

Abstract: The direct epitaxial growth of ultrahigh-mobility InGaAs/InAlAs quantum-well (QW) device layers onto silicon substrates using metamorphic buffer layers is demonstrated for the first time. In this letter, 80 nm physical gate length depletion-mode InGaAs QW transistors with saturated transconductance gm of 930 muS / mum and fT of 260 GHz at VDS = 0.5 V are achieved on 3.2 mum thick buffers. We expect that compound semiconductor-based advanced QW transistors could become available in the future as very high-speed and ultralow-power device technology for heterogeneous integration with the mainstream silicon CMOS.

Fast Thin-Film Transistor Circuits Based on Amorphous Oxide Semiconductor

Abstract: Five-stage ring oscillators (ROs) composed of amorphous In/Ga/Zn/O (a-IGZO) channel thin-film transistors (TFTs) with the channel lengths of 10 mum were fabricated on a glass substrate. The a-IGZO layer was deposited by RF magnetron sputtering onto the unheated substrate. The RO operated at 410 kHz (the propagation delay of 0.24 mus/stage), when supplied with an external voltage of +18 V. This is the fastest integrated circuit based on oxide-semiconductor channel TFTs to date that operates faster than the ROs using conventional hydrogenated amorphous silicon TFTs and organic TFTs

Millimeter-Wave Bandpass Filters by Standard 0.18- $\mu\hbox{m}$ CMOS Technology

Abstract: Millimeter-wave (mm-wave) bandpass filters are presented using the standard 0.18-mum CMOS process. Without any postprocessing steps, thin film microstrip (TFMS) structure is properly constructed on the low-resistivity silicon substrate, aiming at reducing the substrate loss and crosstalk to a large extent. Using the broadside-coupled scheme, a tight coupling is achieved so as to make up a class of low-loss and broadband TFMS bandpass filters in the mm-wave range. To achieve a small size, one-stage and two-stage filters with sinuous-shaped resonators are designed and fabricated. A good agreement between the predicted and measured results has been observed up to 110 GHz

High-Temperature Operation of AlGaN/GaN HEMTs Direct-Coupled FET Logic (DCFL) Integrated Circuits

Abstract: This letter presents the high-temperature performance of AlGaN/GaN HEMT direct-coupled FET logic (DCFL) integrated circuits. At 375 degC, enhancement-mode (E-mode) AlGaN/GaN HEMTs which are used as drivers in DCFL circuits exhibit proper E-mode operation with a threshold voltage (VTH) of 0.24 V and a peak current density of 56 mA/mm. The monolithically integrated E/D-mode AlGaN/GaN HEMTs DCFL circuits deliver stable operations at 375 degC: An E/D-HEMT inverter with a drive/load ratio of 10 exhibits 0.1 V for logic-low noise margin (NML) and 0.3 V for logic-high-noise margin (NMH) at a supply voltage (VDD) of 3.0 V; a 17-stage ring oscillator exhibits a maximum oscillation frequency of 66 MHz, corresponding to a minimum propagation delay ( taupd) of 446 ps/stage at VDD of 3.0 V

Schottky-Barrier Height Tuning by Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In Anneal

Abstract: An experimental study on Schottky-barrier height (SBH) tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented. Measured on B-implanted NiSi and PtSi Schottky diodes, the effective SBH on n-type Si is altered to ~1.0 eV. For As- and P-implanted diodes, the SBH on p-type Si can be tuned to around 0.9 eV. The process window for the most pronounced SBH modification is dopant dependent.

Carrier Transport Mechanism in a Nanoparticle-Incorporated Organic Bistable Memory Device

Abstract: In this letter, the conduction mechanism in nanoparticle-contained polymer memory was investigated experimentally and theoretically. The current-voltage characteristics showed that the device switches from an initial low-conductivity state to a high-conductivity state upon application of an external electric field at room temperature. The current transition exhibited a very narrow voltage range that causes an abrupt increase of current. A trap-filled space-charge-limited current model was proposed and supported by the experimental data to explain the transport mechanism in organic memory.

Normally Off AlGaN/GaN Low-Density Drain HEMT (LDD-HEMT) With Enhanced Breakdown Voltage and Reduced Current Collapse

Abstract: We report a low-density drain high-electron mobility transistor (LDD-HEMT) that exhibits enhanced breakdown voltage and reduced current collapse. The LDD region is created by introducing negatively charged fluorine ions in the region between the gate and drain electrodes, effectively modifying the surface field distribution on the drain side of the HEMT without using field plate electrodes. Without changing the device physical dimensions, the breakdown voltage can be improved by 50% in LDD-HEMT, and the current collapse can be reduced. No degradation of current cutoff frequency (ft) and slight improvement in power gain cutoff frequency (fmax) are achieved in the LDD-HEMT, owing to the absence of any additional field plate electrode

A Novel 700-V SOI LDMOS With Double-Sided Trench

Abstract: A novel silicon-on-insulator (SOI) high-voltage device structure with double-sided trenches on the buried oxide layer (DT SOI) is proposed and its breakdown characteristics are investigated theoretically and experimentally in this letter. Theoretically, the charges implemented in the DTs, whose density changes with the drain voltage, increase the electric field in the buried layer and modulate the electric field in the drift region, which results in the enhancement of the breakdown voltage (BV). Experimentally, the BV of 730 V is obtained for the first time in SOI LDMOS with DT on 20-mum SOI layer and 1- mum buried oxide layer

Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

Abstract: Conventional charge pumping is demonstrated on triple-gate silicon-on-insulator FinFET gated-diode structures with varying fin widths. A simple technique is proposed and verified allowing to independently estimate fin top and sidewall interface trap density. A higher interface state density on the sidewalls is observed, which is attributed to higher fin sidewall roughness. The methodology is also demonstrated to be sensitive to fin sidewall surface crystallographic orientation. The technique presents a straightforward means of assessing the fin sidewall and topwall interface quality, which can then be directly correlated with both processing influences and reliability effects

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

Abstract: We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (Lgges0.35 mum), exhibit excellent device performance with high ION/IOFF ratio (~106), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate

A Planar Gunn Diode Operating Above 100 GHz

Abstract: We show the experimental realization of a 108-GHz planar Gunn diode structure fabricated in GaAs/AlGaAs. There is a considerable interest in such devices since they lend themselves to integration into millimeter-wave and terahertz integrated circuits. The material used was grown by molecular beam epitaxy, and devices were made using electron beam lithography. Since the frequency of oscillation is defined by the lithographically controlled anode-cathode distance, the technology shows great promise in fabricating single chip terahertz sources.

Solution-Processed TIPS-Pentacene Organic Thin-Film-Transistor Circuits

Abstract: We have fabricated solution-processed organic thin-film transistors (OTFTs) and circuits using triisopropylsilyl pentacene (TIPS-pentacene) as the active semiconductor material. Patterned bottom-gate solution-processed TIPS-pentacene OTFTs on glass substrates have mobility as large as 0.6 cm2/Vldrs and subthreshold slope as low as 0.4 V/dec. Seven-stage ring oscillators have oscillation frequency greater than 10 kHz and propagation delay of less than 8 mus per stage at a bias of 80 V. The 7- and 15-stage ring oscillators also operate with supply-voltage magnitude of less than 5 V.

Analyzing Conductance of Mixed Carbon-Nanotube Bundles for Interconnect Applications

Abstract: The carbon-nanotube (CNT) bundle is a potential candidate for deep-nanometer-interconnect applications due to its superior conductivity and current-carrying capabilities. A CNT bundle is generally a mixture of single-wall and multiwall CNTs (SWCNTs and MWCNTs) and has not been fully explored in previous studies. This letter introduces a diameter-dependent model to analyze the conductance of both SWCNTs and MWCNTs. Using this model, the conductance performance of the mixed CNT bundles is analyzed, and the estimation is consistent with the corresponding experimental result. This letter also demonstrates that the mixed CNT bundles can provide two to five times conductance improvement over copper by selecting the suitable parameters such as bundle width, tube density, and metallic tube ratio.

Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High ( $\sim$ 1.5 GPa) Channel Stress

Abstract: A flexure-based four-point mechanical wafer bending setup is used to apply large uniaxial tensile stress (up to 1.2 GPa) on industrial nMOSFETs with 0 to ~700 MPa of process-induced stress. This provides the highest uniaxial channel stress to date at ~1.5 GPa. The stress altered drain-current is measured for long and short (50-140 nm) devices and the extracted pi-coefficients are observed to be approximately constant for stresses up to ~1.5 GPa. For short devices, this trend is seen only after correcting for the significant degradation in the pi-coefficients observed due to parasitic source/drain series resistances (Rsd/)

Current–Voltage Characteristics of Long-Channel Nanobundle Thin-Film Transistors: A “Bottom-Up” Perspective

Abstract: By generalizing the classical linear response theory of "stick" percolation to nonlinear regime, we find that the drain-current of a nanobundle thin-film transistor (NB-TFT) is described under a rather general set of conditions by a universal scaling formula ID=A/LSxi(LS/LC,rho SLS 2)timesf(VG,VD ), where A is a technology-specific constant, xi is a function of geometrical factors such as stick length LS, channel length LC, and stick density rhoS, and f is a function of drain VD and gate VG biasing conditions This scaling formula implies that the measurement of the full current-voltage characteristics of a "single" NB-TFT is sufficient to predict the performance characteristics of any other transistor with arbitrary geometrical parameters and biasing conditions

Resistive Switching Mechanism in $\hbox{Zn}_{x}\hbox{Cd}_{1 - x}\hbox{S}$ Nonvolatile Memory Devices

Abstract: Nonvolatile information storage devices based on an abrupt resistance switch when an electric bias is applied are very attractive for future memory applications. Recently, such a resistance switch was described in ferroelectric ZnxCd1-xS, but the mechanism of switching remains controversial. Here, we present results that elucidate the mechanism, showing that a metal needs to be easily oxidized and is capable of diffusing into the ZnCdS film as a cation impurity forming a filamentary metallic conduction path