Showing papers in "IEEE Electron Device Letters in 2009"
TL;DR: In this article, the first-ever measured small-signal radio-frequency (RF) performance of epitaxial-graphene RF field effect transistors (FETs) was reported.
Abstract: We report dc and the first-ever measured small-signal radio-frequency (RF) performance of epitaxial-graphene RF field-effect transistors (FETs), where the epitaxial-graphene layer is formed by graphitization of 2-in-diameter Si-face semi-insulating 6H-SiC (0001) substrates. The gate is processed with a metal gate on top of a high-k Al2 O3 gate dielectric deposited via an atomic-layer-deposition method. With a gate length (Lg) of 2 mum and an extrinsic transconductance of 148 mS/mm, the extrinsic current-gain cutoff frequency (fT) is measured as 4.4 GHz, yielding an extrinsic fT ldr Lg of 8.8 GHz middot mum. This is comparable to that of Si NMOS. With graphene FETs fabricated in a layout similar to those of Si n-MOSFETs, on-state current density increases dramatically to as high as 1.18 A/mm at Vds = 1 V and 3 A/mm at Vds = 5 V. The current drive level is the highest ever observed in any semiconductor FETs.
367 citations
TL;DR: In this paper, the existence of spintronic memristor in nanoscale is demonstrated based upon spin-torque induced magnetization switching and magnetic-domain-wall motion.
Abstract: Existence of spintronic memristor in nanoscale is demonstrated based upon spin-torque-induced magnetization switching and magnetic-domain-wall motion. Our examples show that memristive effects are quite universal for spin-torque spintronic device at the time scale that explicitly involves the interactions between magnetization dynamics and electronic charge transport. We also proved that the spintronic device can be designed to explore and memorize the continuum state of current and voltage based on interactions of electron and spin transport.
365 citations
TL;DR: In this paper, the authors used the ambipolar transport properties of graphene flakes to fabricate full-wave signal rectifiers and frequency-doubling devices, and the spectral purity of the 20-kHz output signal is excellent.
Abstract: In this letter, the ambipolar transport properties of graphene flakes have been used to fabricate full-wave signal rectifiers and frequency-doubling devices. By correctly biasing an ambipolar graphene field-effect transistor in common-source configuration, a sinusoidal voltage applied to the transistor gate is rectified at the drain electrode. Using this concept, frequency multiplication of a 10-kHz input signal has been experimentally demonstrated. The spectral purity of the 20-kHz output signal is excellent, with more than 90% of the radio-frequency power in the 20-kHz frequency. This high efficiency, combined with the high electron mobility of graphene, makes graphene-based frequency multipliers a very promising option for signal generation at ultrahigh frequencies.
353 citations
TL;DR: In this paper, a rewriteable low-power operation nonvolatile physically flexible memristor device is demonstrated, which is inexpensively fabricated at room temperature by spinning a TiO2 sol gel on a commercially available polymer sheet.
Abstract: A rewriteable low-power operation nonvolatile physically flexible memristor device is demonstrated. The active component of the device is inexpensively fabricated at room temperature by spinning a TiO2 sol gel on a commercially available polymer sheet. The device exhibits memory behavior consistent with a memristor, demonstrates an on/off ratio greater than 10 000 : 1, is nonvolatile for over 1.2 times 106 s, requires less than 10 V, and is still operational after being physically flexed more than 4000 times.
251 citations
TL;DR: Pentacene organic thin-film transistors (OTFTs) with a high-kappa HfLaO dielectric were integrated onto flexible polyimide substrates as discussed by the authors.
Abstract: Pentacene organic thin-film transistors (OTFTs) with a high-kappa HfLaO dielectric were integrated onto flexible polyimide substrates. The pentacene OTFTs exhibited good performance, such as a low subthreshold swing of 0.13 V/decade and a threshold voltage of -1.25 V. The field-effect mobility was 0.13 cm2/Vmiddots at an operating voltage as low as only 2.5 V. These characteristics are attractive for high-switching-speed and low-power applications.
229 citations
TL;DR: In this article, a new type of graphene-based transistor was proposed to allow lower voltage, lower power operation than possible with complementary metal-oxide-semiconductor (CMOS) field effect transistors.
Abstract: We propose a new type of graphene-based transistor intended to allow lower voltage, lower power operation than possible with complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Increased energy efficiency is not only important for its own sake, but is also necessary to allow continued device scaling and the resulting increase in computational power in CMOS-like logic circuits. We describe the basic device structure and physics and predicted current-voltage characteristics. Advantages over CMOS in terms of lower voltage and power are discussed.
211 citations
TL;DR: In this article, the authors achieved a 9?m-thick AlGaN/GaN high-electron mobility transistor (HEMT) epilayer on silicon using thick buffer layers with reduced dislocation density (DD).
Abstract: We have achieved a 9 ?m-thick AlGaN/GaN high-electron mobility transistor (HEMT) epilayer on silicon using thick buffer layers with reduced dislocation density (DD). The crack-free 9 ?m-thick epilayer included 2 ?m i-GaN and 7 ?m buffer. The HEMTs fabricated on these devices showed a maximum drain-current density of 625 mA/mm, transconductance of 190 mS/mm, and a high three-terminal OFF breakdown of 403 V for device dimensions of LgWgLgd=1.5/15/3 ?m . Without using a gate field plate, this is the highest BV reported on an AlGaN/GaN HEMT on silicon for a short Lgd of 3 ?m. A very high BV of 1813 V across 10 ?m ohmic gap was achieved for i-GaN grown on thick buffers. As the thickness of buffer layers increased, the decreased DD of GaN and increased resistance between surface electrode and substrate yielded a high breakdown.
203 citations
TL;DR: In this paper, the resistive switching properties of a ZrO2-based memory film with implanted Ti ions are investigated, and the results demonstrate that doping Ti in Zr O2 can remove the electroforming process and reduce the variations of switching parameters such as set voltage and resistance in off state.
Abstract: In this letter, the resistive switching properties of a ZrO2-based memory film with implanted Ti ions are investigated. The testing results demonstrate that doping Ti in ZrO2 can remove the electroforming process and reduce the variations of switching parameters such as set voltage and resistance in off state. Furthermore, the Ti-doped ZrO2 resistive switching memory also exhibits high device yield (nearly 100%), low operating voltage, fast speed, large on/off ratio (>104), and long retention time (>107 s). The formation and rupture of conducting filaments are suggested to be responsible for the resistive switching phenomenon. The doped Ti impurities can improve the formation of conducting filaments and switching behaviors.
199 citations
TL;DR: In this paper, the average resistivity at a given linewidth (18 nm < W < 52 nm) is about three times that of a Cu wire, whereas the best GNR has a resistivity that is comparable to that of Cu.
Abstract: Graphene nanoribbon (GNR) interconnects are fabricated, and the extracted resistivity is compared to that of Cu. It is found that the average resistivity at a given linewidth(18 nm < W< 52 nm) is about three times that of a Cu wire, whereas the best GNR has a resistivity that is comparable to that of Cu. The conductivity is found to be limited by impurity scattering as well as line-edge roughness scattering; as a result, the best reported GNR resistivity is three times the limit imposed by substrate phonon scattering. This letter reveals that even moderate-quality graphene nanowires have the potential to outperform Cu for use as on-chip interconnects.
199 citations
TL;DR: In this article, the transient response of double-gate thin-body-silicon interband tunnel field-effect transistor (TFET) with its metal-oxide-semiconductor field effect transistor counterpart was compared.
Abstract: We compare the transient response of double-gate thin-body-silicon interband tunnel field-effect transistor (TFET) with its metal-oxide-semiconductor field-effect transistor counterpart. Due to the presence of source side tunneling barrier, the silicon TFETs exhibit enhanced Miller capacitance, resulting in large voltage overshoot/undershoot in its large-signal switching characteristics. This adversely impacts the performance of Si TFETs for digital logic applications. It is shown that TFETs based on lower bandgap and lower density of states materials like indium arsenide show significant improvement in switching behavior due to its lower capacitance and higher ON current at reduced voltages.
198 citations
TL;DR: In this paper, a unified model was proposed to elucidate the resistive switching behavior of metal-oxide-based resistive random access memory devices using the concept of electron hopping transport along filamentary conducting paths in dielectric layer.
Abstract: A unified model is proposed to elucidate the resistive switching behavior of metal-oxide-based resistive random access memory devices using the concept of electron hopping transport along filamentary conducting paths in dielectric layer. The transport calculation shows that a low-electron-occupied region along the conductive filament (CF) is formed when a critical electric field is applied. The oxygen vacancies in this region are recombined with oxygen ions, resulting in rupture of the CFs. The proposed mechanism was verified by experiments and theoretical calculations. In this physical model, the observed resistive switching behaviors in the oxide-based systems can be quantified and predicted.
TL;DR: In this paper, a suite of realistically extended InAs p-i-n single gate (SG) and dual-gate (DG) ultrathin-body (UTB) and gate-all-around nanowire (GAA NW) devices with a gate length of 20 nm were analyzed.
Abstract: Band-to-band tunneling field-effect transistors (BTBT FETs) are expected to exhibit a subthreshold swing (SS) better than the 60-mV/dec limit of conventional metal-oxide-semiconductor FETs at room temperature. Through atomistic modeling of a suite of realistically extended InAs p-i-n single-gate (SG) and dual-gate (DG) ultrathin-body (UTB) and gate-all-around nanowire (GAA NW) devices with a gate length of 20 nm, we demonstrate that such a reduced SS can only be achieved if the electrostatic potential under the gate contact is very well controlled. We find that GAA NWs keep an SS less than 60 mV/dec for diameters larger than 10 nm, while the bodies in DG and SG UTBs must be scaled down to 7 and 4 nm, respectively. Still, all the considered devices are characterized by an on current smaller than the ITRS requirements.
TL;DR: In this article, a single-chip switch-mode boost converter that features a monolithically integrated lateral field effect rectifier (L-FER) and a normally off transistor switch was demonstrated.
Abstract: We demonstrate a single-chip switch-mode boost converter that features a monolithically integrated lateral field-effect rectifier (L-FER) and a normally off transistor switch. The circuit was fabricated on a standard AlGaN/GaN HEMT epitaxial wafer grown with GaN-on-Si technology. The fabricated rectifier with a drift length of 15 mum exhibits a breakdown voltage of 470 V, a turn-on voltage of 0.58 V, and a specific on-resistance of 2.04 mOmegaldrcm2. The L-FER exhibits no reverse recovery current associated with the turn-off transient because of its unipolar nature. A prototype of GaN-based boost converter that includes monolithically integrated rectifiers and transistors is demonstrated using conventional GaN-on-Si wafers for the first time to prove the feasibility of the GaN-based power IC technology.
TL;DR: In this article, the authors reported the temperature dependence of the intrinsic thermal conductivity and interface resistances of 56-200-Aring-thick HfO2 films.
Abstract: Thin-film HfO2 is a promising gate dielectric material that will influence thermal conduction in modern transistors. This letter reports the temperature dependence of the intrinsic thermal conductivity and interface resistances of 56-200-Aring-thick HfO2 films. A picosecond pump-probe thermoreflectance technique yields room-temperature intrinsic thermal conductivity values between 0.49 and 0.95 W/(mmiddotK). The intrinsic thermal conductivity and interface resistance depend strongly on the film-thickness-dependent microstructure.
TL;DR: In this paper, a vertical silicon-nanowire (SiNW)-based tunneling field effect transistor (TFET) using CMOS-compatible technology was demonstrated, and the obtained 53 muA/mum I on can be further enhanced with heterostructures at the tunneling interface.
Abstract: This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p+-i- n+ tunneling junction, the TFET with a gate length of ~ 200 nm exhibits good subthreshold swing of ~ 70 mV/dec, superior drain-induced-barrier-lowering of ~ 17 mV/V, and excellent I on - I off ratio of ~ 107 with a low I off ( ~ 7npA/mum). The obtained 53 muA/mum I on can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.
TL;DR: In this article, the bilayer graphene tunnel field effect transistor (TFET) was proposed for fabrication and circuit integration with present-day technology, and it provided high I on/I off ratio at ultralow supply voltage without the limitations in terms of prohibitive lithography and patterning requirements for circuit integration of graphene nanoribbons.
Abstract: In this letter, we propose the bilayer graphene tunnel field-effect transistor (TFET) as a device suitable for fabrication and circuit integration with present-day technology. It provides high I on/I off ratio at ultralow supply voltage, without the limitations in terms of prohibitive lithography and patterning requirements for circuit integration of graphene nanoribbons. Our investigation is based on the solution of the coupled Poisson and Schrodinger equations in three dimensions, within the non-equilibrium Green's function formalism on a tight binding Hamiltonian. We show that the small achievable gap of only few hundreds of millielectronvolts is still enough for promising TFET operation, providing a large I on/I off ratio in excess of 103 even for a supply voltage of only 0.1 V. A key to this performance is the low quantum capacitance of bilayer graphene, which permits to obtain an extremely small subthreshold swing S smaller than 20 mV/dec at room temperature.
TL;DR: In this paper, the authors proposed that the tail distribution will be diminished and separated from the main distribution as the cell size shrinks into a true nanoscale, and that the retention time is eventually to be determined by the main distributions only.
Abstract: Data retention time for ultimate DRAMs with an extremely scaled-down cell size has been investigated. The entire memory cells can be discretely categorized by two groups: leaky cells or normal cells, and the main distribution representing the normal cells shows longer than 40 s of the mean retention time. The leaky cells are mainly originated by trap-assisted gate-induced drain leakage currents depending on trap energy dispersion. Through analyses of full chip retention failure curves and interface trap density ( Dit*) measurements, we propose that the tail distribution will be diminished and separated from the main distribution as the cell size shrinks into a true nanoscale. As a result, the retention time is eventually to be determined by the main distribution function only.
TL;DR: For a variety of solar cells, the authors showed that the single exponential J-V model parameters, namely ideality factor eta, parasitic series resistance R s, parasitic shunt resistance R sh, dark current J 0, and photogenerated current J ph can be extracted simultaneously from just four simple measurements of the bias points corresponding to V oc, 0.6V Oc, J sc, and ε 2.6J sc, using closed-form expressions.
Abstract: For a variety of solar cells, it is shown that the single exponential J-V model parameters, namely - ideality factor eta, parasitic series resistance R s, parasitic shunt resistance R sh, dark current J 0, and photogenerated current J ph can be extracted simultaneously from just four simple measurements of the bias points corresponding to V oc, ~ 0.6V oc, J sc, and ~ 0.6J sc on the illuminated J-V curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any dJ/dV (i.e., slope). The method is based on the power law J-V model proposed recently by us.
TL;DR: In this article, the authors simulated heat propagation in silicon-on-insulator (SOI) circuits with and without graphene lateral heat spreaders using finite element method and obtained numerical solutions of the heat propagation equations using the finite-element method.
Abstract: Graphene was recently proposed as a material for heat removal owing to its extremely high thermal conductivity. We simulated heat propagation in silicon-on-insulator (SOI) circuits with and without graphene lateral heat spreaders. Numerical solutions of the heat-propagation equations were obtained using the finite-element method. The analysis was focused on the prototype SOI circuits with the metal-oxide-semiconductor field-effect transistors. It was found that the incorporation of graphene or few-layer graphene (FLG) layers with proper heat sinks can substantially lower the temperature of the localized hot spots. The maximum temperature in the transistor channels was studied as function of graphene's thermal conductivity and the thickness of FLG. The developed model and obtained results are important for the design of graphene heat spreaders and interconnects.
TL;DR: In this article, the authors present results of the experimental investigation of the low-frequency noise in bilayer graphene transistors, where the back-gated devices were fabricated using the electron beam lithography and evaporation and the charge neutrality point for the transistors was around +10 V.
Abstract: We present results of the experimental investigation of the low-frequency noise in bilayer graphene transistors. The back-gated devices were fabricated using the electron beam lithography and evaporation. The charge neutrality point for the transistors was around +10 V. The noise spectra at frequencies f > 10-100 Hz were of the 1/f type with the spectral density on the order of S1 ~ 10-23-10-22 A2/Hz at the frequency of 1 kHz. The deviation from the 1/f spectrum at f < 10-100 Hz suggests that the noise is of the carrier-number fluctuation origin due to the carrier trapping by defects. The Hooge parameter was determined to be as low as ~ 10-4. The gate dependence of the normalized noise spectral density indicates that it is dominated by the contributions from the ungated parts of the device and can be reduced even further. The obtained results are important for graphene electronic and sensor applications.
TL;DR: In this article, the properties and integration of these graphene-on-insulator transistors are presented and compared to the characteristics of devices made from graphitized SiC and exfoliated graphene flakes.
Abstract: Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO2 substrate. The properties and integration of these graphene-on-insulator transistors are presented and compared to the characteristics of devices made from graphitized SiC and exfoliated graphene flakes.
TL;DR: In this paper, a simple top-down method for realizing an array of vertically stacked nanowires is presented, which utilizes the nonuniformity in inductively coupled plasma (ICP) etching to form a scallop pattern at the sidewall of a tall silicon ridge.
Abstract: A simple top-down method for realizing an array of vertically stacked nanowires is presented. The process utilizes the nonuniformity in inductively coupled plasma (ICP) etching to form a scallop pattern at the sidewall of a tall silicon ridge that is further trimmed to form stacked nanowires by stress-limited oxidation. The process has been demonstrated to be controllable and repeatable, starting with bulk silicon wafers. Vertically stacked gate-all-around MOSFETs have been fabricated, which show excellent performance with a nearly ideal subthreshold slope of 62 mV/dec, a low leakage current, and a high I on/I off ratio of ~ 108.
TL;DR: TaN-pure-GeTe-Cu bipolar switching devices which can be adaptable to semiconductor processes were fabricated as a function of top-electrode sizes (0.2, 0.4, 10, and 50 mum).
Abstract: TaN-pure-GeTe-Cu bipolar switching devices which can be adaptable to semiconductor processes were fabricated as a function of top-electrode sizes (0.2, 0.4, 10, and 50 mum). The on/off resistance change ratio increased highly with decreasing electrode size. In particular, the on/off resistance change ratio was about 103 when the electrode size was scaled down to 200 nm. We obtained the characteristics of conductive bridging memory cell using pure-GeTe film without any doping of Cu or Ag; we also determined the reason for the enhancement of the on/off resistance change ratio when scaling down the electrode size.
TL;DR: An anomalous kink effect has been observed in the room-temperature drain current ID versus drain voltage V DS characteristics of GaN high electron mobility transistors as mentioned in this paper, characterized by extremely long negative charge buildup times and by a nonmonotonic behavior as a function of photon energy under illumination.
Abstract: An anomalous kink effect has been observed in the room-temperature drain current ID versus drain voltage V DS characteristics of GaN high electron mobility transistors. The kink is originated by a buildup (at low V DS) and subsequent release (at high V DS) of negative charge, resulting in a shift of pinch-off voltage VP toward more negative voltages and in a sudden increase in ID. The kink is characterized by extremely long negative charge buildup times and by a nonmonotonic behavior as a function of photon energy under illumination. The presence of traps in the GaN buffer may explain both spectrally resolved photostimulation data and the slow negative charge buildup.
TL;DR: In this paper, the effect of strain on tunneling field effect transistor (TFET) characteristics was investigated and it was found that tensile strain increases drain current, whereas compressive strain reduces the drain current.
Abstract: We report the first study of the effect of strain on tunneling field-effect transistor (TFET) characteristics. Double-gate silicon TFETs were employed. It was found that tensile strain increases the drain current, whereas compressive strain reduces the drain current. This is attributed to strain-induced band splitting and carrier repopulation and provides guidelines on strain engineering of TFETs. An elaborate study of the dependence of the electrical characteristics of TFET on temperature is also reported. It was observed that on-state tunneling current exhibits a positive temperature dependence at low drain bias condition (V DS = 1 V), whereas opposite behavior was observed when V DS = 1.5 V. When the device temperature is increased, enhancement of the drain current at V DS = 1 V results from band gap narrowing, whereas reduction in the drain current at V DS = 1.5 V is attributed to the decrease in the electric field at the tunneling junction.
IBM1
TL;DR: In this paper, the integration of rare-earth silicides, known to feature the lowest Schottky barriers (SBs) to electrons, coupled with a dopant segregation based on arsenic (As+) implantation was studied.
Abstract: As an attempt to considerably reduce the equivalent contact resistivity of Schottky junctions, this letter studies the integration of rare-earth silicides, known to feature the lowest Schottky barriers (SBs) to electrons, coupled with a dopant segregation based on arsenic (As+) implantation. Both erbium (Er) and ytterbium (Yb) have been considered in the implant-before-silicide (IBS) and implant-to-silicide flavors. It is shown that the two schemes coupled with a limited thermal budget (500degC) produce an SB below the target of 0.1 eV. The implementation of IBS arsenic-segregated YbSi1.8 junctions in an n-type SB-MOSFET is demonstrated for the first time resulting in a current-drive improvement of more than one decade over the dopant-free counterpart.
TL;DR: In this article, an external compensation method that senses and compensates variations of threshold voltage and mobility of TFTs and degradation of organic light-emitting-diode (OLED) device is proposed.
Abstract: The variation of electrical characteristics of polycrystalline-silicon thin-film transistor (TFT) and degradation of organic light-emitting-diode (OLED) device cause nonuniform intensity of luminance and image sticking in active-matrix OLED (AMOLED) displays. An external compensation method that senses and compensates variations of threshold voltage and mobility of TFTs and degradation of OLED device is proposed. The effect of the external compensation method on AMOLED pixel is experimentally verified by measuring the luminance of OLEDs and the electrical characteristics of TFTs in AMOLED pixels.
TL;DR: In this article, the first on-wafer integration of Si(100) MOSFETs and AlGaN/GaN high electron mobility transistors (HEMTs) is demonstrated.
Abstract: The first on-wafer integration of Si(100) MOSFETs and AlGaN/GaN high electron mobility transistors (HEMTs) is demonstrated. To enable a fully Si-compatible process, we fabricated a novel Si(100)-GaN-Si(100) virtual substrate through a wafer bonding and etch-back technique. The high thermal stability of nitride semiconductors allowed the fabrication of Si MOSFETs on this substrate without degrading the performance of the GaN epilayers. After the Si devices were fabricated, the nitride epilayer is exposed, and the nitride transistors are processed. By using this technology, GaN and Si devices separated by less than 5 mum from each other have been fabricated, which is suitable for building future heterogeneous integrated circuits.
IBM1
TL;DR: In this article, both short and long buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated.
Abstract: Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.
TL;DR: In this article, the authors explore the device potential of a tunable-gap bilayer graphene (BG) FET exploiting the possibility of opening a bandgap in BG by applying a vertical electric field via independent gate operation.
Abstract: We explore the device potential of a tunable-gap bilayer graphene (BG) FET exploiting the possibility of opening a bandgap in BG by applying a vertical electric field via independent gate operation. We evaluate device behavior using atomistic simulations based on the self-consistent solution of the Poisson and Schrodinger equations within the nonequilibrium Green's function formalism. We show that the concept works, but the bandgap opening is not strong enough to suppress band-to-band tunneling in order to obtain a sufficiently large Ion/Ioff ratio for CMOS device operation.