Showing papers in "IEEE Electron Device Letters in 2010"
TL;DR: In this article, the authors present details of high-performance enhancement-mode GaN MIS high-electron-mobility transistor (MIS-HEMT) devices.
Abstract: This letter presents details of high-performance enhancement-mode GaN MIS high-electron-mobility transistor (MIS-HEMT) devices. Devices with an n-GaN/i-AlN/n-GaN triple cap layer, a recessed-gate structure, and high- k gate dielectrics show high drain current and complete enhancement-mode operation. The maximum drain current and threshold voltage (V th) are 800 mA/mm and +3 V, respectively. These results indicate that a recessed AlGaN/GaN MIS-HEMT with the triple cap could be a promising new technology for future device applications.
275 citations
TL;DR: In this paper, a gate-recessed AlGaN/GaN high-electron mobility transistor (HEMT) with a SiC substrate with a record power-gain cutoff frequency (fmax) was reported.
Abstract: We report on a gate-recessed AlGaN/GaN high-electron mobility transistor (HEMT) on a SiC substrate with a record power-gain cutoff frequency (fmax). To achieve this high fmax, we combined a low-damage gate-recess technology, scaled device geometry, and recessed source/drain ohmic contacts to simultaneously enable minimum short-channel effects (i.e., high output resistance Rds) and very low parasitic resistances. A 60-nm-gate-length HEMT with recessed AlGaN barrier exhibited excellent Rds of 95.7 ?·mm, Ron of 1.1 ~ 1.2 ? · mm, and fmax of 300 GHz, with a breakdown voltage of ~ 20 V. To the authors' knowledge, the obtained fmax is the highest reported to date for any nitride transistor. The accuracy of the fmax value is verified by small signal modeling based on carefully extracted S-parameters.
275 citations
TL;DR: In this article, a new technique for fabricating 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) with high inversion channel mobility was proposed.
Abstract: We propose a new technique for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO2/4H-SiC (0001) interface by postoxidation annealing using phosphoryl chloride (POCl3). The interface state density near the conduction band edge of 4H-SiC was reduced significantly, and the peak field-effect mobility of lateral 4H-SiC MOSFETs on (0001) Si face was improved to 89 cm2/V · s by POCl3 annealing at 1000°C.
274 citations
TL;DR: In this article, the authors demonstrate the use of the ambipolar-transport properties of graphene for the fabrication of a new kind of RF mixer device, which can effectively suppress odd-order intermodulations and lead to lower spurious emissions in the circuit.
Abstract: The combination of the unique properties of graphene with new device concepts and nanotechnology can overcome some of the main limitations of traditional electronics in terms of maximum frequency, linearity, and power dissipation. In this letter, we demonstrate the use of the ambipolar-transport properties of graphene for the fabrication of a new kind of RF mixer device. Due to the symmetrical ambipolar conduction in graphene, graphene-based mixers can effectively suppress odd-order intermodulations and lead to lower spurious emissions in the circuit. The mixer operation was demonstrated at a frequency of 10 MHz using graphene grown by chemical vapor deposition on a Ni film and then transferred to an insulating substrate. The maximum operating frequency was limited by the device geometry and the measurement setup, and a high-quality factor was observed with a third-order intercept point of +13.8 dBm.
253 citations
TL;DR: In this paper, a high performance oxide thin-film transistor (TFT) with an amorphous indium gallium zinc oxide (a-IGZO) channel and ZrO2 gate dielectrics was investigated.
Abstract: We have investigated the high-performance oxide thin-film transistor (TFT) with an amorphous indium gallium zinc oxide (a-IGZO) channel and ZrO2 gate dielectrics. The a-IGZO TFT is fully fabricated at room temperature without any thermal treatments. ZrO2 is one of the most promising high-k materials. The a-IGZO TFT (channel W/L = 240/30 ?m) with ZrO2 shows high performance such as high on current of 2.11 mA and high field effect mobility of 28 cm2/(V·s) at the gate voltage 10 V. The threshold voltage and the subthreshold swing are 3.2 V and 0.56 V/decade, respectively. Note that the high-performance a-IGZO TFT is higher than ever shown in previous researches.
240 citations
TL;DR: In this article, the impact of band lineup and source doping concentration on the performance of heterojunction tunnel FETs with type-II heterointerface was investigated by simulations.
Abstract: The impact of band lineup and source doping concentration on the performance of heterojunction tunnel FETs (H-TFETs) with type-II heterointerface is investigated by simulations. Exemplarily, H-TFETs based on InAs/AlxGa1-xSb heterostructures are studied. Varying the Al content x, the band lineup can be adjusted from staggered to broken. We find that a staggered band lineup and a medium source doping concentration yield the best ON/OFF-state performance in terms of an inverse subthreshold slope that is smaller than 60 mV/dec and fT values in the terahertz range.
223 citations
TL;DR: In this article, the authors present a new technology to increase the breakdown voltage of AlGaN/GaN high-electron-mobility transistors (HEMTs) grown on Si substrates.
Abstract: In this letter, we present a new technology to increase the breakdown voltage of AlGaN/GaN high-electron-mobility transistors (HEMTs) grown on Si substrates. This new technology is based on the removal of the original Si substrate and subsequent transfer of the AlGaN/GaN HEMT structure to an insulating carrier wafer (e.g., glass or polycrystalline AlN). By applying this new technology to standard AlGaN/GaN HEMTs grown on Si substrate, an AlGaN/GaN HEMT with breakdown voltage above 1500 V and specific on resistance of 5.3 mΩ·cm2 has been achieved.
204 citations
TL;DR: In this paper, a numerical simulation study of gate capacitance components in a tunneling field effect transistor (TFET) was performed, showing key differences in the partitioning of gate capacitor between the source and drain as compared with a MOSFET.
Abstract: We report a numerical simulation study of gate capacitance components in a tunneling field-effect transistor (TFET), showing key differences in the partitioning of gate capacitance between the source and drain as compared with a MOSFET. A compact model for TFET capacitance components, including parasitic and inversion capacitances, was built and calibrated with computer-aided design data. This model should be useful for further investigation of performance of circuits containing TFETs. The dependence of gate-drain capacitance Cgd on drain design and gate length was further investigated for reduction of switching delay in TFETs.
201 citations
TL;DR: In this paper, the experimental temperature-dependent characteristics of vertical In0.53Ga0.47As tunnel field effect transistors (TFETs) at low drain bias to provide key insight into its device operation and design.
Abstract: We report on the experimental temperature-dependent characteristics of vertical In0.53Ga0.47As tunnel field-effect transistors (TFETs) at low drain bias to provide key insight into its device operation and design. Leakage floor (IOFF) is determined by the ungated p+-i-n+ reverse bias leakage and is dominated by Shockley-Read-Hall generation-recombination current. The temperature dependence of subthreshold slope arises from tunneling into mid-gap states at the oxide-semiconductor interface, followed by thermal emission into the conduction band. At intermediate gate voltages, pure band-to-band tunneling dominates, while at higher gate voltages, current transport is diffusion limited. The temperature-dependent study of In0.53Ga0.47As TFET highlights the importance of passivating the III-V and dielectric interface.
198 citations
TL;DR: In this article, a lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-on-insulator was proposed, which utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body.
Abstract: We present a new lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-on-insulator. The device utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body. We demonstrate that the proposed device provides a low and constant reverse leakage-current density of about 1 fA/μm with ON/OFF current ratios of around 107 at 1-V forward bias and room temperature. In the forward mode, a current swing of 88 mV/dec is obtained, which is reduced to 68 mV/dec by back-gate biasing.
197 citations
TL;DR: In this paper, a phenomenological model was proposed to provide a unified explanation for both the unipolar and bipolar resistive switching mechanisms of metal oxide RRAMs, which combines the previous thermal dissolution model and ion migration model and thus can explain many experimental observations such as the electrode material-dependent switching polarity and the voltage-time dilemma between fast switching and long retention.
Abstract: The reset mechanism of metal oxide RRAM has been attributed to oxygen ion migration assisted by Joule heating. Here, we present a phenomenological model to provide a unified explanation for both the unipolar and bipolar resistive switching mechanisms. Numerical simulation results reveal that the switching mode is determined by the electrode/oxide interface property. Without/with an interfacial barrier, unipolar/bipolar switching behavior is obtained. This model combines the previous thermal dissolution model and ion migration model and thus can explain many experimental observations such as the electrode-material-dependent switching polarity and the voltage-time dilemma between fast switching and long retention.
TL;DR: In this article, a normally off GaN MOSFET was proposed by utilizing an extremely high 2D electron-gas density at an AlGaN/GaN heterostructure as source and drain, which can be obtained by controlling the tensile stress accompanied with the growth of GaN on silicon substrate.
Abstract: A normally off GaN MOSFET was proposed by utilizing an extremely high 2-D electron-gas density (> 1014 / cm2) at an AlGaN/GaN heterostructure as source and drain, which can be obtained by controlling the tensile stress accompanied with the growth of GaN on silicon substrate. The fabricated MOSFET with an Al2O3 gate insulator exhibited excellent device performance, such as a threshold voltage of 2 V, drain current of 353 mA/mm, extrinsic transconductance of 98 mS/mm, and field-effect mobility of 225 cm2/V·s.
TL;DR: In this paper, the memory performance of hafnium oxide (HfOx)-based resistive memory containing a thin reactive Ti buffer layer can be greatly improved due to the excellent ability of Ti to absorb oxygen atoms from the HfOx film after post-metal annealing.
Abstract: The memory performance of hafnium oxide (HfOx)-based resistive memory containing a thin reactive Ti buffer layer can be greatly improved. Due to the excellent ability of Ti to absorb oxygen atoms from the HfOx film after post-metal annealing, a large amount of oxygen vacancies are left in the HfOx layer of the TiN/Ti/HfOx/TiN stacked layer. These oxygen vacancies are crucial to make a memory device with a stable bipolar resistive switching behavior. Aside from the benefits of low operation power and large on/off ratio (>100), this memory also exhibits reliable switching endurance (>106 cycles), robust resistance states (200°C), high device yield (~100%), and fast switching speed (<10 ns).
TL;DR: In this paper, a physics-based analytical model for the currentvoltage characteristics corresponding to the low and high resistive states in electroformed metal-insulator-metal structures with HfO2 layers is proposed.
Abstract: A physics-based analytical model for the current-voltage (I-V) characteristics corresponding to the low and high resistive states in electroformed metal-insulator-metal structures with HfO2 layers is proposed. The model relies on the Landauer theory for the electron transport in mesoscopic systems. The switching phenomenon is ascribed to the modulation of the constriction's bottleneck cross-sectional area associated with atomic rearrangements within the confinement path. The extracted parameter values allow one to conclude that the length and radius of the region that controls the conduction characteristics are in the nanometer range.
TL;DR: In this paper, the impact of edge scattering on carrier transport in GNRs has been investigated, and it is shown that carrier mobility is limited by edge scattering in patterned GNRs, where the ribbon width is less than 20 nm.
Abstract: Graphene has shown impressive properties for nanoelectronics applications, including a high mobility and a widthdependent bandgap. Use of graphene in nanoelectronics would most likely be in the form of graphene nanoribbons (GNRs) where the ribbon width is expected to be less than 20 nm. Many theoretical projections have been made on the impact of edge scattering on carrier transport in GNRs-most studies point to a degradation of mobility (of GNRs) as well as the on/off ratio (of GNR FETs). This letter provides the first clear experimental evidence of the onset of size effect in patterned GNRs; it is shown that, for W < 60 nm, carrier mobility in GNRs is limited by edge scattering.
TL;DR: In this article, a thermal boundary resistance (TBR) is associated with the presence of an AlN nucleation layer (NL) in AlGaN/GaN high-electron-mobility transistors (HEMTs) grown on SiC substrates.
Abstract: A thermal boundary resistance (TBR) is associated with the presence of an AlN nucleation layer (NL) in AlGaN/GaN high-electron-mobility transistors (HEMTs) grown on SiC substrates, raising device temperature beyond what is expected from the simple thermal conductivities of the main device layers. TBR was found to differ by up to a factor of four between different device suppliers, all using standard metal-organic chemical vapor deposition (MOCVD) growth techniques, related to the detailed NL microstructure. Optimizing the NL crystalline structure in MOCVD could therefore significantly improve heat extraction from AlGaN/GaN HEMTs into the SiC substrate, potentially reducing peak channel temperature rise by up to 40%, significantly benefiting device reliability.
TL;DR: In this article, the effect of the gate dielectric material on the light-induced bias-temperature instability of an In-Ga-Zn-O (IGZO) thin-film transistor (TFT) was examined.
Abstract: This letter examines the effect of the gate dielectric material on the light-induced bias-temperature instability of an In-Ga-Zn-O (IGZO) thin-film transistor (TFT) After applying positive and negative bias stresses, the SiNx-gated TFT exhibited inferior stability to the SiO2-gated TFT, which was explained by the charge trapping mechanism However, light illumination under a negative bias stress accelerated the negative displacement of the threshold voltage (Vth) of the SiNx-gated IGZO TFT compared to that of the SiO2-gated TFT This was attributed to the injection of photocreated hole carriers into the underlying gate dielectric bulk region as well as the hole trapping at the gate/channel interface
TL;DR: In this article, a resistive switching memory device based on graphene oxide (GO) was presented, which showed good switching performance with an on/off resistance ratio of 103, low set/reset voltage, and excellent data retention.
Abstract: A resistive switching memory device based on graphene oxide (GO) is presented. It is found that the resistive switching characteristic has a strong dependence on electrode material and GO thickness. In our experiment, an Al/GO/ITO structure with 30-nm-thick GO shows good switching performance with an on/off resistance ratio of 103, low set/reset voltage, and excellent data retention. The GO memory is also fabricated on a flexible substrate with no degradation in switching property, even when the substrate is bent down to 4-mm radius, indicating that the GO memory is an excellent candidate to be a memory device for future flexible electronics.
TL;DR: In this article, the authors present state-of-the-art performance of top-gated graphene n-and p-FETs fabricated with epitaxial graphene layers on Si-face 6H-SiC substrates on 50mm wafers.
Abstract: In this letter, we present state-of-the-art performance of top-gated graphene n-FETs and p-FETs fabricated with epitaxial graphene layers grown on Si-face 6H-SiC substrates on 50-mm wafers. The current-voltage characteristics of these devices show excellent saturation with on-state current densities (Ion) of 0.59 A/mm at Vds = 1 V and 1.65 A/mm at Vds = 3 V. Ion/Ioff ratios of 12 and 19 were measured at Vds = 1 and 0.5 V, respectively. A peak extrinsic gm as high as 600 mS/mm was measured at Vds = 3.05 V, with a gate length of 2.94 ?m. The field-effect mobility versus effective electric field (Eeff) was measured for the first time in epitaxial graphene FETs, where record field-effect mobilities of 6000 cm2/V·s for electrons and 3200 cm2/V·s for holes were obtained at Eeff ~ 0.27 MV/cm .
IBM1
TL;DR: In this paper, experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length.
Abstract: Experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short-channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length. Data from undoped-body single-gate extremely thin SOI (ETSOI) devices additionally show that the universality of short-channel effects is valid for any undoped-body fully depleted SOI MOSFET. Our data indicate that LEFF of undoped GAA NW MOSFETs can be scaled down by ~2.5 times compared with undoped single-gate ETSOI MOSFETs while maintaining equivalent short-channel control.
TL;DR: In this paper, ultrathin (7 nm) atomic layer deposited Al2O3 layers and highdeposition-rate plasma-enhanced chemical vapor deposited AlOx layers have been applied and characterized as rear-surface passivation for high-efficiency silicon solar cells.
Abstract: Ultrathin (7 nm) atomic layer deposited Al2O3 layers and high-deposition-rate plasma-enhanced chemical vapor deposited AlOx layers have been applied and characterized as rear-surface passivation for high-efficiency silicon solar cells. The excellent efficiency values (up to 21.3%-21.5%) demonstrate that both aluminum oxide deposition processes have a very high potential comparable to the reference cells with SiO2 passivation. The high voltages ( 680 mV), the excellent long-wavelength quantum efficiency, and the high short-circuit currents of these cells (~40 mA/ cm2) are a proof for the low rear-surface recombination velocity and excellent internal rear-surface reflection.
TL;DR: In this article, the authors reported 55-nm gate AlInN/GaN high-electron-mobility transistors (HEMTs) featuring a short-circuit current gain cutoff frequency of fT = 205 GHz at room temperature, a new record for GaN-based HEMTs.
Abstract: We report 55-nm gate AlInN/GaN high-electron-mobility transistors (HEMTs) featuring a short-circuit current gain cutoff frequency of fT = 205 GHz at room temperature, a new record for GaN-based HEMTs. The devices source a maximum current density of 2.3 A/mm at VGS = 0 V and show a measured transconductance of 575 mS/mm, which is the highest value reported to date for nonrecessed gate nitride HEMTs. Comparison to state-of-the-art thin-barrier AlGaN/GaN HEMTs suggests that AlInN/GaN devices benefit from an advantageous channel velocity under high-field transport conditions.
TL;DR: In this paper, the reliable resistive switching properties of Au/ZrO2/Ag structure fabricated with full room temperature process are demonstrated and the tested devices show low operation voltages (< 1 V, high resistance ratio (about 104), fast switching speed (50 ns), and reliable data retention (ten years extrapolation at both RT and 85 °C).
Abstract: The reliable resistive switching properties of Au/ZrO2/ Ag structure fabricated with full room temperature process are demonstrated in this letter. The tested devices show low operation voltages (< 1 V), high resistance ratio (about 104), fast switching speed (50 ns), and reliable data retention (ten years extrapolation at both RT and 85 °C). Moreover, the benefits of high yield and multilevel storage possibility make them promising in the next generation nonvolatile memory applications.
TL;DR: In this paper, the performance of a tunnel field effect transistor (TFET) with a raised germanium (Ge) source region is investigated via 2D device simulation with a tunneling model calibrated to experimental data.
Abstract: The performance of a tunnel field effect transistor (TFET) with a raised germanium (Ge) source region is investigated via 2-D device simulation with a tunneling model calibrated to experimental data. The comparison of various Ge-source TFET designs shows that a fully elevated Ge-source design provides for the steepest subthreshold swing and, therefore, the largest on-state drive current for low-voltage operation. Mixed-mode (dc and ac) simulations are used to assess the energy-delay performance. In comparison with a MOSFET, an optimized Ge-source TFET is projected to provide for a lower energy per operation for throughput in the frequency range of up to ~1 GHz for sub-0.5-V operation.
TL;DR: In this article, a new methodology is developed to determine spatial location and properties of traps generated by electrical stressing of AlGaN/GaN high-electron mobility transistors, based on integrated optical and electrical analysis.
Abstract: A new methodology is developed to determine spatial location and properties of traps generated by electrical stressing of AlGaN/GaN high-electron mobility transistors, based on integrated optical and electrical analysis. Mild off-state stress increases irreversibly the number of traps located in the near-surface AlGaN region at the gate edge. A deep level with 0.45-eV activation energy in fresh devices changes its nature to interacting defect after the off-state stress, accompanied by an activation energy change. These results are consistent with trap generation in the near-surface AlGaN region at the gate edge related to high electric field and gate leakage current, as stressing does not result in the generation of cracks in the AlGaN layer.
TL;DR: In this paper, an extraction technique for subgap density of states (DOS) in an n-channel amorphous InGaZnO thin-film transistor (TFT) by using multifrequency capacitancevoltage (C -V) characteristics is proposed and verified by comparing the measured I-V characteristics with the technology computer-aided design simulation results incorporating the extracted DOS as parameters.
Abstract: An extraction technique for subgap density of states (DOS) in an n-channel amorphous InGaZnO thin-film transistor (TFT) by using multifrequency capacitance-voltage (C -V) characteristics is proposed and verified by comparing the measured I- V characteristics with the technology computer-aided design simulation results incorporating the extracted DOS as parameters. It takes on the superposition of exponential tail states and exponential deep states with characteristic parameters for N TA = 1.1 × 1017 cm-3 · eV-1, N DA = 4 × 1015 cm-3 · eV-1, kT TA = 0.09 eV, and kT DA = 0.4 eV. The proposed technique allows obtaining the frequency-independent C-V curve, which is very useful for oxide semiconductor TFT modeling and characterization, and considers the nonlinear relation between the energy level of DOS and the gate voltage V GS. In addition, it is a simple, fast, and accurate extraction method for DOS in amorphous InGaZnO TFTs without optical illumination, temperature dependence, and numerical iteration.
TL;DR: In this paper, a 150-nm gate enhancement-mode InAlN/Aln/GaN high-electron-mobility transistors are demonstrated on SiC substrates using plasma-based gate-recess etch.
Abstract: Having a drain current density of 1.9 A/mm, a peak extrinsic transconductance of 800 mS/mm (the highest reported in III-nitride transistors), ft/fmax of 70/105 GHz, and Vbr of 29 V, 150-nm-gate enhancement-mode InAlN/AlN/GaN high-electron-mobility transistors are demonstrated on SiC substrates using plasma-based gate-recess etch. The possible plasma-induced damage in the gate region was investigated using interface-trap states extracted from temperature-dependent subthreshold slopes.
IBM1
TL;DR: In this paper, a dual-gate graphene field effect transistor with a cutoff frequency of 50 GHz is presented, which is the highest frequency reported for any graphene transistor, and it also exceeds that of Si MOS field effect transistors at the same gate length.
Abstract: A dual-gate graphene field-effect transistor is presented, which shows improved radio-frequency (RF) performance by reducing the access resistance using electrostatic doping. With a carrier mobility of 2700 cm2/V · s, a cutoff frequency of 50 GHz is demonstrated in a 350-nm-gate-length device. This fT value is the highest frequency reported to date for any graphene transistor, and it also exceeds that of Si MOS field-effect transistors at the same gate length, illustrating the potential of graphene for RF applications.
TL;DR: Al2O3-based RRAM devices were fabricated using atomic layer deposition under 100°C and 300°C deposition temperatures, respectively, and their resistance-switching behaviors were investigated.
Abstract: Al2O3-based RRAM devices were fabricated using atomic layer deposition under 100°C and 300°C deposition temperatures, respectively, and their resistance-switching behaviors were investigated. Both devices show unipolar switching if the top electrode (TE) is made of Ti/Al, whereas the bipolar phenomenon is observed when TE is pure aluminum. Devices fabricated at higher temperature give better uniformity and higher resistance ratio. Ultralow RESET current (~1 μA) was obtained, together with adequate voltage margin.
TL;DR: In this article, a 30-nm InAs pseudomorphic HEMTs (PHEMTs) with tins = 4 nm is presented, which exhibits excellent gm,max of 1.9 S/mm, fT of 644 GHz, and fmax of 681 GHz at VDS = 0.5 V simultaneously.
Abstract: We present 30-nm InAs pseudomorphic HEMTs (PHEMTs) on an InP substrate with record fT characteristics and well-balanced fT and fmax values. This result was obtained by improving short-channel effects through widening of the side-recess spacing (Lside) to 150 nm, as well as reducing parasitic source and drain resistances. To compensate for an increase in Rs and Rd due to Lside widening, we optimized the ohmic contact process so as to decrease the specific ohmic contact resistance (Rc) to the InGaAs cap to 0.01 Ω·mm. A 30-nm InAs PHEMT with tins = 4 nm exhibits excellent gm,max of 1.9 S/mm, fT of 644 GHz, and fmax of 681 GHz at VDS = 0.5 V simultaneously. To the knowledge of the authors, the obtained fT in this work is the highest ever reported in any FET on any material system. This is also the first demonstration of simultaneous fT and fmax higher than 640 GHz in any transistor technology.