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Showing papers in "IEEE Electron Device Letters in 2012"


Journal ArticleDOI
Han Liu1, P. D. Ye1
TL;DR: In this paper, the authors demonstrate atomic layer-deposited (ALD) high-k dielectric integration on 2-D layer-structured molybdenum disulfide (MoS2) crystals and MoS2 dual-gate n-channel MOSFETs with ALD Al2O3 as the gate.
Abstract: We demonstrate atomic-layer-deposited (ALD) high-k dielectric integration on 2-D layer-structured molybdenum disulfide (MoS2) crystals and MoS2 dual-gate n-channel MOSFETs with ALD Al2O3 as the gate dielectric. Our C- V study of MOSFET structures shows good interface between 2-D MoS2 crystal and ALD Al2O3. Maximum drain currents using back gates and top gates are measured to be 7.07 and 6.42 mA/mm, respectively, at Vds = 2 V with a channel width of 3 μm, a channel length of 9 μm, and a top-gate length of 3 μm. We achieve the highest field-effect mobility of electrons using back-gate control to be 517 cm2/V·s. The highest current on/off ratio is over 108.

381 citations


Journal ArticleDOI
TL;DR: In this paper, the authors reported 30-nm-gate-length InAlN/Aln/GaN/SiC high-electron-mobility transistors with a record current gain cutoff frequency (fT) of 370 GHz.
Abstract: We report 30-nm-gate-length InAlN/AlN/GaN/SiC high-electron-mobility transistors (HEMTs) with a record current gain cutoff frequency (fT) of 370 GHz. The HEMT without back barrier exhibits an extrinsic transconductance (gm.ext) of 650 mS/mm and an on/off current ratio of 106 owing to the incorporation of dielectric-free passivation and regrown ohmic contacts with a contact resistance of 0.16 Ω·mm. Delay analysis suggests that the high fT is a result of low gate-drain parasitics associated with the rectangular gate. Although it appears possible to reach 500-GHz fT by further reducing the gate length, it is imperative to investigate alternative structures that offer higher mobility/velocity while keeping the best possible electrostatic control in ultrascaled geometry.

315 citations


Journal ArticleDOI
TL;DR: In this paper, a SPICE compact model for metaloxide-based resistive random access memory (RRAM) was developed, which includes the critical impact of temperature change and temporal variation.
Abstract: A SPICE compact model is developed for metal-oxide-based resistive random access memory (RRAM). The model includes the critical impact of temperature change and temporal variation. Using experimental data from HfOx-based RRAM, the model reproduces both the voltage-time relationship and the cycle-to-cycle variation in the RESET of the memory cells.

225 citations


Journal ArticleDOI
TL;DR: The tri-gate normally-off GaN on-Si field effect transistor (MISFET) was proposed in this paper, achieving a breakdown voltage of 565 V at a drain leakage current of 0.6 μA/mm and Vgs = 0.80 ± 0.06 V.
Abstract: We present a new normally-off GaN transistor-the tri-gate normally-off GaN metal-insulator-semiconductor field- effect transistor (MISFET). Due to the excellent channel control of a new 3-D gate structure, a breakdown voltage of 565 V has been achieved at a drain leakage current of 0.6 μA/mm and Vgs = 0. The new device has an on/off current ratio of more than eight orders of magnitude and a subthreshold slope of 86 ± 9 mV/decade. The threshold voltage of the new device is 0.80 ± 0.06 V with a maximum drain current of 530 mA/mm. These results confirm the great potential of the tri-gate normally-off GaN-on-Si MISFETs for the next generation of power electronics.

217 citations


Journal ArticleDOI
TL;DR: In this paper, an effective passivation technique for AlGaN/GaN high-electron-mobility transistors (HEMTs) was presented, which features an AlN thin film grown by plasma-enhanced atomic layer deposition (PEALD).
Abstract: An effective passivation technique for AlGaN/GaN high-electron-mobility transistors (HEMTs) is presented. This technique features an AlN thin film grown by plasma-enhanced atomic layer deposition (PEALD). With in situ remote plasma pretreatments prior to the AlN deposition, an atomically sharp interface between ALD-AlN and III-nitride has been obtained. Significant current collapse suppression and dynamic ON-resistance reduction are demonstrated in the ALD-AlN-passivated AlGaN/GaN HEMTs under high-drain-bias switching conditions.

215 citations


Journal ArticleDOI
TL;DR: In this article, the performance of high-κ /metal gate nanowire (NW) transistors without junctions is reported, with a channel thickness of 9 nm and sub-15-nm gate length and width.
Abstract: In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (Ion/Ioff) >; 106. For the first time, an SS lower than 70 mV/dec is achieved at LG = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.

211 citations


Journal ArticleDOI
TL;DR: In this paper, a novel Au-free CMOS process compatible process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors is presented.
Abstract: We report on a novel Au-free CMOS process-compatible process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors. The process starts from a 150-mm GaN-on-Si substrate with an embedded Si3N4/Al2O3 bilayer gate dielectric, encapsulated by a high-temperature low-pressure chemical vapor deposited nitride layer. Power devices with a 20-mm gate width reach a maximum output current of 8 A, a breakdown voltage of 750 V, and a specific on-resistance Ron, sp of 2.9 mΩ·cm2. The off-state drain leakage at 600 V is 7 μA. We show robust gate dielectrics with a large gate bias swing.

190 citations


Journal ArticleDOI
TL;DR: In this article, the vertical leakage/breakdown mechanisms in AlGaN/GaN high-electron-mobility transistors grown on low-resistivity p-type (111) Si substrate are studied by temperature-dependent current-voltage (I-V) measurements.
Abstract: Vertical leakage/breakdown mechanisms in AlGaN/GaN high-electron-mobility transistors grown on low-resistivity p-type (111) Si substrate are studied by temperature-dependent current-voltage ( I-V) measurements. It is found that the top-to-substrate vertical breakdown voltage (BV) is dominated by the space-charge-limited current conduction involving both acceptor and donor traps in the GaN buffer/transition layer. From the temperature-dependent transient backgating measurements, the acceptor level at EV + 543 meV and the donor level at EC-616 meV were identified.

173 citations


Journal ArticleDOI
TL;DR: In this article, a hot-electron graphene base transistor (GBT) is proposed for high-frequency operation, which can potentially allow terahertz operation, based on energy-band considerations.
Abstract: We present a novel graphene-based-device concept for a high-frequency operation: a hot-electron graphene base transistor (GBT). Simulations show that GBTs have high current on/off ratios and high current gain. Simulations and small-signal models indicate that it potentially allows terahertz operation. Based on energy-band considerations, we propose a specific material solution that is compatible with SiGe process lines.

157 citations


Journal ArticleDOI
TL;DR: In this article, the impact of random dopant fluctuation (RDF) on junctionless FinFET variability was investigated for sub-32-nm technology generations using technology computer-aided design (TCAD) simulations.
Abstract: Junctionless fin held-effect transistor (FinFET) variability due to random dopant fluctuation (RDF) was investigated for sub-32-nm technology generations using technology computer-aided design (TCAD) simulations. Results indicate that variations in threshold voltage, drive current, leakage current, and drain-induced barrier lowering are heavily impacted by RDF for junctionless FinFETs with sufficiently high channel doping (greater than 1019 cm-3). Unexpectedly, the RDF impact is found to be less severe for finer technology generations, although the overall magnitude is still significant compared to line-edge-roughness-induced variability.

153 citations


Journal ArticleDOI
TL;DR: In this article, the fabrication of completely CMOS-compatible ferroelectric field effect transistors (FETs) by stabilization of a Ferroelectric phase in 10-nm-thin Si:HfO2 was reported.
Abstract: We report the fabrication of completely CMOS-compatible ferroelectric field-effect transistors (FETs) by stabilization of a ferroelectric phase in 10-nm-thin Si:HfO2. The program and erase operation of this metal-ferroelectric-insulator-silicon FET (MFIS) with poly-Si/TiN/Si:HfO2/SiO2/Si gate stack is compared to the transient switching behavior of a TiN-based metal-ferroelectric-metal (MFM) capacitor. Polarization reversal in the MFM capacitor follows a characteristic time and field dependence for ferroelectric domain switching, leading to a higher switching speed with increasing applied field. Similar observations were made for the material when implemented into an MFIS structure. Nonvolatile switching was observed down to 20-ns pulsewidth, yielding a memory window (MW) of 1.2 V. Further increase in gate bias or pulsewidth led to charge injection and degradation of the MW. Retention measurements for up to 106 s suggest a retention of more than ten years.

Journal ArticleDOI
TL;DR: In this article, a GaN-based heterostructure lateral Schottky barrier diodes (SBDs) are investigated on n-SiC substrate, which have very low onset voltage VF = 0.43 V, high reverse blocking VBR >; 1000 V, very low capacitive charge of 0.213 nC/A, and a very fast recovery time of 10 ps.
Abstract: GaN-based heterostructure lateral Schottky barrier diodes (SBDs) grown on n-SiC substrate are investigated in this letter. These SBDs own very low onset voltage VF = 0.43 V, high reverse blocking VBR >; 1000 V, very low capacitive charge of 0.213 nC/A, and a very fast recovery time of 10 ps. These unique qualities are achieved by combining lateral topology, GaN:C back-barrier epitaxial structure, fully recessed Schottky anode (φB = 0.43 eV), and slanted anode field plate in a robust and innovative process. Diode operation at elevated temperature up to 200 °C was also characterized.

Journal ArticleDOI
TL;DR: In this article, a current aperture vertical electron transistor (CAVET) with a Mg-ion-implanted current blocking layer (CBL) and a channel regrown by plasma assisted molecular beam epitaxy (MBE), is successfully demonstrated on bulk GaN to work as a high voltage device.
Abstract: A current aperture vertical electron transistor (CAVET) with a Mg-ion-implanted current blocking layer (CBL) and a channel regrown by plasma assisted molecular beam epitaxy (MBE), is successfully demonstrated on bulk GaN to work as a high voltage device. The fabrication of the device combined a drift region grown by metalorganic chemical vapor deposition (MOCVD), to hold the blocking voltage, with AlGaN/GaN layers regrown by plasma-MBE to conduct current. The device registered a maximum current of 4 kA· cm-2 under direct-current operation offering a specific on-state resistance Ron - A of 2.2 mΩ·cm2. With 80 μs pulses applied to the gate, the devices showed no dispersion. The increased aperture length Lap resulted in the decrease in specific Ron, as expected. The impact of the gate overlap to aperture Lgo on the leakage current was studied, where the leakage current was found to increase with a smaller overlap.

Journal ArticleDOI
TL;DR: A new type of true random number generator, based on the random telegraph noise of a contact-resistive random access memory device, is proposed in this letter, demonstrating substantial saving in the circuit area.
Abstract: A new type of true random number generator, based on the random telegraph noise of a contact-resistive random access memory device, is proposed in this letter. The random-number generator consists of only a simple bias circuit plus a comparator, leading to small circuit area and low power consumption. By realizing this generator by the 65-nm complementary metal-oxide-semiconductor logic process, the occupied area can be as low as 45 μm2, demonstrating substantial saving in the circuit area.

Journal ArticleDOI
Kirsten E. Moselund1, Heinz Schmid1, Cedric D Bessire1, Mikael Björk, H. Ghoneim1, Heike Riel1 
TL;DR: In this paper, a vertical InAs-Si nanowire heterojunction tunnel FET is presented, which achieves high Ion/Ioff ratios above 106, with an Ion of 2.4 μA/μm and an inverse sub-threshold slope of 150 mV/dec measured over three decades of current.
Abstract: In this letter, we present vertical InAs-Si nanowire heterojunction tunnel FETs (TFETs). The devices consist of an InAs source on a Si channel and drain, with a wraparound gate stack. The Si-InAs combination allows achieving high Ion/Ioff ratios above 106, with an Ion of 2.4 μA/μm and an inverse subthreshold slope of 150 mV/dec measured over three decades of current. Ni alloying of the InAs top contact is shown to improve performance of both diodes and TFETs significantly. The combination of higher doping at the contact and the alloying also leads to an enhanced performance compared with previously published devices.

Journal ArticleDOI
TL;DR: In this paper, the electrostatic and performance of cylindrical silicon nanowire (NW) MOSFETs with an omega-shaped gate and diameters down to 8 nm are investigated.
Abstract: In this letter, the electrostatic and the performance of cylindrical silicon nanowire (NW) MOSFETs with an omega-shaped gate and diameters down to 8 nm are investigated. The impact of silicon nitride (SiN) spacer thickness (7, 10, or 15 nm) on short-channel performance is examined. The tradeoff between superior electrostatic confinement and electrical performance, which will be an essential consideration for the design of future NW devices, is clearly observed. Finally, a comparison with trigate NWs shows an improved electrostatic control for a cylindrical-shaped gate, as theoretically expected.

Journal ArticleDOI
TL;DR: An analytical formulation of the threshold voltage variance induced by random dopant fluctuations in junctionless transistors is derived for both cylindrical nanowire and planar double-gate structures under uniform channel and constant mobility approximation as mentioned in this paper.
Abstract: An analytical formulation of the threshold voltage variance induced by random dopant fluctuations in junctionless transistors is derived for both cylindrical nanowire and planar double-gate structures under uniform channel and constant mobility approximation. Results from drift-diffusion-based numerical methods are in reasonable agreement also for large , including mobility variations, and for short gate lengths. The results clearly indicate that the threshold voltage fluctuations can become a concern with the reduction of the critical dimensions.

Journal ArticleDOI
TL;DR: Ferroelectric properties of Si-doped HfO2 thin films (10 nm) have been investigated in this article, where the potential applicability of these thin films for future 3-D ferroelectric random access memory capacitors is evaluated.
Abstract: Ferroelectric properties of Si-doped HfO2 thin films (10 nm) have been investigated. The focus of this letter is to evaluate the potential applicability of these thin films for future 3-D ferroelectric random access memory capacitors. Polarization switching was tested at elevated temperatures up to 185°C and showed no severe degradation. Domain switching dynamics were electrically characterized with pulse-switching tests and were not in accordance with Kolmogorov-Avrami-type switching. Nucleation-limited switching is proposed to be applicable for these new types of ferroelectric thin films. Furthermore, same-state and opposite-state retention tests were performed at 125°C up to 20 h. It was found that samples that had previously been annealed at 800°C showed improved retention of the written state as well as of the opposite state. In addition, fatigue measurements were carried out, and no degradation occurred for 106 programming and erase cycles at 3 V.

Journal ArticleDOI
TL;DR: In this article, a single-photon avalanche diode (SPAD) was reported in a 130-nm CMOS imaging process which achieves a peak photon detection efficiency (PDE) of ≈72% at 560 nm with >; 40% PDE from 410 to 760 nm.
Abstract: A single-photon avalanche diode (SPAD) is reported in a 130-nm CMOS imaging process which achieves a peak photon detection efficiency (PDE) of ≈72% at 560 nm with >; 40% PDE from 410 to 760 nm. This is achieved by eliminating junction isolation, utilizing dielectric stack optimizations designed for CMOS imaging, and operating at high bias enabled by ac coupling. The 8-μm-diameter device achieves a low median dark count rate of 18 Hz at 2-V excess bias (VEB), a <; 60-ps FWHM timing resolution at 654 nm from VEB = 6 V to VEB = 12 V, and a <; 4% after-pulsing probability. This represents performance which is comparable to fully customized discrete SPADs.

Journal ArticleDOI
TL;DR: In this article, a dielectric modulated double-gate tunnel field effect transistor (DG-TFET)-based sensor was proposed for low power consumption label-free biomolecule detection applications.
Abstract: In this letter, we propose a dielectric modulated double-gate tunnel field-effect transistor (DG-TFET)-based sensor for low power consumption label-free biomolecule detection applications. A nanogap-embedded FET-based biosensor has already been demonstrated experimentally, but a TFET-based biosensor has not been demonstrated earlier. Thus, a concept of TFET-based sensor is presented by analytical and simulation-based study. The results indicate better sensitivity toward two different effects (dielectric constant and charge of biomolecule) in comparison with a FET-based biosensor, and the additional advantages of CMOS compatibility, low leakage (low static power dissipation), and steep subthreshold slope make TFET an attractive alternative architecture for CMOS-based sensor applications.

Journal ArticleDOI
TL;DR: In this paper, nonalloyed ohmic contacts regrown by molecular beam epitaxy were made on InAlN, AlN/AlN/GaN/SiC high-electron-mobility transistors (HEMTs).
Abstract: Nonalloyed ohmic contacts regrown by molecular beam epitaxy were made on InAlN/AlN/GaN/SiC high-electron-mobility transistors (HEMTs). Transmission-line-method measurements were carried out from 4 K to 350 K. Although the total contact resistance is dominated by the metal/ n+-GaN resistance ( ~ 0.16 Ω·mm), the resistance induced by the interface between the regrown n+ GaN and HEMT channel is found to be 0.05-0.075 Ω·mm over the entire temperature window, indicating a minimal barrier for electron flow at the as-regrown interface. The quantum contact resistance theory suggests that the interface resistance can be further reduced to be <; 0.02 Ω·mm in GaN HEMTs.

Journal ArticleDOI
TL;DR: In this article, the currentvoltage characteristics of AlGaSb/InAs staggered-gap n-channel tunnel field effect transistors are simulated in a geometry in which the gate electric field is oriented to be in the same direction as the tunnel junction internal field.
Abstract: The current-voltage characteristics of AlGaSb/InAs staggered-gap n-channel tunnel field-effect transistors are simulated in a geometry in which the gate electric field is oriented to be in the same direction as the tunnel junction internal field. It is shown that this geometry can also support low-voltage operation and low subthreshold swing. In the absence of a simple analytic theory for this transistor to allow direct analytic comparisons, two-dimensional numerical simulations are used to explore the electrostatic and geometrical design considerations including dependence on gate length, gate underlap, gate undercut, and equivalent oxide thickness.

Journal ArticleDOI
TL;DR: In this article, a tunnel field effect transistor (TFET) with a staggered AlGaSb/InAs heterojunction with the tunneling direction oriented in-line with the gate field was shown to achieve a record high on-current of 78 μA/μm in a TFET at room temperature.
Abstract: Record high on-current of 78 μA/ μm in a tunnel field-effect transistor (TFET) is achieved at 0.5 V at room temperature. The TFET employs a staggered AlGaSb/InAs heterojunction with the tunneling direction oriented in-line with the gate field. The measured results are consistent with numerical simulation of the device structure. Simulations of optimized structures suggest that switching speed comparable to that of the MOSFET should be achievable with improvements in the source and drain resistances.

Journal ArticleDOI
TL;DR: In this article, an enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs) were demon-strated based on lateral scaling of the 2-D electron gas channel using nanochannel array (NCA) structure.
Abstract: In this letter, enhancement-mode (E-mode) AlGaN/ GaN high electron mobility transistors (HEMTs) were demon- strated based on lateral scaling of the 2-D electron gas channel using nanochannel array (NCA) structure. The NCA structure consists of multiple parallel channels with nanoscale width defined by electron-beam lithography and dry etching. Because of the improved gate control from the channel sidewalls and partially relaxed piezoelectric polarization, the fabricated 2 μm-gate-length NCA-HEMT with a nanochannel width of 64 nm showed a thresh- old voltage of +0.6 V and a higher extrinsic transconductance of 123 mS/mm, compared to -1.6 V and 106 mS/mm for the conventional HEMT with μm-scale channel width. The scaling of threshold voltages, peak transconductance, and gate leakage as a function of the nanochannel width were investigated. Small-signal RF performance of NCA-HEMTs were characterized for the first time and compared with those of conventional HEMTs.

Journal ArticleDOI
TL;DR: In this paper, a capacitor-less one-transistor dynamic random access memory (DRAM) based on fully depleted silicon-on-insulator substrate is presented. But the performance of the DRAM is limited.
Abstract: We demonstrate experimentally a capacitor-less one-transistor dynamic random access memory (DRAM) based on fully depleted silicon-on-insulator substrate. In our device, the charges are directly stored in front gate capacitor (CG) and read out through a fast feedback regeneration process. The simulated read/write times of our device reach below 1 ns, much faster than conventional 1T-1C DRAM. The read/write biasing voltages can be scaled down to 1.1 V, achieving long retention time (tre >; 5s).

Journal ArticleDOI
TL;DR: In this article, an InGaAs/InAlAs/INP high-electron-mobility transistor (InP HEMT) with record noise temperature at very low dc power dissipation was presented.
Abstract: We present in this letter an InGaAs/InAlAs/InP high-electron-mobility transistor (InP HEMT) with record noise temperature at very low dc power dissipation. By minimizing parasitic contact and sheet resistances and the gate current, a 130-nm-gate-length InP HEMT was optimized for cryogenic low-noise operation. When integrated in a 4- to 8-GHz three-stage hybrid low-noise amplifier operating at 10 K, a noise temperature of 1.2 K ± 1.3 K at 5.2 GHz was measured. The gain of the amplifier across the entire band was 44 dB, consuming only 4.2 mW of dc power. The extracted minimum noise temperature of the InP HEMT was 1 K at 6 GHz.

Journal ArticleDOI
TL;DR: In this paper, the germanium electron-hole (EH) bilayer tunnel field effect transistor (TFL) was proposed to provide a quasi-ideal alignment between the tunneling path and the electric field controlled by the gate.
Abstract: In this letter, we present a novel device, the germanium electron-hole (EH) bilayer tunnel field-effect transistor, which exploits carrier tunneling through a bias-induced EH bilayer. The proposed architecture provides a quasi-ideal alignment between the tunneling path and the electric field controlled by the gate. The device principle and performances are studied by 2-D numerical simulations. This device allows interesting features in terms of low operating voltage (<; 0.5 V), due to its super-steep subthreshold slope (SSAVG ~ 13 mV/dec over six decades of current), ION/IOFF ratio of ~ 109, and drive current of ION ~ 10 μA/μm at VDD = 0.5 V. The same structure with symmetric voltages can be used to achieve a p-type device with ION and IOFF levels comparable to the n-type, which enables a straightforward implementation of complementary logic that could theoretically reach a maximum operating frequency of 1.39 GHz when VDD = 0.25 V.

Journal ArticleDOI
TL;DR: In this paper, the channel width scaling of back-gated MoS2 field effect transistors from 2 μm down to 60 nm was studied. And the authors showed that the channel conductance scales linearly with channel width, indicating no evident edge damage for MoS 2 nanoribbons with widths down to 50 nm as defined by plasma dry etching.
Abstract: We study the channel width scaling of back-gated MoS2 metal-oxide-semiconductor field-effect transistors from 2 μm down to 60 nm. We reveal that the channel conductance scales linearly with channel width, indicating no evident edge damage for MoS2 nanoribbons with widths down to 60 nm as defined by plasma dry etching. However, these transistors show a strong positive threshold voltage (VT) shift with narrow channel widths of less than 200 nm. Our results also show that transistors with thinner channel thicknesses have larger VT shifts associated with width scaling. Devices fabricated on a 6-nm-thick MoS2 crystal underwent the transition from depletion mode to enhancement mode.

Journal ArticleDOI
TL;DR: In this article, a subharmonic resistive graphene FET mixer utilizing the symmetrical channel-resistance versus gate-voltage characteristic was demonstrated, achieving a down-conversion loss of 24 dB with fRF = 2 GHz, fLO= 1.01 GHz, and fIF= 20 MHz in a 50- Ω-impedance system.
Abstract: We demonstrate a subharmonic resistive graphene FET mixer utilizing the symmetrical channel-resistance versus gate-voltage characteristic. A down-conversion loss of 24 dB is obtained with fRF = 2 GHz, fLO= 1.01 GHz, and fIF= 20 MHz in a 50- Ω-impedance system. Unlike conventional subharmonic resistive FET mixers, this type of mixer operates with only one transistor and does not need any balun at the local oscillator (LO) port, which makes it more compact.

Journal ArticleDOI
TL;DR: In this article, the authors describe the procedure to manufacture high-performance surface acoustic wave (SAW) resonators on AlN/diamond heterostructures working at frequencies beyond 10 GHz.
Abstract: This letter describes the procedure to manufacture high-performance surface acoustic wave (SAW) resonators on AlN/diamond heterostructures working at frequencies beyond 10 GHz. In the design of SAW devices on AlN/diamond systems, the thickness of the piezoelectric layer is a key parameter. The influence of the film thickness on the SAW device response has been studied. Optimized thin films combined with advanced e-beam lithographic techniques have allowed the fabrication of one-port SAW resonators with finger width and pitch of 200 nm operating in the 10-14 GHz range with up to 36 dB out-of-band rejection.