Showing papers in "IEEE Electron Device Letters in 2015"

First Demonstration of Amplification at 1 THz Using 25-nm InP High Electron Mobility Transistor Process

Abstract: We report the first ever terahertz monolithic integrated circuit amplifier based on 25-nm InP high electron mobility transistor (HEMT) process demonstrating amplification at 1 THz (1000 GHz) with 9-dB measured gain at 1 THz. This milestone was achieved with a 25-nm InP HEMT transistor, which exhibits 3.5-dB maximum available gain at 1 and 1.5 THz projected $f_{\mathrm {\mathbf {MAX}}}$ .

Optimization of Conductance Change in Pr 1– x Ca x MnO 3 -Based Synaptic Devices for Neuromorphic Systems

Abstract: The optimization of conductance change behavior in synaptic devices based on analog resistive memory is studied for the use in neuromorphic systems. Resistive memory based on Pr1– x Ca x MnO3 (PCMO) is applied to a neural network application (classification of Modified National Institute of Standards and Technology handwritten digits using a multilayer perceptron trained with backpropagation) under a wide variety of simulated conductance change behaviors. Linear and symmetric conductance changes (e.g., self-similar response during both increasing and decreasing device conductance) are shown to offer the highest classification accuracies. Further improvements can be obtained using nonidentical training pulses, at the cost of requiring measurement of individual conductance during training. Such a system can be expected to achieve, with our existing PCMO-based synaptic devices, a generalization accuracy on a previously-unseen test set of 90.55%. These results are promising for hardware demonstration of high neuromorphic accuracies using existing synaptic devices.

Vertical GaN p-n Junction Diodes With High Breakdown Voltages Over 4 kV

Abstract: Vertical structured GaN power devices have recently been attracting a great interest because of their potential on extremely high-power conversion efficiency. This letter describes increased breakdown voltages in the vertical GaN p-n diodes fabricated on the free-standing GaN substrates. By applying multiple lightly Si doped n-GaN drift layers to the p-n diode, the record breakdown voltages ( $V_{B}$ ) of 4.7 kV combined with low specific differential ON-resistance ( $R_{\mathrm{\scriptscriptstyle ON}}$ ) of 1.7 $\text{m}\Omega $ cm2 were achieved. With reducing the Si-doping concentration of the top n-GaN drift layer adjacent to the p-n junction using well-controlled metal-organic vapor phase epitaxy systems, the peak electric field at the p-n junction could be suppressed under high negatively biased conditions. The second drift layer with a moderate doping concentration contributed to the low $R_{\mathrm{\scriptscriptstyle ON}}$ . A Baliga’s figure of merit ( $V_{B}^{2}/R_{\mathrm{\scriptscriptstyle ON}}$ ) was 13 GW/cm2. These are the best values ever reported among those achieved by GaN p-n junction diodes on the free-standing GaN substrates.

Utilizing the Variability of Resistive Random Access Memory to Implement Reconfigurable Physical Unclonable Functions

Abstract: The stochastic switching mechanism and intrinsic variability of resistive random access memory (RRAM) present severe challenges for memory applications, which, however, may be utilized to implement the physical unclonable function (PUF) for hardware security. A PUF based on RRAM resistance variability is proposed in this letter. Unlike PUFs based on manufacturing variation, this proposal exploits an intrinsic variability in physical mechanisms with reconfigurability. Key characteristics of the PUF design are assessed by simulation using measured RRAM properties and device model. Truly random variation of RRAM resistance is critical for PUF uniqueness (or unclonability). The reliability (or robustness) of the proposed PUF is affected by temperature and voltage dependence of RRAM resistance as well as retention characteristics. Large separation between inter-chip and intra-chip Hamming distance as the measure of uniqueness and reliability confirms the feasibility of the PUF proposal.

Ultrahigh-Speed GaN High-Electron-Mobility Transistors With $f_{T}/f_{\mathrm {max}}$ of 454/444 GHz

Abstract: This letter reports record RF performance of deeply scaled depletion-mode GaN-high-electron-mobility transistors (GaN-HEMTs). Based on double heterojunction AlN/GaN/AlGaN epitaxial structure, fully passivated devices were fabricated by self-aligned-gate technology featuring recessed $n^{+}$ -GaN ohmic contact regrown by molecular beam epitaxy. Record-high $f_{T}$ of 454 GHz and simultaneous $f_{{\rm {max}}}$ of 444 GHz were achieved on a 20-nm gate HEMT with 50-nm-wide gate-source and gate-drain separation. With an OFF-state breakdown voltage of 10 V, the Johnson figure of merit of this device reaches 4.5 THz-V, representing the state-of-the-art performance of GaN transistor technology to-date. Compared with previous E-mode GaN-HEMTs of similar device structure, significantly reduced extrinsic gate capacitance and enhanced average electron velocity are the key reasons for improved frequency characteristic.

Forward Bias Gate Breakdown Mechanism in Enhancement-Mode p-GaN Gate AlGaN/GaN High-Electron Mobility Transistors

Abstract: In this letter, we studied the forward bias gate breakdown mechanism on enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistors To the best of our knowledge, it is the first time that the temperature dependence of the forward gate breakdown has been characterized We report for the first time on the observation of a positive temperature dependence, ie, a higher temperature leads to a higher gate breakdown voltage Such unexpected behavior is explained by avalanche breakdown mechanism: at a high positive gate bias, electron/hole pairs are generated in the depletion region at the Schottky metal/p-GaN junction Furthermore, at a high gate bias but before the catastrophic gate breakdown, a light emission was detected by a emission microscopy measurement This effect indicates an avalanche luminescence, which is mainly due to the recombination of the generated electron/hole pairs

1.9-kV AlGaN/GaN Lateral Schottky Barrier Diodes on Silicon

Abstract: In this letter, we present AlGaN/GaN lateral Schottky barrier diodes on silicon with recessed anodes and dual field plates. A low specific ON-resistance $R_{{\rm ON, SP}}$ (5.12 $\text{m}\Omega \cdot \textrm {cm}^{2}$ ), a low turn-ON voltage ( 1.9 kV) were simultaneously achieved in devices with a 25- $\mu \text{m}$ anode/cathode distance, resulting in a power figure-of-merit BV $^{2}$ / $R_{{\rm ON, SP}}$ of 727 $\textrm {MW}\,\cdot \, \textrm {cm}^{-2}$ . The record high BV of 1.9 kV is attributed to the dual field-plate structure.

Threshold Selector With High Selectivity and Steep Slope for Cross-Point Memory Array

Abstract: In this letter, we demonstrated a new type of threshold selector with excellent electrical characteristics for cross-point memory array. The proposed Ag/TiO2-based threshold selector device showed high selectivity ( $\sim 10^{\mathrm {\mathbf {7}}}$ ) and steep slope ( $ mV/decade). The observed threshold switching in programmable metallization cell device occurred due to the spontaneous rupturing of silver (Ag) filament. The Ag ionization to minimize the steric repulsion between Ag and surrounding TiO2 electrolyte was the main origin of the spontaneous rupture.

Steep Slope and Near Non-Hysteresis of FETs With Antiferroelectric-Like HfZrO for Low-Power Electronics

Abstract: The antiferroelectricity in HfZrO2 (HZO) annealed at 600 °C with an abrupt turn ON of FET characteristics with SS $_{\rm {min}}=23$ mV/dec and SS $_{\rm {avg}}=50$ mV/dec over 4 decades of $I_{\rm {DS}}$ is demonstrated. The near non-hysteresis is achieved with an antiferroelectric-like HZO due to a small remanent polarization and a coercive field. A feasible concept of coupling the antiferroelectric and ferroelectric type HZO are used for low-power electronics and the memory applications, respectively.

Demonstration of Low Power 3-bit Multilevel Cell Characteristics in a TaO x -Based RRAM by Stack Engineering

Abstract: Multilevel cell (MLC) storage technology is attractive in achieving ultrahigh density memory with low cost. In this letter, we have demonstrated 3-bit per cell storage characteristics in a TaO x -based RRAM. By analyzing the key requirements for MLC operation mainly the switching uniformity and stability of resistance levels, an engineered stack based on thermodynamics in top electrode/(vacancy reservoir/defect control layer)/switching layer/bottom electrode structure was designed. In the optimized stack with $\sim 10$ -nm Ta layer incorporated at W/TaO x interface, seven low resistance state levels with same high resistance state were obtained by controlling the switching current down from $30~\mu $ A enabling low power 3-bit storage in contrast to the control device which shows 2-bit MLC with resistance saturation. The improved switching and MLC behavior is attributed to the minimized stochastic nature of set/reset operations due to filament confinement by favorable electric field generation and formation of thin but highly conductive filament which is confirmed electrically.

Impact of Gate Metal on the Performance of p-GaN/AlGaN/GaN High Electron Mobility Transistors

Abstract: For conventional GaN-based high electron mobility transistors (HEMTs), the work function of gate metal is critical to electrical parameters, such as OFF-state leakage current, forward operating current, and threshold voltage. A high work function is thus required to maintain Schottky gate contact. In this letter, an enhancement-mode HEMT composed of p-type GaN/AlGaN/GaN was fabricated. Unlike typical HEMTs that the Schottky barrier height is determined by the energy difference between gate metal work function and semiconductor (AlGaN, or GaN) conduction band, the insertion of the p-GaN relieves the constraint of gate metal. In addition, the gate Schottky barrier now correlates to the valence band of the semiconductor. Here we compare the HEMT performance of different gate metals-Ni/Au, Ti/Au, and Mo/Ti/Au. The results reveal that a tradeoff between V TH and output drain current.

Experimental Characterization of Physical Unclonable Function Based on 1 kb Resistive Random Access Memory Arrays

Abstract: In this letter, we propose a reliable design of physical unclonable function (PUF) exploiting resistive random access memory (RRAM). Unlike the conventional silicon PUFs based on manufacturing process variation, the randomness of RRAM PUF comes from the stochastic switching mechanism and intrinsic variability of the RRAM devices. RRAM PUF’s characteristics, such as uniqueness and reliability, are evaluated on 1 kb HfO2-based 1-transistor-1-resistor (1T1R) arrays. Our experimental results show that the selection of the reference current significantly affects the uniqueness. More dummy cells to generate the reference can improve the uniqueness of RRAM. The reliability of RRAM PUF is determined by the RRAM data retention. A new design is proposed where the sum of the readout currents of multiple RRAM cells is used for generating one response bit, which statistically minimizes the risk of early lifetime failure. The experimental results show that with eight cells per bit, the retention time is more than 50 h at 150 °C or equivalently 10 years at 69 °C. This experimental work demonstrates that RRAM PUF is a viable technology for hardware security primitive with inter-Hamming distance 49.8% and intra-Hamming distance 0%.

Energy-Efficient Artificial Synapses Based on Flexible IGZO Electric-Double-Layer Transistors

Abstract: Flexible low-voltage indium-gallium-zinc-oxide (IGZO) electric-double-layer transistors are fabricated on polyethylene terephthalate substrates at room temperature and proposed for energy-efficient artificial synapse application. The IGZO channel conductance and the gate voltage pulse are regarded as synaptic weight and synaptic spike, respectively. The energy consumption of our IGZO synaptic transistor is estimated to be as low as $\sim 0.23$ pJ/spike. Short-term synaptic plasticity and high-pass filtering behaviors are also mimicked in an individual IGZO synaptic transistor.

High Reverse Blocking and Low Onset Voltage AlGaN/GaN-on-Si Lateral Power Diode With MIS-Gated Hybrid Anode

Abstract: An AlGaN/GaN-on-Si lateral power diode with recessed metal/Al2O3/III-nitride (MIS)-gated ohmic anode for improved forward conduction and reverse blocking has been realized. The low onset voltage of $\sim 0.6$ V with good uniformity for the fabricated 189 devices is obtained. In comparison with the conventional Schottky diode the specific ON-resistance ( $R_{\mathrm {\mathbf {\mathrm{{\scriptscriptstyle ON}},SP}}})$ was reduced by 51% in a device with anode-to-cathode spacing ( $L_{\mathrm {\mathbf {AC}}})$ of 5 $\mu \text{m}$ . The incorporation of high- $k$ dielectric in the recessed gate region enabling two-order lower reverse leakage comparing with the conventional device, leading to a high breakdown voltage over 1.1 kV at leakage current as low as 10 $\mu \text{A}$ /mm in device with $L_{\mathrm {\mathbf {AC}}}=20~\mu \text{m}$ . The strong reverse blocking over 600 V was still achieved at 150 °C. The proposed diode is compatible with GaN normally $\mathbf {\mathrm{{\scriptstyle OFF}}}$ MIS high-electron-mobility transistors, revealing its potential for highly efficient GaN-on-Si power ICs.

Black Phosphorus p-MOSFETs With 7-nm HfO 2 Gate Dielectric and Low Contact Resistance

Abstract: We report record contact resistance and transconductance in locally back-gated black phosphorus p-MOSFETs with 7-nm thick HfO2 gate dielectrics. Devices with effective gate lengths, $L_{\mathrm {\mathbf {eff}}}$ , from 0.55 to 0.17 $\mu \text{m}$ were characterized and shown to have contact resistance values as low as $1.14~\pm ~0.05~\Omega $ -mm. In addition, devices with $L_{\mathrm {\mathbf {eff}}}= 0.17~\mu \text{m}$ displayed extrinsic transconductance exceeding 250 $\mu \text{S}$ / $\mu \text{m}$ and ON-state current approaching $300~\mu \text{A}$ / $\mu \text{m}$ .

Low On-Resistance Normally-Off GaN Double-Channel Metal–Oxide–Semiconductor High-Electron-Mobility Transistor

Abstract: A low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with $V_{\mathrm {th}}$ of +0.5 V at $I_{\mathrm {DS}}= 10 ~\mu \text{A}$ /mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/( $\text{V}\cdot \text{s}$ ). The on-resistance is as small as 6.9 $\Omega \cdot \text {mm}$ for a DC-MOS-HEMT with $L_{G}/L_{\mathrm {GS}}/L_{\mathrm {GD}} = 1.5/2/15~\mu \text{m}$ , and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained.

GaN-Based Metal-Insulator-Semiconductor High-Electron-Mobility Transistors Using Low-Pressure Chemical Vapor Deposition SiN x as Gate Dielectric

Abstract: In this letter, silicon nitride (SiN x ) film deposited at 780 °C by low-pressure chemical vapor deposition (LPCVD) was employed as gate dielectric for GaN-based metal–insulator–semiconductor high-electron-mobility transistors. The LPCVD-SiN x exhibit improved gate dielectric performance than the plasma enhanced chemical vapor deposition-SiN x , including smaller forward and reverse gate leakage, and higher forward gate breakdown voltage.

Low-Temperature Characteristics of HfO x -Based Resistive Random Access Memory

Abstract: This letter investigates the low-temperature switching characteristics and conduction mechanism of the Pt/HfO x /TiN resistive random access memory devices. For the first time, Pt/HfO x /TiN devices were demonstrated to be well functional at ultralow temperature (4 K). The switching voltages slightly increase at lower temperature. The failure state in a breakdown sample shows a metallic behavior, while the normal low-resistance states and high-resistance states show a semiconducting behavior. The slope change in the 1/kT plot below 77 K indicates a transition from the nearest-neighboring hopping to the variable range hopping. Different slopes or activation energies are observed at the same resistance level in the same device but after different programming cycles, indicating a cycle-dependent variation of the filament configuration.

Ab-Initio Simulation of van der Waals MoTe 2 –SnS 2 Heterotunneling FETs for Low-Power Electronics

Abstract: Band-to-band tunneling field-effect transistors (TFETs) made of a vertical heterojunction of single-layer MoTe2 and SnS2 are investigated by means of 3-D, full-band, atomistic quantum-transport simulations relying on a first-principles basis. At a supply voltage ${V_{\rm dd}=0.4}$ V and OFF-current $I_{\mathrm{{\scriptscriptstyle OFF}}}=10^{-6}\mu \text{A} / \mu \text{m}$ , on-state currents $>75\boldsymbol {\mu }\text{A} / \boldsymbol {\mu }\text{m}$ are reported for both n- and p-type logic switches. Our findings indicate that metal-dichalcogenide heterojunction TFETs represent a viable option in low-power electronics.

4-kV and 2.8- $\text{m}\Omega $ -cm 2 Vertical GaN p-n Diodes With Low Leakage Currents

Abstract: There is great interest in bulk GaN-based power electronics devices for applications requiring breakdown voltages greater than 3.3 kV. In this letter, the vertical GaN p-n diodes fabricated on improved bulk GaN substrates demonstrating low leakage currents ( $10^{4}$ cm $^{-2}$ ) bulk GaN substrates with improved quality and specifications that are uniquely suitable for power electronic device applications. The measured devices show breakdown voltages larger than 4 kV with an area differential specific ON-resistance ( $R_{\textrm {sp}}$ ) of less than 3 $\text{m}\Omega $ -cm2. Applications that would require such breakdown voltages, include ship propulsion, rail, wind, uninterruptable power supplies, and the power grid.

A 0.27e $^{-}_{\text {rms}}$ Read Noise 220- $\mu \text{V}/\text{e}^{-}$ Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11- $\mu \text{m}$ CIS Process

Abstract: A low temporal read noise and high conversion gain reset-gate-less CMOS image sensor (CIS) has been developed and demonstrated for the first time at photoelectron-counting-level imaging. To achieve a high pixel conversion gain without fine or special processes, the proposed pixel has two unique structures: 1) coupling capacitance between the transfer gate and floating diffusion (FD) and 2) coupling capacitance between the reset gate and FD, for removing parasitic capacitances around the FD node. As a result, a CIS with the proposed pixels is able to achieve a high pixel conversion gain of $220~\mu \text{V}/\text{e}^{ {{-}}}$ and a low read noise of 0.27e $^{-}_{\text {rms}}$ using correlated multiple-sampling-based readout circuitry.

4H-SiC Piezoresistive Pressure Sensors at 800 °C With Observed Sensitivity Recovery

Abstract: Uncooled MEMS-based 4H-SiC Wheatstone bridge configured piezoresistive pressure sensors were demonstrated from 23 °C to 800 °C. The full-scale output (FSO) voltage exhibited gradual decrease with increasing temperature from 23 °C to 400 °C, then swung upward as temperature increased further to where the values measured at 800 °C were nearly equal to or higher than the room temperature values. This newly observed FSO behavior in 4H-SiC contrasts sharply with the FSO behavior of silicon piezoresistive sensors that decrease continuously with increasing temperature. The increase in the sensor output sensitivity at 800 °C implies higher signal to noise ratio and improved fidelity, thereby offering promise of further insertion into >600 °C environments without the need for cooling and complex signal conditioning.

ZnO Nanowire-Reduced Graphene Oxide Hybrid Based Portable NH 3 Gas Sensing Electron Device

Abstract: A ZnO nanowire-reduced graphene oxide (ZnO-rGO) based portable ammonia (NH3) gas sensing electron device working at room temperature has been demonstrated for the first time. The sensor is developed on a microelectrode of micro-electromechanical systems and supported by peripheral circuits and a hosting computer, which enables the real-time detection of NH3 at room temperature. In contrast to the traditional sensors based on pure graphene or ZnO nanowires alone, the ZnO-rGO based gas sensing electron device can detect low-concentration (1 ppm) NH3 with higher sensitivity ( $\sim 7.2$ %). Besides, this sensor exhibits satisfying properties at sensing NH3 with the concentration as low as 500 ppb at room temperature.

Programming Protocol Optimization for Analog Weight Tuning in Resistive Memories

Abstract: Analog weight tuning in resistive memories is attractive for multilevel operation and neuro-inspired computing. To tune the device conductance to the desired states as fast as possible without sacrificing the accuracy, we propose an optimization programming protocol by adjusting the pulse amplitude incremental steps, the pulsewidth incremental steps, and the start voltages. Our experimental results on HfOx-based resistive memories indicate that avoiding over-reset by appropriate programming parameters is critical for fast convergence of the conductance tuning. The over-reset behavior is caused by the stochastic nature of filament formation and rupture, as simulated by a 1-D filament model.

Quanta Image Sensor Jot With Sub 0.3e- r.m.s. Read Noise and Photon Counting Capability

Abstract: The first quanta image sensor jot with photon counting capability is demonstrated. The low-voltage device demonstrates less than 0.3e- r.m.s. read noise on a single read out without the use of avalanche gain and single-electron signal quantization is observed. A new method for determining read noise and conversion gain is also introduced.

Dielectric Engineered Tunnel Field-Effect Transistor

Abstract: The dielectric engineered tunnel field-effect transistor (DE-TFET) as a high-performance steep transistor is proposed. In this device, a combination of high- $k$ and low- $k$ dielectrics results in a high electric field at the tunnel junction. As a result, a record ON-current of $\sim 1000~\mu \text{A}/\mu \text{m}$ and a subthreshold swing (SS) below 20 mV/decade are predicted for WTe2 DE-TFET. The proposed TFET works based on a homojunction channel and electrically doped contacts both of which are immune to interface states, dopant fluctuations, and dopant states in the bandgap, which typically deteriorate the OFF-state performance and SS in the conventional TFETs.

Robust SiN x /AlGaN Interface in GaN HEMTs Passivated by Thick LPCVD-Grown SiN x Layer

Abstract: Low-pressure chemical vapor deposition (LPCVD) technique is utilized for SiN x passivation of AlGaN/GaN high-electron-mobility transistors (HEMTs). A robust SiN x / AlGaN interface featuring high thermal stability and well-ordered crystalline structure is achieved by a processing strategy of “passivation-prior-to-ohmic” in HEMTs fabrication. Effective suppression of surface-trap-induced current collapse and lateral interface leakage current are demonstrated in the LPCVD-SiN x passivated HEMTs, as compared with conventional plasma-enhanced chemical vapor deposition-SiN x passivated ones. Energy dispersive X-ray spectroscopy mapping analysis of SiN x /AlGaN interfaces suggests the interface traps are likely to stem from amorphous oxide/oxynitride interfacial layer.

Avalanche Capability of Vertical GaN p-n Junctions on Bulk GaN Substrates

Abstract: Inductive avalanche test results presented in this letter demonstrate that GaN p-n diodes can sustain single-pulse and repetitive inductive avalanche currents. The 0.36-mm2 vertical GaN p-n diodes can sustain single-pulse avalanche currents as high as 10 A. The safe zone of the single-pulse avalanche current is limited by peak pulse power and energy deposited in the device. The temperature-dependent behavior of the breakdown voltage and the reverse-voltage at onset of avalanche has a positive temperature coefficient. Repetitive avalanche ruggedness testing was performed by applying $10^{\mathrm {5}}$ pulses at 5-kHz frequency with increasing repetitive stress current. Based on a population of 63 devices, the incremental failure rate under repetitive avalanche current increases with increasing avalanche current. The devices that survive the step stress test sustain no parametric drift under repetitive avalanche.

Electret-Free Micromachined Silicon Electrostatic Vibration Energy Harvester With the Bennet’s Doubler as Conditioning Circuit

Abstract: This letter presents for the first time experiments combining a previously reported microelectromechanical system electrostatic vibration energy harvester (e-VEH) and the Bennet’s doubler circuit. A self-limiting effect on the harvested power, which was not reported before on macroscopic e-VEHs, has been observed. This effect is due to the nonlinear dynamics of the system and to the self-increase of the electromechanical damping that is typical for e-VEHs. With a few volts of initial precharge, the Bennet’s doubler progressively increases the voltage across the transducer’s terminals up to 23 V, where saturation occurs. A power of 2.3 $\mu $ W is available for a load, when the harvester is excited by 1.5 g at 150 Hz of external acceleration.

High-Performance Temperature Sensor Based on 4H-SiC Schottky Diodes

Abstract: A high-performance temperature sensor based on coupled 4H-SiC Schottky diodes is presented. The linear dependence on temperature of the difference between the forward voltages appearing on two diodes biased at different constant currents, in a range from 30 °C up to 300 °C, was used for temperature sensing. A high sensitivity of 5.11 mV/°C was measured. This is, to the best of our knowledge, the first experimental result about a proportional-to-absolute-temperature sensor made with SiC diodes, showing both a good degree of linearity and long-term stability performance.