Showing papers in "IEEE Electron Device Letters in 2016"

3.8-MV/cm Breakdown Strength of MOVPE-Grown Sn-Doped $\beta $ -Ga 2 O 3 MOSFETs

Abstract: A Sn-doped (100) $\beta $ -Ga2O3 epitaxial layer was grown via metal–organic vapor phase epitaxy onto a single-crystal, Mg-doped semi-insulating (100) $\beta $ -Ga2O3 substrate. Ga2O3-based metal–oxide–semiconductor field-effect transistors with a 2- $\mu \text{m}$ gate length ( $L_{G})$ , 3.4- $\mu \text{m}$ source–drain spacing ( $L_{\textrm {SD}})$ , and 0.6- $\mu \text{m}$ gate–drain spacing ( $L_{\textrm {GD}})$ were fabricated and characterized. Devices were observed to hold a gate-to-drain voltage of 230 V in the OFF-state. The gate-to-drain electric field corresponds to 3.8 MV/cm, which is the highest reported for any transistor and surpassing bulk GaN and SiC theoretical limits. Further performance projections are made based on layout, process, and material optimizations to be considered in future iterations.

Field-Plated Ga 2 O 3 MOSFETs With a Breakdown Voltage of Over 750 V

Abstract: Depletion-mode field-plated Ga2O3 metal–oxide–semiconductor field-effect transistors were demonstrated for the first time. Substantial enhancement in breakdown voltage was achieved with a gate-connected field plate. The device channels, formed by selective-area Si ion implantation doping of an undoped Ga2O3 epilayer, were electrically isolated by the highly resistive epilayer without mesa etching. Effective surface passivation and high Ga2O3 material quality contributed to the absence of drain current collapse. The transistors exhibited an off-state breakdown voltage of 755 V, a high drain current on/off ratio of over $10^{9}$ , and stable high temperature operation against 300°C thermal stress.

Improved Synaptic Behavior Under Identical Pulses Using AlO x /HfO 2 Bilayer RRAM Array for Neuromorphic Systems

Abstract: We analyze the response of identical pulses on a filamentary resistive memory (RRAM) to implement the synapse function in neuromorphic systems. Our findings show that the multilevel states of conductance are achieved by varying the measurement conditions related to the formation and rupture of a conductive filament. Furthermore, abrupt set switching behavior in the RRAM leads to an unchanged conductance state, leading to degradation in the accuracy of pattern recognition. Thus, we demonstrate a linear potentiation (or depression) behavior of conductance under identical pulses using the effect of barrier layer on the switching, which was realized by fabricating an RRAM on top of an Al electrode. As a result, when the range of the conductance is symmetrically controlled at both polarities, a significantly improved accuracy is achieved for pattern recognition using a neural network with a multilayer perceptron.

Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

Abstract: We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length $L_{g}=100$ nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau–Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective $S$ -shaped ferroelectric charge–voltage characteristics that provides important insights into the device operation.

Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching

Abstract: We demonstrate a nearly hysteresis-free sub-60-mV/decade subthreshold swing (SS) operation in a p-type bulk metal–oxide–semiconductor field-effect transistor externally connected to a ferroelectric capacitor. The SS $\mu \text{m}\sim 10$ nA/ $\mu \text{m}$ of drain current) and at large drain current levels. However, the extent of hysteresis is found to be strongly dependent on the drain voltage. At high drain voltages, large hysteresis occurs, indicating the influence of drain voltage in the charge balance with the ferroelectric capacitor.

Why Is FE–HfO 2 More Suitable Than PZT or SBT for Scaled Nonvolatile 1-T Memory Cell? A Retention Perspective

Abstract: The limited retention time for single-transistor memory cell based on ferroelectric-gated field-effect-transistor (FeFET) has prevented the commercialization of its nonvolatile memory (NVM) option using the commercially available ferroelectric materials, such as strontium bismuth tantalite (SBT) or lead zirconium titanate (PZT), as the gate dielectric. However, the recent advent of the HfO2-based ferroelectric has demonstrated the strong possibility of meeting the NVM requirement of 10-year retention on aggressively scaled FeFETs. This letter will analyze why the retention for HfO2-based ferroelectric (FE–HfO2) is much longer than its PZT or SBT counterparts, based on the two major retention loss mechanisms: depolarization field and charge trapping.

TiO x -Based RRAM Synapse With 64-Levels of Conductance and Symmetric Conductance Change by Adopting a Hybrid Pulse Scheme for Neuromorphic Computing

Abstract: We propose TiO x -based resistive switching device for neuromorphic synapse applications This device is capable of 64-levels conductance states because of their optimized interface between the metal electrode and the TiO x film To compensate the change in switching power with increasing pulse number, we propose the use of fixed voltage and current pulses in potentiation and depression conditions, respectively By adopting a hybrid pulse scheme, the symmetry of conductance change under both potentiation and depression conditions is shown to be significantly improved Both the improved conductance levels and the symmetry of conductance change are directly related with enhanced pattern recognition accuracy, which is confirmed by a neural network simulation

1.7-kV and 0.55- $\text{m}\Omega \cdot \text {cm}^{2}$ GaN p-n Diodes on Bulk GaN Substrates With Avalanche Capability

Abstract: We report vertical GaN-on-GaN p-n diodes with a breakdown voltage (BV) of 1.7 kV and a low differential specific ON-resistance $R_{\mathrm{\scriptscriptstyle ON}}$ of 0.55 $\text{m}\Omega \cdot \text {cm}^{2}$ with current spreading considered (or 0.4 $\text{m}\Omega \cdot \text {cm}^{2}$ using the diode bottom mesa size), resulting in a figure-of-merit ( $V_{B}^{2}/R_{\mathrm{\scriptscriptstyle ON}})$ of 5.3 GW/cm2 (or 7.2 GW/cm $^{2})$ . These devices exhibit a current swing over 14 orders of magnitude and a low ideality factor of 1.3. Temperature dependent $I$ – $V$ measurements show that the BV increases with increasing temperature, a signature of avalanche breakdown.

Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors

Abstract: We present a SPICE model for ferroelectric transistors (FEFETs) based on time-dependent Landau–Khalatnikov equation solved self-consistently with the transistor equations. The model also considers depolarization fields due to non-ideal contacts. We experimentally characterize FE films to calibrate our model, based on which we analyze the device and circuit implications of FEFETs. We discuss the dependence of the ON current and gate capacitance of FEFETs on the FE thickness and FE material parameters. A ring oscillator analysis shows delay reduction up to 97% at iso-energy for FEFETs compared with MOSFETs at $V_{\mathrm{ DD}} V. FEFET-based SRAMs show 47%–68% larger read stability and 50%–57% lower access time, albeit with an increase in the write time.

Tunnel Field-Effect Transistor With an L-Shaped Gate

Abstract: In this letter, a new L-shaped gate tunnel field-effect transistor (LG-TFET) is proposed and investigated by Silvaco Atlas simulation. The tunneling junction in the LG-TFET is perpendicular to the channel direction that facilitates the implementation of a relatively large tunneling junction area. The channel is U-shaped that makes the channel mainly distribute in the vertical direction, reducing the device area. The n+ pocket design is also introduced between the source and the intrinsic regions to improve the device characteristic. In addition, the gate and n+ pocket region overlap both in the vertical and the lateral directions resulting in an enhanced electric field, and the ON-state current of the LG-TFET is increased up to $\sim 50$ % compared with the previous L-shaped channel TFET. The minimum subthreshold swing of the LG-TFET is 38.5 mV/decade at 0.2 V gate-to-source voltage. By using the L-shaped gate, U-shaped channel, and the insertion of n+ pocket, the overall performance of the LG-TFET is optimized.

Gate Reliability Investigation in Normally-Off p-Type-GaN Cap/AlGaN/GaN HEMTs Under Forward Bias Stress

Abstract: Gate reliability of normally-off p-type-GaN/AlGaN/GaN high-electron mobility transistors grown on Si substrate subjected to forward bias stress at different gate voltages and temperatures was analyzed. Stress-induced gate current degradation was found to be consistent with the percolation process. Obtained time-to-breakdown data were interpreted using the Weibull statistics, and the maximum allowed gate operating voltage was estimated. The gate degradation was found to be weakly dependent on temperature with an activation energy of 0.1 eV.

Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array

Abstract: Convolution is the key operation in the convolutional neural network, one of the most popular deep learning algorithms. The implementation of the convolution kernel on the resistive cross-point array is different than the implementation of the matrix-vector multiplication in prior works. In this letter, we propose a dimensional reduction of 2-D kernel matrix into 1-D column vector, i.e., a column of the array, and enable the parallel readout of multiple 2-D kernels simultaneously. As a proof-of-concept demonstration, we use the Prewitt kernels to detect both horizontal and vertical edges of the $20 \times 20$ pixels of black-and-white MNIST handwritten digits. The experiments were performed on the fabricated $12 \times 12$ resistive cross-point array based on the Pt/HfO x /TiN structure. The experimental results of the Prewitt kernel operation perfectly matches the simulation results, indicating the feasibility of the proposed implementation methodology of the convolution kernel on resistive cross-point array.

Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory

Abstract: In this letter, we propose a layer selection method by permutations (LSMPs) of string select line (SSL) bias and string select transistor with multi-level states. Due to the increased number of threshold voltage orderings by the permutation, the number of required SSLs for the layer selection and the space occupied by SSLs can be minimized. Also, the operation scheme for the layer selection is discussed. To verify the operation of proposed LSMP, a fabricated pseudo-LSM is measured. As a result, it is clearly revealed that the number of selectable layer can be increased drastically by the LSMP.

First-Principles Study of Sulfur Dioxide Sensor Based on Phosphorenes

Abstract: The adsorption behaviors of sulfur dioxide (SO2) gas molecule over pristine, boron-, silicon-, sulfur-, and nitrogen-doped phosphorenes are theoretically studied using first-principles approach based on density-functional theory. The adsorption energy ( $E_{a}$ ), adsorption distance ( $d$ ), and Mulliken charge ( $Q$ ) of SO2 molecules adsorbed on the different phosphorenes are calculated. The simulation results demonstrate that pristine phosphorene is sensitive to SO2 gas molecule with a moderate adsorption energy and an excellent charge transfer, while evidence of negative effect is observed during doping with S and N. We also observe that B- or Si-doped phosphorene exhibits extremely high reactivity toward SO2 with a stronger adsorption energy, indicating that they are not suitable for use as SO2 sensors, but have potential applications in the development of metal-free catalysts for SO2. Therefore, we suggest that pristine phosphorene could be an excellent candidate as sensor for the polluting gas SO2.

An Experimental Demonstration of GaN CMOS Technology

Abstract: This letter reports the first demonstration of gallium nitride (GaN) complementary metal–oxide–semi-conductor (CMOS) field-effect-transistor technology. Selective area epitaxy was employed to have both GaN N-channel MOSFET (NMOS) and P-channel MOSFET (PMOS) structures on the same wafer. An AlN/SiN dielectric stack grown by metal–organic chemical vapor deposition served as the gate oxide for both NMOS and PMOS, yielding enhancement-mode N- and P-channel with the electron mobility of 300 cm2/V-s and hole mobility of 20 cm2/V-s, respectively. Using the GaN CMOS technology, a functional inverter integrated circuit was fabricated and characterized.

600 V/ $1.7~\Omega$ Normally-Off GaN Vertical Trench Metal–Oxide–Semiconductor Field-Effect Transistor

Abstract: This letter reports a GaN vertical trench metal–oxide–semiconductor field-effect transistor (MOSFET) with normally-off operation. Selective area regrowth of n+-GaN source layer was performed to avoid plasma etch damage to the p-GaN body contact region. A metal-organic-chemical-vapor-deposition (MOCVD) grown AlN/SiN dielectric stack was employed as the gate “oxide”. This unique process yielded a 0.5-mm2-active-area transistor with threshold voltage of 4.8 V, blocking voltage of 600 V at gate bias of 0 V, and on-resistance of $1.7~\Omega $ at gate bias of 10 V.

Negative Bias-Induced Threshold Voltage Instability in GaN-on-Si Power HEMTs

Abstract: This letter reports an in-depth study of the negative threshold voltage instability in GaN-on-Si metal-insulator–semiconductor high electron mobility transistors with partially recessed AlGaN. Based on a set of stress/recovery experiments carried out at several temperatures, we demonstrate that: 1) operation at high temperatures and negative gate bias (−10 V) may induce a significant negative threshold voltage shift, that is well correlated to a decrease in on -resistance; 2) this process has time constants in the range between 10–100 s, and is accelerated by temperature, with activation energy equal to 0.37 eV; and 3) the shift in threshold voltage is recoverable, with logarithmic kinetics. The negative shift in threshold voltage is ascribed to the depletion of trap states located at the SiN/AlGaN interface and/or in the gate insulator.

Very Low-Programming-Current RRAM With Self-Rectifying Characteristics

Abstract: To resolve the sneak leakage problem and reduce the power consumption in crossbar RRAM arrays, a Cu/Al2O3/aSi/Ta cell with self-rectifying characteristics is developed. The cell exhibits low operating current ( $\sim $ nA), high ON/OFF ratios ( $> 100\times $ ), and pronounced nonlinearity. The use of low-programming-current RRAM elements avoids the current-driving capability bottleneck of selectors, while the integrated rectifying layer improves the RRAM operation reliability. Endurance of over 500 cycles with $\sim 100$ ON/OFF ratio was achieved without external current compliance. Even at such low programming levels, retention over $10^{4}$ s at 100 °C can still be obtained.

Al2O3/ $\beta $ -Ga2O3(-201) Interface Improvement Through Piranha Pretreatment and Postdeposition Annealing

Abstract: In this letter, we report on the improvement of atomic layer deposited (ALD) Al2O3/ $\beta $ –Ga2O3 (-201) interface quality through piranha pretreatment and postdeposition annealing (PDA). The high quality interface is verified via the temperature dependent capacitance–voltage ( $C$ – $V$ ) and photo-assisted (deep UV) $C$ – $V$ measurements, considering its ultra wide bandgap of 4.8 eV for $\beta $ -Ga2O3. A low $C$ – $V$ hysteresis of 0.1 V from the measurement frequency of 1 kHz to 1 MHz is obtained, compared with the hysteresis of 0.45 V without piranha optimization. An average interface trap density $({\mathrm{ D}}_{\mathrm {it}})$ of $2.3 \times 10^{11}$ cm $^{\mathrm {-2}}\cdot $ eV $^{\mathrm {-1}}$ is extracted from the photo $C$ – $V$ measurements. Piranha pretreatments and PDA turn out to be an effective way to improve the ALD Al2O3/ $\beta $ –Ga2O3 (-201) interface for future high quality Ga2O3 metal–oxide–semiconductor field-effect transistors.

2.07-kV AlGaN/GaN Schottky Barrier Diodes on Silicon With High Baliga’s Figure-of-Merit

Abstract: In this letter, we demonstrate high-performance AlGaN/GaN Schottky barrier diodes (SBDs) on Si substrate with a recessed-anode structure for reduced turn-on voltage $V_{\mathrm {ON}}$ . The impact of the surface roughness after the recessed-anode formation on device characteristics is investigated. An improved surface condition can reduce the leakage current and enhance the breakdown voltage simultaneously. A low turn-on voltage of only 0.73 V can be obtained with a 50-nm recess depth. In addition, the different lengths of Schottky extension acting like a field plate are investigated. A high reverse breakdown voltage of 2070 V and a low specific ON-resistance of 3.8 $\text{m}\Omega \cdot \textrm {cm}^{2}$ yield an excellent Baliga’s figure of merit of 1127 MW/cm2, which can be attributed to the low surface roughness of only 0.6 nm and also a proper Schottky extension of 2 $\mu \text{m}$ to alleviate the peak electric field intensity in the SBDs.

Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) Using a Single Ohmic/Schottky Process Scheme

Abstract: This letter reports a new 900 V 4H-SiC JBSFET containing an MOSFET with an integrated JBS diode in the center area of the chip. Both MOSFET and JBS diode structures utilize the same edge termination structure,which results in 30% reduction in SiC wafer area consumption in case of 10 A rating device. In order to form a Schottky contact for the JBS diode as well as ohmic contacts for n+ source and p+ body of the MOSFET,a simple metal process flow has been newly developed. It was found that Ni can simultaneously form ohmic contacts on n+ and p+ implanted regions while it remains a Schottky contact on the n-epitaxial drift layer when it is annealed at moderate temperature (900°C for 2 min). The proposed JBSFET was successfully fabricated using a nine-mask on 6-in 4H-SiC wafers.

7.6 V Threshold Voltage High-Performance Normally-Off Al 2 O 3 /GaN MOSFET Achieved by Interface Charge Engineering

Abstract: An efficient approach to engineering the Al2O3/GaN positive interface fixed charges by post-dielectric annealing in nitrogen is demonstrated. The remarkable reduction of interface fixed charges from $1.44 \times 10^{13}$ to $3 \times 10^{12}$ cm−2 was observed, which leads to a record high threshold voltage ( $V_{\mathrm{ TH}})$ of 7.6 V obtained in the Al2O3/GaN MOSFETs. The significantly reduced interface fixed charges and the corresponding remote scattering effect enable respectable improvement in the electron mobility that results in a high drain current density of 355 mA/mm in the device. These competitive results reveal that the method reported in this letter is promising in pushing $V_{\mathrm{ TH}}$ more positive and simultaneously achieving good device performance of normally-off GaN power devices.

Volatile and Non-Volatile Switching in Cu-SiO 2 Programmable Metallization Cells

Abstract: In this letter, we propose a CMOS-compatible selector prototype based on a Cu-SiO2 programmable metallization cell. With a porous e-beam evaporated SiO2 switching layer, the filament ruptures in less than a millisecond. The device exhibits diode-like $I$ – $V$ characteristics with a selectivity of more than $10^{7}$ . This volatile PMC can be changed to a bipolar resistive memory switch if the SiO2 switching layer is thermally doped with Cu. Threshold switching is a result of filament dissolution caused by Cu diffusion in SiO2.

Fully Vertical GaN p-i-n Diodes Using GaN-on-Si Epilayers

Abstract: Using GaN-on-Si epilayers, for the first time, fully vertical p-i-n diodes are demonstrated after Si substrate removal, transfer, and n-electrode formation at the top of the device. After SiO2 sidewall passivation, the vertical p-i-n diodes, with n-GaN facing up, exhibit $V_{{\mathrm{\scriptscriptstyle ON}}}$ of 3.35 V at 1 A/cm2, a low differential on-resistance of 3.3 $\text{m}\Omega $ cm2 at 300 A/cm2, and a breakdown voltage of 350 V. The corresponding Baliga's figure of merit is 37.0 MW/cm2, a very good value for GaN-based p-i-n rectifiers grown on Si substrates. The results indicate that fully vertical rectifiers using GaN-on-Si epilayers have great potential in achieving cost-effective GaN devices for high-power and high-voltage applications.

A Broadside-Coupled Meander-Line Resonator in 0.13- $\mu \text{m}$ SiGe Technology for Millimeter-Wave Application

Abstract: An on-chip resonator is designed and fabricated using a standard 0.13- $\mu \text{m}$ SiGe technology for millimeter-wave applications. The designed resonator is based on a unique structure, which consists of two broadside-coupled meander lines with opposite orientation. The equivalent $LC$ circuit of the resonator is given, while the impact of the structure on the resonance frequencies is investigated. Using this structure along with capacitors, a compact bandpass filter (BPF) is also designed and fabricated. The measured results show that the resonator can generate a resonance at 57 GHz with the attenuation better than 13.7 dB, while the BPF has a center frequency at 31 GHz and a insertion loss of 2.4 dB. The chip size of both the resonator and the BPF, excluding the pads, is only 0.024 mm2 ( $0.09 \times 0.27$ mm $^{2})$ .

Interface State Density in Atomic Layer Deposited SiO 2 / $\beta $ -Ga 2 O 3 ( $\bar {2}01$ ) MOSCAPs

Abstract: The interface state density ( $D_{\mathrm{ it}})$ at the interface between $\beta $ -Ga2O3 ( $\bar {2}01$ ) and atomic layer deposited (ALD) SiO2 dielectric is extracted using Terman method and conductance method. The effect of the different surface treatments on the extracted $D_{\mathrm{ it}}$ was also studied. It is observed that the extracted $D_{\mathrm{ it}}$ of $6\times 10^{11}$ cm $^{-2}$ eV $^{-1}$ for the sample with no surface treatment is lower than hydrofluoric and hydrochloric acid treated samples. Low $D_{\mathrm{ it}}$ sample shows narrow peak in the conductance method, suggesting a smooth interface. The extracted low $D_{\mathrm{ it}}$ makes ALD SiO2 an attractive candidate for future Ga2O3 power devices.

High Uniformity Normally-OFF GaN MIS-HEMTs Fabricated on Ultra-Thin-Barrier AlGaN/GaN Heterostructure

Abstract: Ultra-thin-barrier (UTB) AlGaN/GaN heterostructure is utilized for fabrication of normally-OFF GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs). The sheet resistance of 2-D electron gas in the UTB Al0.22Ga0.78N(5-nm)/GaN heterostructure is effectively reduced by SiNx passivation grown by low-pressure chemical vapor deposition, from 2570 to $334~\Omega $ /□. The fabricated Al2O3/AlGaN/GaN MIS-HEMTs exhibit normally-OFF behavior with good $V_{\mathrm {TH}}$ uniformity and low $V_{\mathrm {TH}}$ -hysteresis. 20 mm-gate-width power devices featuring a low $R_{\sc {\mathrm{ on}}}$ of $0.75~\Omega $ ( $\text{I}_{\mathrm {D,MAX}} =6.5$ A) are also demonstrated on the platform.

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

Abstract: A comprehensive analysis of the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was carried out. In particular, two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared. The GIDL current of the JM-FET was considerably smaller than that of the IM-FET, and the reason for the difference was consequently determined by numerical simulations. It was found that the source of the difference between the IM-FET and JM-FET was the difference in source/drain (S/D) doping concentration, where the depletion width becomes the tunneling width, considering a long extension length at the S/D regions. The experimental results showed that the GIDL current of the NW FET was significantly controlled by longitudinal band-to-band tunneling (BTBT), rather than the transverse BTBT, as had been reported in the previous literature.

Silicon-Based Floating-Body Synaptic Transistor With Frequency-Dependent Short- and Long-Term Memories

Abstract: A new synaptic transistor was fabricated with two separated gates based on a FinFET structure in order to mimic short- and long-term memories in a biological synapse and connect with a postsynaptic neuron circuit directly. The transition between short- and long-term memories occurred after applying repetitive input pulses and strongly depended upon intervals between input pulses. These findings indicate that it has very similar learning characteristics with a biological synapse and the possibility as a synaptic device in neuromorphic systems.

Low ON-Resistance SiC Trench/Planar MOSFET With Reduced OFF-State Oxide Field and Low Gate Charges

Abstract: We propose a SiC trench/planar MOSFET (TP-MOS) which features a trench channel and a planar channel in one half-cell. Numerical simulations with Sentaurus TCAD have been carried out to study the proposed device architecture. Compared with traditional planar MOSFET (P-MOS), the TP-MOS has a much lower ${R} _{\mathrm {ON}}$ owing to the increased channel density. Unlike traditional trench MOSFET (T-MOS) which enables a higher channel density at the price of a high bottom-oxide field in the high-voltage OFF-state, the TP-MOS features bottom p-bases as in the P-MOS that protect the gate oxide from high electric field. The OFF-state oxide field in the TP-MOS is found to be even lower than the P-MOS. In addition, the TP-MOS boasts a low feedback capacitance ( ${C} _{\mathrm {rss}})$ and gate-to-drain charge ( ${Q} _{\mathrm {GD}})$ , since the coupling between the gate and the drain is suppressed by the collective effects of the top p-bases and the bottom p-bases. The ${Q} _{\mathrm {G}}$ of the TP-MOS is nearly the same as the P-MOS, and is much smaller than the T-MOS. Superior figures of merit ( ${Q} _{\mathrm {G}}\times {R} _{\mathrm {ON}}$ and ${Q} _{\mathrm {GD}}\times {R} _{\mathrm {ON}})$ are achieved in the TP-MOS.