Showing papers in "IEEE Electron Device Letters in 2020"
TL;DR: In this paper, field-plated vertical Ga2O3 trench Schottky barrier diodes (SBDs) were employed to achieve a 2.89 kV breakdown voltage, which is 500 V higher than those without field plate.
Abstract: We report the realization of field-plated vertical Ga2O3 trench Schottky barrier diodes (SBDs). The trench SBDs show significantly lower leakage current than regular SBDs. With employment of field plate, a breakdown voltage (BV) of 2.89 kV is achieved, which is ~ 500 V higher than those without field plate. Trench sidewall depletion is observed, and the average depletion width is extracted using an analytical model. The trench SBDs have a differential specific on-resistance ( $\text {R}_{\text {on,sp}}$ ) of 10.5 (8.8) $\text{m}\Omega ~\cdot {\mathrm {cm}}^{\text {2}}$ from DC (pulsed) measurements, which leads to a Baliga’s figure-of-merit ( ${\mathrm {BV}}^{{2}}/\text {R}_{\text {on,sp}}$ ) of 0.80 (0.95) GW/cm2— the highest among Ga2O3 power devices to date.
156 citations
TL;DR: This letter reports the polymer passivation of field plated lateral MOSFETs with significant improvement in the breakdown voltages as compared to non-passivated devices.
Abstract: This letter reports the polymer passivation of field plated lateral $\beta $ -Ga2 O3 MOSFETs with significant improvement in the breakdown voltages as compared to non-passivated devices. We show consistent results of higher breakdown voltages in passivated devices as compared to non-passivated devices for MOSFETs with $\text{L}_{\textit {gd}}$ ranging from $30~\mu \text{m}$ to $70~\mu \text{m}$ and across two process runs. We obtain a record high breakdown voltage of 6.72 kV for a MOSFET with $\text{L}_{\textit {gd}}= {40}\mu \text{m}$ giving an average field strength of 1.69 MVcm−1. The peak drain current is $\sim ~3$ mA/mm for $\text{L}_{g}= {2}\mu \text{m}$ device with a gate source separation of $3~\mu \text{m}$ . The on-resistance for the device is, $\text{R}_{\textit {on}}= {13}\,\,\text{k}\Omega ^{.}$ mm, giving a power device Figure of Merit of 7.73 kWcm−2. The $\text{R}_{\textit {on}}$ is high due to plasma induced damage of channel and access regions. The $\text{R}_{\textit {on}}$ and on-current density remain unchanged after passivation. The breakdown increases with $\text{L}_{\textit {gd}}$ up to 70 $\mu \text{m}$ , giving a maximum breakdown voltage of 8.03 kV.
149 citations
TL;DR: In this paper, high performance NiO/β $ -Ga2O3 heterojunction pn diodes were realized by applying a sputtered p-type NiO film onto a lightly doped n-type Ga2O-3 epitaxial layer.
Abstract: High performance NiO/ $\beta $ -Ga2O3 heterojunction pn diodes were realized by applying a sputtered p-type NiO film onto a lightly doped n-type $\beta $ -Ga2O3 epitaxial layer. Taking advantage of the high barrier height against carriers within the pn heterojunction, the demonstrated device exhibited a high breakdown voltage ( ${V}_{B}{)}$ of 1059 V without optimized electric field management techniques, and before breakdown the reverse leakage current density remained below $1~\mu \text{A}$ /cm2. Simultaneously, a relatively low specific on-resistance ( $R_{\text {on, sp}}{)}$ of 3.5 $\text{m}\Omega \cdot \text {cm}^{{2}}$ was achieved. The built-in potential of the heterojunction that determined by a capacitance-voltage ( ${C}$ - ${V}$ ) measurement was around 2.4 eV. As discussed in terms of the energy band diagram of a type-II heterojunction, the conduction band and valence band offsets at the NiO/ $\beta $ -Ga2O3 hetero-interface were estimated to be 1.2 and 2.3 eV, respectively.
105 citations
TL;DR: In this article, a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures was derived.
Abstract: This letter reports a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures. Below a critical temperature, the derived limit saturates to a value that is independent of temperature and proportional to the characteristic decay of a band tail. The proposed expression tends to the Boltzmann limit when the decay of the band tail tends to zero. Since the saturation is universally observed in different types of MOSFETs (regardless of dimension or semiconductor material), this suggests that an intrinsic mechanism is responsible for the band tail.
84 citations
TL;DR: High-performance lateral D-mode MOSFETs with state-of-art power figure- of-merit (P-FOM) and breakdown voltage (BV) and specific ON-resistance show a great potential for future power electronic applications.
Abstract: In this work, we have demonstrated high-performance lateral $\beta $ -Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) with state-of-art power figure-of-merit (P-FOM) and breakdown voltage (BV) by adopting a T-shape gate field-plate and source connected field-plate structures. Depletion-mode (D-mode) $\beta $ -Ga2O3 MOSFETs with gate-to-drain distance ( $\text{L}_{\sf GD}$ ) of $4.8~\mu \text{m}$ /17.8 $\mu \text{m}$ demonstrate a BV of 1.4 kV/2.9 kV and specific ON-resistance ( $\text{R}_{ \mathrm{\scriptscriptstyle ON}, {\sf sp}}$ ) of 7.08 $\text{m}\Omega \cdot $ cm2/46.2 $\text{m}\Omega \cdot $ cm2, respectively, yielding a high P-FOM of 277 MW/cm2 and averaged electrical field of 2.9 MV/cm for the device with $\text{L}_{\sf GD} = {\sf 4.8}\,\, \mu \text{m}$ . To the best of all the authors’ knowledge, this P-FOM of 277 MW/cm2 and BV = 2.9 kV are the highest values among all the lateral D-mode $\beta $ -Ga2O3 MOSFETs. Combined with negligible gate pulsed and drain pulsed current collapse and drain current on/off ratio of 109, these $\beta $ -Ga2O3 MOSFETs show a great potential for future power electronic applications.
81 citations
TL;DR: These devices show forming-free RS behaviors with high speed, uniform resistance distribution, large on/off ratio, and good retention, and temperature stability with record high endurance from cryogenic to high-temperature.
Abstract: Through oxygen profile engineering, we fabricated W/AlO $_{\mathbf {x}}$ /Al $_{\mathbf {{2}}}~\text{O}_{\mathbf {{3}}}$ /Pt bilayer memristors with a 250-nm feature size. The AlO $_{{\mathbf {x}}}$ fabricated by sputtering serves as an oxygen vacancy source, whereas the Al $_{{\mathbf {{2}}}}~\text{O}_{{\mathbf {{3}}}}$ deposited by atomic layer deposition acts as a dominant resistive switching (RS) layer. Our devices show forming-free RS behaviors with high speed (28 ns), uniform resistance distribution, large on/off ratio ( $\sim 10^{{\mathbf {{3}}}}$ @100K, $\sim 10^{{\mathbf {{3}}}}$ @298K, and $\sim 80$ @400K), and good retention. Besides, temperature stability with record high endurance from cryogenic to high-temperature ( $10^{{\mathbf {{8}}}}$ @100K, $10^{{\mathbf {{10}}}}$ @298K, and $10^{{\mathbf {{7}}}}$ @400K) is demonstrated, to the best of our knowledge.
63 citations
TL;DR: In this article, a complementary logic circuit (an inverter) on a GaN-on-Si platform without the use of regrowth technology is presented, which yields a record maximum voltage gain of ~27 V/V at an input voltage of 0.59 V with
Abstract: This paper demonstrates a complementary logic circuit (an inverter) on a GaN-on-Si platform without the use of regrowth technology. Both n-channel and p-channel GaN transistors are monolithically integrated on a GaN/AlGaN/GaN double heterostructure. N-channel FETs show enhancement-mode (E-mode) operation with a threshold voltage around 0.2 V, ON- OFF current ratio of 107 and RON of $6~\Omega \cdot \text {mm}$ , while the p-channel FETs show E-mode operation with Vth of −1 V, ON- OFF current ratio of 104 and RON of 2.3 $\text{k}\Omega \cdot \text {mm}$ . Complementary logic inverters fabricated with this technology yield a record maximum voltage gain of ~27 V/V at an input voltage of 0.59 V with $\text{V}_{\text {DD}}={5}$ V. Excellent transfer characteristics have been obtained up to 300 °C operating temperatures, which demonstrates the suitability of this technology for low-power high-temperature electronic applications.
62 citations
TL;DR: In this article, a 40nm-thick ex-situ silicon nitride passivation layer was added to nitrogen-polar gallium nitride (GNT) transistors to improve the dispersion control.
Abstract: This letter reports on the improvement of the large-signal W-band power performance of nitrogen-polar gallium nitride deep recess high electron mobility transistors with the addition of a 40-nm-thick ex-situ silicon nitride passivation layer deposited by plasma enhanced chemical vapor deposition. The additional passivation improves the dispersion control allowing the device to be operated at higher voltages. Continuous-wave load pull measurements performed at 94 GHz on a $2\times 37.5\,\,\mu \text{m}$ transistor demonstrated an improvement in the peak power-added efficiency (PAE) to 30.2% with an associated output power density of 7.2 W/mm at 20 V drain bias. Furthermore, at 23 V, a new record-high W-band power density of 8.84 W/mm (663 mW) was achieved with an associated PAE of 27.0%.
60 citations
TL;DR: In this work, fast sweeping characterization with an extremely short relaxation time was used to probe the instability of p-GaN gate HEMTs, finding a very fast shifting process but a slower recovering process that should be high enough to avoid HEMT faulty turn-on.
Abstract: In this work, fast sweeping characterization with an extremely short relaxation time was used to probe the ${V}_{\text {TH}}$ instability of p-GaN gate HEMTs. As the ${I}_{\text {D}}$ - ${V}_{\text {G}}$ sweeping time deceases from 5 ms to $5~\mu \text{s}$ , the ${V}_{\text {TH}}$ dramatically degenerates from 3.13 V to 1.76 V, meanwhile the hysteresis deteriorates from 22.6 mV to 1.37 V. Positive bias temperature instability (PBTI) measurement by fast sweeping shows the ${V}_{\text {TH}}$ features a very fast shifting process but a slower recovering process. D-mode HEMTs counterpart without Mg contamination demonstrates a negligible ${V}_{\text {TH}}$ shift and hysteresis, proving the ${V}_{\text {TH}}$ instability is probably due to the ionization of acceptor-like traps in the p-GaN depletion region. Finally, the ${V}_{\text {TH}}$ instability is verified by a GaN circuit under switching stress. The ${V}_{\text {TH}}$ instability under different sweeping speed uncovers the fact that the high ${V}_{\text {TH}}$ by conventionally slow DC measurements is probably artificial. The DC ${V}_{\text {TH}}$ should be high enough to avoid HEMT faulty turn-on.
57 citations
TL;DR: In this article, the authors demonstrate the high-frequency and high-power performance of GaN high electron mobility transistors (HEMTs) on Si substrates using InAlN/GaN HEMTs with a gate length of 55 nm and a source-drain spacing of 175 nm.
Abstract: This work demonstrates the high-frequency and high-power performance capacity of GaN high electron mobility transistors (HEMTs) on Si substrates. Using a T-gate and ${n}^{++}$ -GaN source/drain contacts, the InAlN/GaN HEMT with a gate length of 55 nm and a source-drain spacing of 175 nm shows a maximum drain current ${I}_{{D,MAX}}$ of 2.8 A/mm and a peak transconductance ${g}_{m}$ of 0.66 S/mm. The same HEMT exhibits a forward-current-gain cutoff frequency ${f}_{T}$ of 250 GHz and a maximum frequency of oscillation ${f}_{{MAX}}$ of 204 GHz. The ${I}_{{D,MAX}}$ , peak ${g}_{m}$ and ${f}_{T} -{f}_{{MAX}}$ product are among the best reported for GaN HEMTs on Si, which are very close to the state-of-the-art depletion-mode GaN HEMTs on SiC without a back barrier. Given the low cost of Si and the high compatibility with CMOS circuits, GaN HEMTs on Si prove to be particularly attractive for cost-sensitive applications.
57 citations
TL;DR: In this article, the authors systematically investigated the tradeoff of the annealing process on the Hf0.5Zr 0.5O2/Si interface properties of ferroelectric FETs.
Abstract: Crystallization annealing is a key process for the formation of the ferroelectric phase in HfO2-based ferroelectric thin films. In this study, we systematically investigate the notable tradeoff of the annealing process, with temperature varied from 300°C to 700°C, on the Hf0.5Zr0.5O2/Si interface properties of ferroelectric FETs. While high-temperature annealing leads to improved ferroelectricity, it results in the unintentional formation of an interfacial layer and the increased interface state density. Ferroelectric FETs prepared with high annealing temperature consequently show degraded subthreshold swing, decreased memory window, and increased OFF current. Our results suggest that annealing ferroelectric FETs at temperature as low as possible for sufficient ferroelectricity, which is 400°C in this study, is an effective approach to improve the device performance of Hf0.5Zr0.5O2 ferroelectric FETs.
TL;DR: In this article, a two-terminal 2D MoS2-based memristive device was used to emulate an artificial neuron and the leaky integrate-and-fire neuron implemented with this device successfully emulates the key characteristics of a biological neuron.
Abstract: In this work, we use a two-terminal 2D MoS2-based memristive device to emulate an artificial neuron. The Au/MoS2/Ag device exhibits volatile resistance switching characteristics with a low threshold voltage and a high ON-OFF ratio of 106, originating from an Ag diffusion-based filamentary process. The leaky integrate-and-fire neuron implemented with this device successfully emulates the key characteristics of a biological neuron.
TL;DR: In this article, post-failure cell inspections demonstrate that its main cause is the crack at the SiO2 dielectric layer with melted source aluminum inside, and an electro-thermal-mechanical simulation is performed to reproduce the failure transition.
Abstract: The unique gate failure mode of SiC MOSFETs is often identified but has not been fully understood yet. In this letter, post-failure cell inspections demonstrate that its main cause is the crack at the SiO2 dielectric layer with melted source aluminum inside. An electro-thermal-mechanical simulation is performed to reproduce the failure transition, and it reveals that the crack forms at an early stage. This new failure mechanism further enlightens on the vulnerability of the vertical power MOSFET structure in extremely high-temperature operation.
TL;DR: In this paper, an enhancement-mode (E-mode) vertical Ga2O3 field effect transistors with a current aperture was developed on a single-crystal $β $ -GaO3 (001) substrate.
Abstract: Enhancement-mode (E-mode) vertical $\beta $ -Ga2O3 metal–oxide–semiconductor (MOS) field-effect transistors featuring a current aperture were developed on a single-crystal $\beta $ -Ga2O3 (001) substrate. Nitrogen ions were implanted into a drift layer grown by halide vapor phase epitaxy to form current blocking layers (CBLs) for vertical source–drain isolation, while Si ions were implanted to form degenerately doped source contact regions and a top-gated lateral channel that was fully depleted at 0-V gate bias. The devices delivered a high output current on/off ratio of $2\times {10}^{{7}}$ despite a nonideal MOS interface that limited the maximum drain current density to <0.1 kA/cm2. Pulsed operation without current collapse under off-state voltage stress was demonstrated. Hard breakdown occurred prematurely owing to leakage through the CBLs, but is expected to improve with an optimized nitrogen implantation process. The realization of E-mode vertical Ga2O3 transistors based on a manufacturable all-ion-implanted process represents an important step toward practical applications of Ga2O3 power electronics.
TL;DR: In this article, a gallium arsenide (GaAs)-based on-chip broadband bandpass filter (BPF) is proposed based on slotted half-mode substrate integrated waveguide (HMSIW) spoof surface plasmon polaritons (SSPPs).
Abstract: A gallium arsenide (GaAs)-based millimeter-wave broadband bandpass filter (BPF) is proposed based on slotted half-mode substrate integrated waveguide (HMSIW) spoof surface plasmon polaritons (SSPPs) The center frequency and bandwidth of this SSPP-based on-chip BPF can be easily controlled by tuning the geometry dimensions of the SSPP unit cell, which is attributed to its unique dispersion characteristics For demonstration, a prototype of the proposed BPF is fabricated and experimentally characterized, with good agreement between the simulated and measured results Due to the ability of the strong electric field confinement, the proposed on-chip SSPP structure has lower coupling feature with closely-spaced transmission line circuits than its counterpart traditional HMSIW structure
TL;DR: A Pt/Ag/TiN/HfAlOx/Pt (PATHP) device with excellent TS characteristics, including a large selectivity (1010), a wide range of operation current from 10 nA to 1 mA, an extremely steep slope (0.63 mV/dec) and fast turn-on speed (50 ns).
Abstract: Threshold switching (TS) devices are promising candidates to build highly compact and energy efficient artificial neurons Here, we present a Pt/Ag/TiN/HfAlOx/Pt (PATHP) device with excellent TS characteristics, including a large selectivity(1010), a wide range of operation current from 10 nA to 1 mA, an extremely steep slope (063 mV/dec) and fast turn-on speed (50 ns) The stable TS performance can be ascribed to the introduction of TiN buffer layer and the alternate atomic layer deposited HfAlOx layer Further, we experimentally demonstrate the functions of leaky-integrate-and-fire neurons with low power feature based on a RC circuit and a single device, respectively, which are essential for constructing spiking neuromorphic systems
TL;DR: An enhancement-mode hydrogen-terminated diamond field effect transistor (FET) is realized by using a low work function gate material, namely, lanthanum hexaboride (LaB6) as discussed by the authors.
Abstract: An enhancement-mode hydrogen-terminated diamond field-effect transistor (FET) is realized by using a low work function gate material, namely, lanthanum hexaboride (LaB6). The reason for the enhancement mode should be that the electrons in the LaB6 layer flow into the two-dimensional hole gas (2DHG) channel and compensate the holes, such that the channel is shut down. The threshold voltages ( ${\mathrm {V}}_{\text {TH}}$ ) range from − 0.29 V to − 0.72 V with different gate lengths. The device with 2 $\mu \text{m}$ gate length shows a − 57.9 mA/mm maximum drain current density ( ${\mathrm {I}}_{\text {DSmax}}$ ) at ${\mathrm {V}}_{\text {GS}} =-$ 5 V. The on/off ratio is around 9 orders of magnitude, with a subthreshold swing of 130 mV. Effective mobility ( $\mu _{\text {eff}}$ ) as high as 195.4 cm2/ $\text{V}\cdot \text{s}$ is obtained from the device. This technique reveals undamaged 2 DHG characteristics, uncontaminated interface between LaB6 and aluminum gate metal, and a simple fabrication process, which will promote the development of enhancement diamond FETs.
TL;DR: In this paper, the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the Ferroelectric field effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations was investigated.
Abstract: This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.
TL;DR: In this article, a G-band traveling wave tube for wireless communications and airborne radars is described, which provides a saturation output power over 15 W and a saturation gain over 32 dB with a bandwidth of 7.6 GHz.
Abstract: The development of a G-band traveling wave tube for wireless communications and airborne radars is described. The maximum output power of this device is over 20 W. This device provides a saturation output power over 15 W and a saturation gain over 32 dB with a bandwidth of 7.6 GHz. A folded waveguide circuit with modified circular bends is utilized to eliminate the band-edge instability caused by the high beam voltage of 20 kV. A pencil beam of 50 mA with a transmission ratio over 95 % is realized, making the device capable of operating in continuous wave mode. Periodic permanent magnets are employed for compactness. Chemical vapor deposition diamond disc is used in the input and output RF windows to minimize the loss and voltage standing wave ratios of the traveling wave tube. The weight and the size of the device are 2 kg and 300 mm $\times70$ mm $\times70$ mm, respectively. The efficiency of the device is over 5 %.
TL;DR: In this paper, partial ferroelectric switching was confirmed at room temperature for both materials via the measured transverse piezoelectric coefficients (e31, f) of −1.3 C/m2 (down-switching) and −0.7 c/m 2 (up-switting) for Al0.68Sc0.32N and 0.64Sc 0.36N were measured at 120 K.
Abstract: Ferroelectric switching was studied in 20 nm thick Al0.68Sc0.32N and Al0.64Sc0.36N films (with ~4 nm surface oxides) on platinized silicon wafers by multiple electrical characterization methods. Positive up negative down (PUND) measurements were conducted using 100 $\mu \text{s}$ monopolar triangular waveform excitation. At room temperature, Al0.68Sc0.32N exhibited an apparent remanent polarization, $\text{P}_{\text {r}} = {140}\,\,\mu \text{C}$ /cm2 and a coercive field, $\text{E}_{\text {c}} = {6.5}$ MV/cm, while film leakage prevented quantitative measurement of the Al0.64Sc0.36N ferroelectric properties. Remanent polarizations of $75~\mu \text{C}$ /cm2 for Al0.68Sc0.32N and $25\mu \text{C}$ /cm2for Al0.64Sc0.36N were measured at 120 K. Partial ferroelectric switching was confirmed at room temperature for both materials via the measured transverse piezoelectric coefficients (e31, f) of −1.3 C/m2 (down-switching) and −0.3 C/m2 (up-switching) for Al0.68Sc0.32N, and −0.9 C/m2 (down-switching) and −0.7 C/m2 (up-switching) for Al0.64Sc0.36N.
Abstract: In this work, the deep-level transient spectroscopy (DLTS) is conducted to investigate the gate stack of the ${p}$ -GaN gate HEMT with Schottky gate contact. A metal/ ${p}$ -GaN/AlGaN/GaN heterojunction capacitor is prepared for the study. The DLTS characterization captures the transient capacitance change in the stack, from which the capacitance of the metal/ ${p}$ -GaN Schottky junction can be extracted. By proper selection of the rate window, the impacts of the hole insufficiency effect are avoided during trap states evaluation. Thus, the information of deep energy levels in the ${p}$ -GaN layer is revealed, which consists of an electron trap state with activation energy of 0.85 eV and a hole trap state with activation energy of 0.49 eV. The identification of these trap states in the ${p}$ -GaN layer provides a physical foundation for understanding the threshold voltage instability in Schottky-type ${p}$ -GaN gate power HEMTs.
TL;DR: For the first time, a leaky integrate-and-fire (LIF) neuron with both excitatory and inhibitory characteristics is demonstrated using a single MOSFET.
Abstract: For the first time, a leaky integrate-and-fire (LIF) neuron with both excitatory and inhibitory characteristics is demonstrated using a single MOSFET. No additional circuits such as comparator, reset circuit, or current-to-voltage converter as well as a membrane capacitor are needed, and thus the LIF neuron is realized with a footprint of 6 F2. Because of its gate terminal, neuron firing is selectively inhibited, which can improve the energy efficiency of the neuromorphic system by inducing sparse activity. Furthermore, the spiking property of the neuron can be controlled by the gate, which can provide additional room to enhance the classification accuracy.
TL;DR: In this article, the impact of read operation on the electrical properties of hafnium oxide-based ferroelectric field effect transistors (FeFETs) was investigated, and it was shown that a quasi-static read may induce a series of phenomena, including a severe underestimation of the memory window, undesirable loss of the stored state, increased variability and an apparent steep slope behavior with a subthreshold slope lower than 7 mV/decade.
Abstract: This letter investigates the impact of read operation on the electrical properties of hafnium oxide-based ferroelectric field-effect transistors (FeFETs). We report that a quasi-static read may induce a series of phenomena, including a severe underestimation of the memory window, undesirable loss of the stored state, i.e. destructive read, increased variability and an apparent steep-slope behavior with a subthreshold slope lower than 7 mV/decade, which are not present under a fast read. We explain the results with the time-voltage dependence for the ferroelectric switching. Based on this, we provide comprehensive yet essential guidelines for disturb-free write and read operations.
TL;DR: In this article, an oxygen plasma treatment (OPT) was deployed to the gated region where a relatively thick (i.e. 31 nm) GaN is retained without aggressive gate recess.
Abstract: Enhancement-mode (E-mode) buried ${p}$ -channel GaN metal-oxide-semiconductor field-effect-transistors ( ${p}$ -GaN-MOSFET’s) with threshold voltage ( ${V}_{\text {TH}}$ ) of −1.7 V, maximum ON-state current ( ${I}_{\text {ON}}$ ) of 6.1 mA/mm and ${I}_{\text {ON}}/{I}_{\text {OFF}}$ ratio of 107 are demonstrated on a standard ${p}$ -GaN/AlGaN/GaN-on-Si power HEMT substrate. An oxygen plasma treatment (OPT) was deployed to the gated ${p}$ -GaN region where a relatively thick (i.e. 31 nm) GaN is retained without aggressive gate recess. The OPT converts the top portion of the GaN layer to be free of holes so that only the bottom portion remains ${p}$ -type while being spatially separated from the etched GaN surface and gate-oxide/GaN interface. As a result, E-mode operation is enabled while a high-quality ${p}$ -channel is retained. Multi-energy fluorine ion implantation was implemented for planar isolation of GaN ${p}$ -channel FETs with mesa edges and sidewalls eliminated. Consequently, high ${I}_{\text {ON}}/{I}_{\text {OFF}}$ ratio is obtained.
TL;DR: A quasi-vertical GaN Schottky barrier diode (SBD) fabricated on a hetero-epitaxial layer on silicon with low dislocation density and high carrier mobility is reported in this paper.
Abstract: In this letter, we report a quasi-vertical GaN Schottky barrier diode (SBD) fabricated on a hetero-epitaxial layer on silicon with low dislocation density and high carrier mobility. The reduction of dislocation is realized by inserting a thin layer with high density of Ga vacancies to promote the dislocation bending. The dislocation density is ${1.6}\times {10}^{{8}}$ cm−2 with a GaN drift layer thickness of $4.5~\mu \text{m}$ . The fabricated prototype GaN SBD delivers a high on/off current ratio of $10^{{10}}$ , a high forward current density of 1.6 kA/cm2@3 V, a low specific on-resistance of 1.1 $\text{m}\Omega \cdot \text {cm}^{{2}}$ , and a low ideality factor of 1.23.
TL;DR: In this article, a content addressable memory (CAM) cell based on ferroelectric HfO2 field effect transistors (FeFETs) is presented.
Abstract: In this work, we present an experimental demonstration of a content addressable memory (CAM) cell based on ferroelectric HfO2 field effect transistors (FeFETs). Our proposed ferroelectric CAM (FeCAM) utilizes a CMOS-compatible ferroelectric material, hafnium zirconium oxide (HZO), as the gate dielectric. We discuss operation of the FeCAM cell and propose a suitable architecture to realize in-memory computation as well as single clock cycle content-driven search. In addition, the HZO FeFET is analyzed for its intrinsic memory characteristic, and design considerations are identified for improving device and therefore projected system-level performance. Our results indicate that FeCAM is well-suited to accommodate demanding modern computational needs by sealing the gaps between conventional memory, logic, and continued device scaling.
TL;DR: In this paper, N-polar GaN MIS-HEMTs were reported to achieve high gain (12.7 dB) and excellent linearity performance (OIP3/ $\text{P}_{\mathbf {DC}}$ of 15 dB) for low-power receiver application at 30 GHz.
Abstract: Though GaN HEMTs have primarily been used for power amplification, they are also well suited for receiver applications. In the front-end of receivers, non-linearities, in particular third-order intermodulation products lead to in-band signal distortion. The intermodulation distortion is primarily dominated by transconductance and its derivatives. In this paper, we report on N-polar GaN MIS-HEMTs able to simultaneously achieve high gain (12.7 dB) and excellent linearity performance (OIP3/ $\text{P}_{\mathbf {DC}}$ of 15 dB) for low-power receiver application at 30 GHz. With a two-tone load-pull input-bias sweep, we demonstrate that the linearity of high performance HEMTs is sensitive to bias, and we present our measurement methodology to accommodate this.
TL;DR: In this paper, a hydrogen-plasma-based guard ring (GR) for high voltage vertical GaN p-n diodes grown on bulk GaN substrates by metalorganic chemical vapor deposition (MOCVD) was presented.
Abstract: This letter demonstrates novel hydrogen-plasma based guard rings (GRs) for high voltage vertical GaN p-n diodes grown on bulk GaN substrates by metalorganic chemical vapor deposition (MOCVD). The GR structure can significantly improve breakdown voltages ( BV ) and critical electric fields ( ${E}_{c}$ ) of the devices. Not having field plates or passivation, the p-n diodes with a $9~\mu \text{m}$ drift layer and 10 GRs showed BV /on-resistance ( ${R}_{\textit {on}}$ ) of 1.70 kV/0.65 $\text{m}\Omega \cdot $ cm2, which are close to the GaN theoretical limit. Moreover, the device also exhibited good rectifying behaviors with an on-current of ~ 2.6 kA/cm2, an on/off ratio of ~ 1010, and a turn-on voltage of 3.56 V. This work represents one of the first effective GR techniques for high performance kV-class GaN p-n diodes.
TL;DR: In this paper, a new type of vertical nanowire (NW)/ nanosheet (NS) field effect transistors (FETs), termed vertical sandwich gate-all-around (GAA) FETs, is presented.
Abstract: A new type of vertical nanowire (NW)/ nanosheet (NS) field-effect transistors (FETs), termed vertical sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work. Moreover, an integration flow that is compatible with processes used in the mainstream industry is proposed for the VSAFETs. Si/SiGe epitaxy, isotropic quasi-atomic-layer etching (qALE), and gate replacement were used to fabricate pVSAFETs for the first time. Vertical GAA FETs with self-aligned high-k metal gates and a small effective-gate-length variation were obtained. Isotropic qALE, including Si-selective etching of SiGe, was developed to control the diameter/thickness of the NW/NS channels. NWs with a diameter of 10 nm and NSs with a thickness of 20 nm were successfully fabricated, and good device characteristics were obtained. Finally, the device performance was investigated and is discussed in this work.
TL;DR: This work demonstrates highly scaled, non-volatile memory transistors with ferroelectric Zr-doped HfO2(HZO) as gate insulator with robust memory operation with ≤100 ns program and erase speed at ±5 V, and insights into the importance of holes on memory operation.
Abstract: In this work, we demonstrate highly scaled, non-volatile memory transistors with ferroelectric Zr-doped HfO2(HZO) as gate insulator. ${\Omega }$ -gate transistors with gate length ~30 nm and width ~85 nm were fabricated on ~20 nm thick SOI. We demonstrate robust memory operation with ≤100 ns program and erase speed at ±5 V, projected memory retention time up to 10 years at 85 °C, and ~0.5 V memory window after 108 endurance cycles. The impact of ${V} _{\text {D}}$ on erase speed provides insights into the importance of holes on memory operation.