IEEE Embedded Systems Letters 

About: IEEE Embedded Systems Letters is an academic journal published by Institute of Electrical and Electronics Engineers. The journal publishes majorly in the area(s): Computer science & Field-programmable gate array. It has an ISSN identifier of 1943-0663. Over the lifetime, 452 publications have been published receiving 5495 citations. The journal is also known as: Embedded systems letters & Institute of Electrical and Electronics Engineers embedded systems letters.

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

Abstract: A key challenge to the future of energy-harvesting systems is the discontinuous power supply that is often generated. We propose a new approach, Hibernus, which enables computation to be sustained during intermittent supply. The approach has a low energy and time overhead which is achieved by reactively hibernating: saving system state only once, when power is about to be lost, and then sleeping until the supply recovers. We validate the approach experimentally on a processor with FRAM nonvolatile memory, allowing it to reactively hibernate using only energy stored in its decoupling capacitance. When compared to a recently proposed technique, the approach reduces processor time and energy overheads by 76%–100% and 49%–79% respectively.

An Analyzable Memory Controller for Hard Real-Time CMPs

Abstract: Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences that tasks suffer when accessing shared hardware resources. We propose an analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of tight WCET estimations.

Multipliers With Approximate 4–2 Compressors and Error Recovery Modules

Abstract: Approximate multiplication is a common operation used in approximate computing methods for high performance and low power computing. Power-efficient circuits for approximate multiplication can be realized with an approximate 4–2 compressor. This letter presents a novel design that uses a modification of a previous approximate 4–2 compressor design and adds an error recovery module. The proposed design, even with the additional error recovery module, is more accurate, requires less hardware, and consumes less power than previously proposed 4–2 compressor-based approximate multiplier designs.

S2CBench : synthesizable systemc benchmark suite for high-level synthesis

Abstract: High-level synthesis (HLS) is being increasingly used for commercial VLSI designs. This has led to the proliferation of many HLS tools. In order to evaluate their performance and functionalities, a standard benchmark suite in a common language supported by all of them is required. This letter presents a benchmark suite, which complies with the latest Synthesizable SystemC standard, called S2CBench. The benchmarks have been carefully chosen to not only include applications of different sizes and from various domains typically used in HLS (e.g., encryption, image and DSP application), but also to test specific optimization techniques in each of them. This allows an easy comparison of not only quality of results (QoR) of the different HLS tools under review, but also to test their completeness.

ZyCAP : efficient partial reconfiguration management on the Xilinx Zynq

Abstract: New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.