IEEE Journal of Solid-state Circuits
About: IEEE Journal of Solid-state Circuits is an academic journal. The journal publishes majorly in the area(s): CMOS & Amplifier. It has an ISSN identifier of 0018-9200. Over the lifetime, 10610 publication(s) have been published receiving 532021 citation(s).
01 Oct 1989-IEEE Journal of Solid-state Circuits
Abstract: The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >
01 Oct 1974-IEEE Journal of Solid-state Circuits
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Abstract: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.
01 Apr 1992-IEEE Journal of Solid-state Circuits
Abstract: Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >
01 Feb 1998-IEEE Journal of Solid-state Circuits
Abstract: A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed.
01 Jun 1975-IEEE Journal of Solid-state Circuits
Abstract: The new class of amplifiers described is based on a load network synthesized to have a transient response which maximizes power efficiency even if the active device switching times are substantial fractions of the a.c. cycle. The new class of amplifiers, named `Class E,' is defined and is illustrated by a detailed description and a set of design equations for one simple member of the class. For that circuit the authors measured 96 percent transistor efficiency at 3.9 MHz at 26-W output from a pair of Motorola 2N3735 TO-5 transistors. Advantages of Class E are unusually high efficiency, a priori designability, large reduction in second-breakdown stress, low sensitivity to active-device characteristics, and potential for high-efficiency operation at higher frequencies than previously published Class-D circuits.
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