Showing papers in "IEEE Journal of Solid-state Circuits in 1967"
TL;DR: The theory emphasizes the decomposition into second-order systems that are developed, following state-space concepts, with special reference to their sensitivity, which is shown to be very low for high operational amplifier gains.
Abstract: Using state-variable flow graphs and simple operational configurations suitable for integration, a theory for insensitive transfer function realization in terms of integrated circuits is discussed. The theory emphasizes the decomposition into second-order systems that are developed, following state-space concepts, with special reference to their sensitivity which is shown to be very low for high operational amplifier gains.
328Â citations
TL;DR: In this article, a technique for operating a p-n junction photodiode in a photon flux integration mode is described, where the voltage across the junction will decay at a rate that is independent of junction area.
Abstract: A technique for operating a p-n junction photodiode in a photon flux integration mode is described. In this mode the p-n junction is charged to a reverse voltage (less than its breakdown voltage) and then open-circuited. The voltage across the junction, with zero incident illumination, will decay at a rate that is independent of junction area. Time constants in the order of seconds may be achieved with silicon planar structures at room temperature. Under illumination, the rate of decay of charge depends linearly on the intensity of the incident illumination, so that the total charge removed is proportional to the time integral of illumination. Operation of p-n junction photodiodes is analyzed for this mode and boundary conditions are established. A practical structure utilizing this mode of operation is discussed. This structure makes use of the nearly ideal switch characteristics of an insulated gate field-effect transistor to periodically sample a photodiode. Advantages offered by this device structure include 1) linear dependence of signal charge on light intensity over several orders of magnitude; 2) electronically controllable sensitivity; 3) ease of integration into arrays for image sensing.
227Â citations
IBM1
TL;DR: A unique but rather simple layout method is described that combines layout standardization with high circuit density generally expected from customized layout, at the same time, the design of the personality (the desired interconnection pattern) is simplified, while using a single layer of metallization.
Abstract: Large scale integration of complex logic is generally assumed to be a compromise between two conflicting cost factors, i.e., reduced design time through layout standardization, and increased yield through high circuit density, A unique but rather simple layout method is described that combines layout standardization with high circuit density generally expected from customized layout. At the same time, the design of the personality (the desired interconnection pattern) is simplified, while using a single layer of metallization. The method has been applied to complex logic using MOS NOR circuits.
119Â citations
TL;DR: A new representation of noisy twoports in terms of parameters invariant under Iossless transformation is proposed, which is especially advantageous when the terminals of the intrinsic device are not directly accessible.
Abstract: A new representation of noisy twoports in terms of parameters invariant under Iossless transformation is proposed. This representation is especially advantageous when the terminals of the intrinsic device are not directly accessible. A method of determining noise parameters in a transmission line system using a calibrated slide-screw tuner is discussed. Experimental results are presented.
90Â citations
TL;DR: The current status of large scale integration (LSI) technology is reviewed, with emphasis on developments made during the past year, with a discussion of complexity versus cost, perfommce, and reliability for various LSI technologies.
Abstract: The current status of large scale integration (LSI) technology is reviewed, with emphasis on developments made during the past year. Problem areas and solution approaches are emphasized, Four LSI technologies are considered as follows. 1) LSI bipolar chip technology (100 percent yield over chip area) reviews progress toward increasing the cornplexit y level on semiconductor chips. Conclusions of a Texas Instruments study of yie!d versus chip area are discussed, and a forecast is made of complexity levels for logic and memory. Several master-slice customization programs now under development in industry are reviewed. 2) LSI full-slice technology (discretionary wiring) is discussed for read-write and read-only memory of 1600 bits per slice and customized logic of 100 to 250 gates per slice. 3) LSI MOS technology is reviewed emphasizing progress in speed improvements and area reduction through development of four-phase ratioless circuitry. Technological factors which govern MOS speed are discussed. 4) LSI hybrid technology is briefly discussed. The paper concludes with a discussion of complexity versus cost, perfommce, and reliability for various LSI technologies. The problem of selecting an optimum LSI technology for a given application is discussed by consideration of several specific examples.
51Â citations
TL;DR: A lumped circuit model is proposed and justified on physical and experimental grounds and it is shown that interconnections behave like RC transmission lines at low frequencies, with the effect of inductance showing up at midrange and high frequencies.
Abstract: The availability of very fast semiconductor switching devices and the possibilities of large scale integration have increased the importance of the interconnection problem for the design of high-speed computers. The interconnection delay represents a fundamental boundary which limits the ultimate speed of logic circuits. The transmission-line behavior of interconnections on integrated-circuit chips, especially for subnanosecond applications, is the prime concern of this paper. A lumped circuit model is proposed and justified on physical and experimental grounds. It is shown that interconnections behave like RC transmission lines at low frequencies, with the effect of inductance showing up at midrange and high frequencies. Some simple formulas are included for design use.
45Â citations
TL;DR: The concept of treating groups of interconnected elements, rather than single gates, as the smallest units that are to be diagnosed and replaced with spares is proposed as a means for reducing the complexity (and the corresponding shrinkage) as well as the cost of discretionary interconnections.
Abstract: Methods of supplementing digital LSI integrated networks with redundant elements, or groups of elements, for the purpose of increasing network yields during their manufacture are described. It is shown how, with a small percentage of spare rows of memory elements in memory arrays or a small percentage of additional groups of elements in shift-register-like structures, substantial yield improvements may be economically achieved. A limited discretionary-wiring technique for random logic is contrasted with an existing more general approach. The concept of treating groups of interconnected elements, rather than single gates, as the smallest units that are to be diagnosed and replaced with spares, is proposed as a means for reducing the complexity (and the corresponding shrinkage) as well as the cost of discretionary interconnections. The concept of a temporary test metallization that deliberately interconnects groups of elements (where each group realizes some combinational switching function) into testable arrays, as one step in manufacturing to reduce the number of test probings and tests, is introduced. The efficient testing of an array of three-variable parity functions with four array tests is demonstrated. The tests applied to such an array, unlimited in dimension, can detect and locate a single failed group and can detect the presence of more than one failed group. Multiple faults can be located with additional sequential array tests if the number of defective groups is not large.
36Â citations
TL;DR: The silicon transistor base bias voltage necessary for linearly increasing collector current with temperature is derived and a constant voltage is shown to be adequate in practical applications, enabling temperature-independent small-signal diode conductance to be simply obtained.
Abstract: The silicon transistor base bias voltage necessary for linearly increasing collector current with temperature is derived. A constant voltage is shown to be adequate in practical applications, enabling temperature-independent small-signal diode conductance to be simply obtained.
33Â citations
TL;DR: The development of economic hybrid integrated filter building blocks is reported on, based on a metliod of network synthesis that generates general second-order networks by pole-zero cancellation of passive RC and active all-purpose frequency emphasizing networks.
Abstract: The development of economic hybrid integrated filter building blocks is reported on. The units are versatile and can be utilized for a wide variety of applications. They are based on a metliod of network synthesis that generates general second-order networks by pole-zero cancellation of passive RC and active all-purpose frequency emphasizing networks.
22Â citations
TL;DR: A new theory of class C amplifiers and frequency multipliers is developed on the basis of the large-signal Ebers-Moll equations and it is shown that both collector efficiency and power gain can be calculated as closed functions of input level for all orders of multiplication.
Abstract: A new theory of class C amplifiers and frequency multipliers is developed on the basis of the large-signal Ebers-Moll equations. It is shown that both collector efficiency and power gain can be calculated as closed functions of input level for all orders of multiplication. The results are obtained without recourse to graphical methods or to piecewise-linear approximations; neither is it necessary to invoke the concept of conduction angle. Expressions are derived for the maximum efficiency and gain attainable with a given transistor under ideal conditions. The theoretical results are presented as normalized curves and are in excellent agreement with measurement at low frequencies. An approximate treatment of the high-frequency case is also given.
21Â citations
TL;DR: A simple network modification is suggested that overcomes this limitation and introduces an added degree of freedom with parameters that are determined by passive components only.
Abstract: Noninverting operational amplifiers cannot readily be used for various Sallen and Key filters because they cannot provide gain less than unity. A simple network modification is suggested that overcomes this limitation and introduces an added degree of freedom with parameters that are determined by passive components only.
TL;DR: To show the feasibility of adapting silicon-on-sapphire complementary MOS technology to LSI, a 9-bit word (1-byte) was constructed and the entire module containing 54 N-channel and 36 P-channel devices dissipated less than 100 /spl mu/ W in a standby condition.
Abstract: Complementary MOS circuitry offers the advantages of high-speed, low-quiescent power dissipation, and loose device parameter tolerances. However, only with the recent development of clean technology has it been possible to fabricate stable devices. The advances in silicon-on-sapphire epitaxy have permitted the development of a high-speed low-power complementary MOS circuit module. This paper describes the circuit, its operation, the method used in fabricating it in silicon-on-sapphire, and the switching performance of the circuit. The basic memory cell is a NDRO flip-flop with feedback supplied through a transmission gate. The total circuit delay from write command to output sense signal is 5 to 7 ns at a standby power dissipation of 7 to 20 /spl mu/ W. To show the feasibility of adapting silicon-on-sapphire complementary MOS technology to LSI, a 9-bit word (1-byte) was constructed. The entire module containing 54 N-channel and 36 P-channel devices dissipated less than 100 /spl mu/ W in a standby condition.
TL;DR: From this analysis, latch-up and oscillation phenomena in the transistor switching circuit can be predicted and a technique of nonlinear analysis is employed to investigate the circuit stability.
Abstract: In the common-emitter transistor switching application, there are occasions in which the collector supply voltage exceeds the transistor sustain voltage Consequently, the load line could intersect the negative resistance characteristic of the device in the I /sub C/ -V /sub CE/ plane, resulting in a possible unstable or latch-up condition The purpose of this paper is to study analytically the avalanche region characteristics and their implications for transistor switching applications The first part is concerned with the derivation of the direct current-voltage relation that, when viewed from the output terminal, represents a negative resistance The characteristic of this negative resistance depends on the base-emitter circuit condition The ac terminal behavior is treated in the second part where consideration of the frequency dependence of alpha leads to an equivalent circuit consisting of an inductance in series with a negative resistance Both elements are nonlinear as well as frequency-dependent With an external load connected to this nonlinear circuit, a technique of nonlinear analysis is employed to investigate the circuit stability From this analysis, latch-up and oscillation phenomena in the transistor switching circuit can be predicted Since the second breakdown involves additional mechanisms besides avalanche multiplication, it is not discussed in this paper
TL;DR: In this paper, the Q and input inductance of a capacitor-loaded gyrator were calculated and it was shown that, at the expense of inductance, arbitrarily large Q can be obtained.
Abstract: Taking into account the nonzero input and output impedances of practical gyrators, the Q and input inductance of a capacitor-loaded gyrator are calculated. It is shown that, at the expense of inductance, arbitrarily large Q can be obtained.
TL;DR: In this paper, a negative-impedance inverter (NIV) is used to realize the negative dual of any driving point function, and the feasibility of such a scheme is demonstrated by using, in place of each controlled source, a transistor amplifier that uses a common base stage and a common collector stage in cascade.
Abstract: A negative-impedance inverter (NIV) can be used to realize the negative dual of any driving-point function. This paper describes a scheme by which two controlled sources are connected in series to realize the NIV, and the basic principle involved is de-lineated. The feasibility of such a scheme is demonstrated by using, in place of each controlled source, a transistor amplifier that uses a common-base stage and a common-collector stage in cascade. The transistor amplifier requires only one power supply and is readily adaptable for integrated-circuit applications. Experimental results showing the realizability of the negative resistance, the negative capacitance, and the negative inductance by this NIV circuit are presented.
TL;DR: The IEEE STANDARD, "Definitions of Terms for Integrated Electronics," (No. 274, effective December, 1966) appears on the following page.
Abstract: The IEEE STANDARD, "Definitions of Terms for Integrated Electronics," (No. 274, effective December, 1966) appears on the following page. Three interesting points form the background of this rather terse description of the essence of a major technological revolution.
TL;DR: A novel 100-ns nondestructively-read semiconductor memory is described, where 16 simple bipolar flip-flops are integrated on a 30 X 38 mil beam-leaded chip.
Abstract: A novel 100-ns nondestructively-read semiconductor memory is described. Sixteen simple bipolar flip-flops are integrated on a 30 X 38 mil beam-leaded chip. Memory arrays are produced by bonding chips on large-area substrates. Performance of a 64-word 16-bits-per-word memory system is reported.
TL;DR: Methods for generating tests for combinatorial and sequential logic circuits are discussed and an integrated approach that uses many of the existing methods plus new techniques is described and illustrated.
Abstract: Methods for generating tests for combinatorial and sequential logic circuits are discussed. A survey of existing techniques is given. An integrated approach that uses many of the existing methods plus new techniques is described and illustrated.
TL;DR: The theoretical power Dissipation of a six-phase shift register is compared to the power dissipation of equivalent shift registers using other low-power circuit techiques, including the complementary MOS transistor technique, and it is shown that the six- phase technique has the lowest power dissidence from very low frequencies up to a limiting high frequency.
Abstract: The principle of multiphase MOS digital circuits is briefly discussed and the features of some presently used multi-phase schemes are given. The basic theory and implementation of a six-phase scheme, which make use of a basic principle not normally considered in low-power digital circuitry, are then described, and the first-order equations for power dissipation are derived. The theoretical power dissipation of a six-phase shift register is compared to the power dissipation of equivalent shift registers using other low-power circuit techiques, including the complementary MOS transistor technique, and it is shown that the six-phase technique has the lowest power dissipation from very low frequencies up to a limiting high frequency. Finally, the power dissipation of an actual six-phase circuit is compared to the dissipation predicted from the derived equations.
TL;DR: A new philosophy is needed for integrating software and hardware using greatly increased quantities of electronics to reduce total costs.
Abstract: Silicon electronics comprise only about two percent of total digital computing costs. For LSI to pay off, a new philosophy is needed for integrating software and hardware using greatly increased quantities of electronics to reduce total costs.
TL;DR: The system, comprised of a small artwork generator of high capability and a language structure which allows for compact description of chip features, has demonstrated itself capable of substantial savings in mask generation time and cost.
Abstract: Large scale integration offers the possibility of very low-cost digital circuits. However, to realize fully the cost potential in LSI, several problems must be solved, one of which is the time and cost involved in preparing, by conventional techniques, masks for LSI chip fabrication. To facilitate mask generation, an artwork generator system has been developed. The system, comprised of a small artwork generator of high capability and a language structure which allows for compact description of chip features, has demonstrated itself capable of substantial savings in mask generation time and cost.
TL;DR: In this article, a DTL design is compared to an ECL design to illustrate a basis for choice of circuit type, power level, and interrelationship with respect to resistor and transistor parameters.
Abstract: Large scale integration is the simultaneous realization of large area circuit chips and optimum component packing density for the express purpose of reducing costs by maximizing the number of system connections done at the chip level. The highly complex monolithic circuits being offered today are obviously the forerunners of true LSI. Many questions pertinent to LSI are asked repeatedly today. Some of the more timely aspects of large scale integration are considered here. The prime objective of this paper is, therefore, to establish where LSI is today. The coverage is limited to bipolar silicon integrated circuits. A DTL design is compared to an ECL design to illustrate a basis for choice of circuit type, power level, and interrelationship with respect to resistor and transistor parameters. Arrays of DTL and ECL gates with single-layer interconnection metal are next considered; each gate is assumed to have one semiconductor crossunder tunnel. The resulting expressions relate the maximum allowable number of DTL and ECL gates in the monolayer array to circuit threshold. Next, the characteristics of metal interconnections are examined to obtain a method for predicting average interconnection length, die area occupied by the interconnections, and signal delay introduced by the interconnections. Finally, some thermal aspects of packaging a square hybrid LSI array of 2n X 2n chips are analyzed for an ECL and a DTL design. An expression is derived which relates power density of the hybrid array to the number of gates in the array and pertinent properties of the base system.
TL;DR: This paper describes a method of designing the optimum monostable tunnel diode switch: optimum in the sense that it permits the highest switching rate for the minimum expense of the output pulse height for a given tunnel diodes.
Abstract: This paper describes a method of designing the optimum monostable tunnel diode switch: optimum in the sense that it permits the highest switching rate for the minimum expense of the output pulse height for a given tunnel diode. The selection criteria of the tunnel diode for high speed switching applications are also given. The method is based on a unified theory of operation of the tunnel diode oscillator and pulse generator by means of a graphical analysis, taking the nonlinear nature of the diode into consideration. The theory explains the phase-gated microwave oscillation; an experimental 9-GHz oscillator generated a very short carrier pulse consisting of any controlled number of oscillation cycles, even of one cycle, thus reducing itself to a monostable pulse generator. 4-GHz oscillators of the optimum design using 20-mA, GaAs tunnel diodes have been demonstrated to be capable of operating as the monostable switch at 2-GHz repetition rate. This is an improvement of the speed capability of the device which has been limited below one GHz.
TL;DR: In this article, a thin-film circuit described in this paper is equivalent to a demodulator circuit containing an extremely selective filter ("sideband" filter), which would, in conventional form, require very high Q inductors or, as the Q requirement increases, the use of crystal or mechanical filters.
Abstract: The thin-film circuit described in this paper is equivalent to a demodulator circuit containing an extremely selective filter ("sideband" filter). Such a filter would, in conventional form, require very high Q inductors or, as the Q requirement increases, the use of crystal or mechanical filters. At the frequency of operation of this circuit (1 MHz), demodulation with conventional filters would have to be accomplished in two or more stages so that the selectivity requirement can be decreased for each filter. Thin-film techniques restrict us to circuits using only resistors (R), capacitors (C), and added semiconductor devices (thin-film inductors are not considered here since their inductance values are too small). The current trend is to realize frequency selective networks (conventionally in LC form) as active RC networks. However, although the circuit described here incorporates such a network, the main selectivity requirement cannot be met by present-day active network techniques. The solution is found in the use of time-varying RC networks, i.e., by combining passive RC thin-film phase-shift networks with miniature transistors, used as electronic switches, in the form of so-called quadrature modulation circuits. The phase-shift networks, which in principle can be passive thin-film RC circuits, are in practice more easily realized as combinations of much simpler RC circuits with buffer amplifiers.
TL;DR: A high-speed transitor circuit suitable for driving S-band diode digital phase shifters for a phased array antenna is described in this correspondence.
Abstract: In a solid-state microwave diode switch, the diode requires a relatively low voltage and high current in the forward direction and a relatively high voltage and low current in the reverse direction with rapid switching between these two states. A high-speed transitor circuit suitable for driving S-band diode digital phase shifters for a phased array antenna is described in this correspondence.
TL;DR: A circuit is presented that exhibits stable long-term memory analogous to that provided by Coulomb friction in mechanical systems and may be applied to cancel the drift of any viscous-type analog memory element.
Abstract: A circuit is presented that exhibits stable long-term memory analogous to that provided by Coulomb friction in mechanical systems. The circuit stabilizes the voltage across a capacitor. The capacitor voltage controls the length of a delay whose beginning is synchronized with a stable oscillator. At the end of the delay, the oscillator output is sampled and fed as a current to the capacitor. Periodic repetition of this procedure produces an average capacitor current that is a periodic function of capacitor voltage. Over the voltage range where the peak value of this current exceeds the intrinsic leakage current, every other one of those voltages at which the net average current is zero is a stable voltage. The principles used in this circuit may be applied to cancel the drift of any viscous-type analog memory element. The stored values are discrete but may be made so numerous as to approximate true analog memory to virtually any desired degree.
TL;DR: Techniques for assessing the inherent pulse noise immunity of saturated logic gates, with a view towards determining their ability to operate reliably in a pulse noise environment are developed.
Abstract: This paper develops techniques for assessing the inherent pulse noise immunity of saturated logic gates, with a view towards determining their ability to operate reliably in a pulse noise environment. A test method has been outlined for specifying and measuring this noise immunity. Although this method is applicable to all forms of saturated logic, the low level T /sup 2/ L gate has been singled out for experiment because of its high speed capability. Using both discrete component and microcircuit gates of this type, close correlation was obtained between experimental results and calculations based on internal parameters of the individual devices.
TL;DR: The purpose of this issue is to act as an expose of advanced work being done in this field and recognize the central position of large scale integration in electronics and its salient importance in solid-state circuits.
Abstract: The interests of the solid-state circuits community have been focused on integrated circuits during the past several years. Through a potent combination of technological and economic factors, the development of digital integrated circuits has progressed at a particularly rapid rate during this petiod. At present, large scale integration represents the region of singular importance in the field of digital integrated circuits. Typically, large scale integration consists of the combination of a multiplicity of circuit elements within a basic cell and the further combination of a multiplicity of cells in a monolithic structure to form a highly complex integrated circuit or an integrated equipment component. A most significant feature of an integrated equipment component is the uniquely intimate interdependence of its material, device, circuit, and system-design considerations. Recognizing this interdependence, the central position of large scale integration in electronics and its salient importance in solid-state circuits, the purpose of this issue is to act as an expose of advanced work being done in this field.
TL;DR: A frequency discriminator using two distributed RC null networks with different null frequencies, which can be realized in thin- or thick-film technology, and the analysis covers exponentially tapered and uniformly distributed networks, their difference in sensitivity, and harmonic disitortion due to nonlinearity of the response.
Abstract: The paper describes a frequency discriminator using two distributed RC null networks with different null frequencies, which can be realized in thin- or thick-film technology. The null networks with their null frequencies situated on either side of the carrier frequency use a common input. Their output signals are rectified and subtracted. The demodulated output signal is available either balanced or unbalanced. The analysis covers exponentially tapered and uniformly distributed networks, their difference in sensitivity, and harmonic disitortion due to nonlinearity of the response. The circuit can handle wide frequency deviations of up to /spl plusmn/ 20 percent and delivers an unbalanced output signal of approximately 0.46 volt rms using exponentially tapered networks and an input signal of 1 volt rms with /spl plusmn/ 10 percent frequency deviation. The harmonic distortion in this case is 3.3 percent. Calculated results are compared with measurements of an experimental 1O-MHz discriminator.
TL;DR: A small, inexpensive, and accurate time-interval counter is described, which has been developed especially for GaAs optical radar systems, and measures time intervals down to 15 ns.
Abstract: A small, inexpensive, and accurate time-interval counter is described, which has been developed especially for GaAs optical radar systems The output of the counter provides a voltage proportional to the time interval of a start and stop pulse Pulse averaging can easily be accomplished The counter measures time intervals down to 15 ns