Showing papers in "IEEE Journal of Solid-state Circuits in 1971"
TL;DR: In this paper, an expression for the equivalent source resistance of the capacitor diode voltage multiplier circuit is derived, and the distribution of capacitors that minimizes source resistance is presented.
Abstract: An expression for the equivalent source resistance of the capacitor diode voltage multiplier circuit is derived. The source resistance is found to increase as the cube of the multiplication factor, explaining the poor regulation observed with large multiplication. The distribution of capacitors that minimizes source resistance is presented. Good regulation is shown to be necessary for high efficiency, and to require relatively larger capacitors than needed for ripple filtering.
144Â citations
TL;DR: CANCER is a reasonably general circuit analysis program especially suited to integrated-circuit simulation and derives its efficiency from the exploitation of sparse matrix, adjoint, and implicit integration techniques.
Abstract: CANCER is a reasonably general circuit analysis program especially suited to integrated-circuit simulation. The program provides for the analysis of large circuits in the following four modes of operation: nonlinear d.c., large-signal transient, small-signal a.c., and thermal and shot noise. These subanalysis capabilities are intercoupled appropriately for convenience and efficiency. Internally, CANCER is a very general nodal analysis program that derives its efficiency from the exploitation of sparse matrix, adjoint, and implicit integration techniques.
125Â citations
TL;DR: The interreciprocal adjoint network concept is applied to the computer simulation of electronic-circuit noise performance, allowing consideration of an arbitrarily large number of uncorrelated noise sources with less effort than for the original small signal.
Abstract: The interreciprocal adjoint network concept is applied to the computer simulation of electronic-circuit noise performance. The method described is extremely efficient, allowing consideration of an arbitrarily large number of uncorrelated noise sources with less effort than for the original small signal a.c. analysis. Because all noise sources may be considered, no a priori assumption need be made as to which noise sources are dominant in a complicated circuit. The method is illustrated with an operational- amplifier example.
115Â citations
TL;DR: A floating-gate avalanche-injection m.o.s. (FAMOS) charge-storage device is used as the basic nonvolatile memory element, and it is fully TTL compatible, and can be operated in both the static or dynamic mode.
Abstract: A floating-gate avalanche-injection m.o.s. (FAMOS) charge-storage device is used as the basic nonvolatile memory element. The memory is organized as 256 words of 8 bits, it is fully TTL compatible, and can be operated in both the static or dynamic mode. The memory array was successfully fabricated with silicon gate m.o.s. technology yielding functional devices with access times of 800 ns in the static mode and 500 ns in the dynamic mode of operation. The memory chip is assembled in a 24-lead dual-in-line package.
90Â citations
TL;DR: In this article, the authors evaluated drift-aiding fringing fields at Si-SiO/SUB 2/interface (fringing fields) in charge-coupled devices (CCD) by an approximate analysis and also by computer.
Abstract: Transverse electric fields at the Si-SiO/SUB 2/ interface (fringing fields) can aid transfer of charge from one potential well to another in charge- coupled devices (CCD). The magnitudes of these drift-aiding fringing fields are evaluated by an approximate analysis and also by computer. The analytical approach assumes zero space charge in the silicon and agrees with the computer solutions in that limit. When the depletion width becomes less than the gate width the fringing field is reduced considerably. Transit times associated with these fringing fields are evaluated. Trapping of charge in interface states rather than transfer of free charge is expected to be the fundamental limitation on speed and transfer efficiency in appropriately designed CCDs.
70Â citations
TL;DR: Q-stability measurements of hybrid- integrated positive feedback, or Sallen-Key-type circuits, which were realized with tantalum thin-film resistors and capacitors combined with beam-leaded operational amplifier chips agree very accurately with the predictions derived from gain-sensitivity calculations.
Abstract: It is shown that a different measure of performance must be used to evaluate hybrid-integrated active filters from that used to evaluate active filters in discrete form. Where sensitivity was previously found to be an adequate and useful measure for Q stability of discrete active filters, the gain-sensitivity product gives an accurate measure of Q stability for hybrid-integrated circuits. Where negative feedback filter schemes were found to be preferable with respect to Q stability when realized in discrete form, positive feedback schemes with their very much lower gain- sensitivity product may be preferable in hybrid-integrated filter circuits. In addition, they require low-gain amplifiers than can be used up to higher frequencies. Q-stability measurements of hybrid- integrated positive feedback, or Sallen-Key-type circuits, which were realized with tantalum thin-film resistors and capacitors combined with beam-leaded operational amplifier chips agree very accurately with the predictions derived from gain-sensitivity calculations.
57Â citations
TL;DR: A low frequency high-Q gyrator realization employing current conveyor building blocks is discussed and circuit design techniques to alleviate semiconductor device limitations are considered.
Abstract: An easily integrable circuit implementation of a current conveyor is presented. A low frequency high-Q gyrator realization employing current conveyor building blocks is discussed. Circuit design techniques to alleviate semiconductor device limitations are considered.
46Â citations
TL;DR: A computer program for the simulation of linear integrated circuits (SLIC) formulates and solves nonlinear equations for d.c. node voltages and transistor operating points; generates linearized small-signal circuit models; and solves for the poles, zeros, frequency response, and noise response of specified transfer functions.
Abstract: A computer program for the simulation of linear integrated circuits (SLIC) is described. The program formulates and solves nonlinear equations for d.c. node voltages and transistor operating points; generates linearized small-signal circuit models; and solves for the poles, zeros, frequency response, and noise response of specified transfer functions. Temperature variations and operating point dependence can be effectively simulated.
42Â citations
IBM1
TL;DR: A number of new mathematical and programming techniques are incorporated in the program, including sparse matrix storage and computation, dynamic storage allocation, and variable order implicit integration.
Abstract: ECAP II is a nonlinear d.c. and transient circuit analysis program capable of handling circuits larger than 1000 branches. It uses a free-format problem-oriented input language for describing the circuit parameters and topology. The program includes a nested model feature that permits the user to store in a model library circuit descriptions of devices, subcircuits, etc., for subsequent recall and insertion into larger circuits. Nonlinearities can be specified by means of tables, certain built-in functions such as the diode equation, and Fortran subroutines. All circuit elements can be made to depend on any current or voltage, on other circuit parameters, or on time itself. The user may specify which variables are to be printed out or plotted and what type of analysis is to be carried out. Diagnostics are provided to pinpoint errors in the input format and/or inconsistencies in the circuit description. A number of new mathematical and programming techniques are incorporated in the program, including sparse matrix storage and computation, dynamic storage allocation, and variable order implicit integration.
42Â citations
TL;DR: In this paper, a linearized analysis is presented to relate the charge transfer properties to the performance of an n-stage register and an approximate small signal equivalent circuit is also derived to illustrate the similarities to a matched transmission line and the reactive and resistive elements of the line.
Abstract: Charge transfer dynamic shift register operation is described and a linearized analysis presented to relate the charge transfer properties to the performance of an n-stage register. An approximate small signal equivalent circuit is also derived to illustrate the similarities to a matched transmission line and the reactive and resistive elements of the line are related to charge transfer and loss characteristics of each stage of the register. The results are expected to be applicable to charge coupled devices and shift registers based on bucket brigade electronics.
39Â citations
TL;DR: The variation of frequency and Q, as well as the sensitivity of these two quantities to changes in network elements, are closely and simply related to the variation and sensitivity of the corresponding pole.
Abstract: The variation of frequency and Q, as well as the sensitivity of these two quantities to changes in network elements, are closely and simply related to the variation and sensitivity of the corresponding pole. Since network analysis is often more convenient in terms of the complex pole quantities, while laboratory evaluations are carried out more easily in terms of the measurable frequency and Q quantities, the simple relationships discussed here have been found very useful when comparing experimental results with theoretical predictions.
TL;DR: An investigation of a typical example of the 741-type IC amplifier of the characteristics of the transistors and the performance limitations resulting from the devices and the individual stages of the amplifier.
Abstract: Although the basic operation of modern IC opamps is well understood, no detailed evaluation has been published concerning the characteristics of the transistors and the performance limitations resulting from the devices and the individual stages of the amplifier. In this paper, the results are given of an investigation of a typical example of the 741-type IC amplifier. Complete data are given on the transistor characteristics and parameters. Computer simulation is used to study the performance and limitations of the stages and the overall amplifier.
TL;DR: In this article, the effects of dielectric dissipation have been included in studies of distributed RC notch filter networks, and it was shown that these may have considerable influence on the magnitude of the optimum notch parameter /spl alpha/SUB 0,1/ and the location of the lowest order optimum notch frequency /spl omega//SUB 1,1/. Voltage transfer function relationships, incorporating a frequency-dependence dissipation factor B(spl omega/), are given for uniform and exponentially tapered structures.
Abstract: The effects of dielectric dissipation have been included in studies of distributed RC notch filter networks, and it is shown that these may have considerable influence on the magnitude of the optimum notch parameter /spl alpha//SUB 0,1/ and the location of the lowest order optimum notch frequency /spl omega//SUB 0,1/. Voltage transfer function relationships, incorporating a frequency-dependence dissipation factor B(/spl omega/), are given for uniform and exponentially tapered structures. The measured transfer responses of aluminium-silicon monoxide-nichrome evaporated thin-film notch structures were in good agreement with these values predicted. Uniformly distributed RC notch filters exhibited optimum notch attenuations of 71 dB, while exponentially tapered RC filters with taper D=+1 gave 62-dB optimum notch attenuation together with reduced rejection band width.
TL;DR: The authors set forth the onset parameters for the Ebers-Moll model and discuss their determination by terminal measurement and by calculation based on the transistor makeup, which limits consideration to the static behavior of transistors operating in the forward-active mode.
Abstract: A method is described that selects, for each transistor in a circuit, the model of least complexity that will give acceptable accuracy. The capability to assess model adequacy derives from a self-consistency test in which the values of currents and voltages computed in a simulation of the circuit behavior are compared with onset parameters, to determine whether these computed values are consistent with the approximations underlying the device models used in the simulation. The onset parameters for a model are the terminal currents and voltages above or below which the model fails to give a satisfactory representation of device behavior. The authors set forth the onset parameters for the Ebers-Moll model and discuss their determination by terminal measurement and by calculation based on the transistor makeup. The paper limits consideration to the static behavior of transistors operating in the forward-active mode.
TL;DR: TIME's straightforward free- format input, its built-in transistor model, the general analysis method, and its very efficient sparse matrix algorithm are described.
Abstract: TIME is a Fortran computer program that can perform low-cost nonlinear d.c. and time-response simulation of bipolar transistor circuits. This paper describes TIME's straightforward free- format input, its built-in transistor model, the general analysis method, and its very efficient sparse matrix algorithm. Example analyses illustrate the computational efficiency of the program.
TL;DR: A new current- differencing opamp has been developed that uses a simple circuit to provide a gain element that out performs the 741 IC opamp and multiple opamps are possible.
Abstract: The conventional integrated-circuit operational amplifier is not well suited to many system applications that operate from only a single power supply voltage. To more optimally meet the requirements of industrial control systems a new current- differencing opamp has been developed that uses a simple circuit to provide a gain element that out performs the 741 IC opamp. As a result of the circuit simplicity, multiple opamps are possible and six independent internally compensated amplifiers have been fabricated on a single 80/spl times/93-mil die. Many circuits are presented only not to show how this circuit can perform most the application functions of a standard IC opamp, but also to indicate the increased usefulness of this new input current differencing type of opamp circuit in single power-supply control system applications.
TL;DR: The transistor differential pair is analyzed and it is shown that the common mode rejection ratio (CMRR) is limited both in magnitude and bandwidth by device parameters.
Abstract: The transistor differential pair is analyzed and it is shown that the common mode rejection ratio (CMRR) is limited both in magnitude and bandwidth by device parameters. The performance is not significantly improved by series common-mode feedback. It is shown that amplifiers with shunt common-mode feedback reject common-mode input currents and that their common-mode rejection ratio can be made independent of device parameters. Applications of such amplifiers include differential operational amplifiers, rejection of large common-mode voltages, and transducer amplifiers. Basic circuitry is described and the performance of a practical circuit is given.
TL;DR: This paper presents a novel circuit technique that utilizes a resistive ladder network coupled to an array of common- emitter transistors, having obvious applications in other areas, for example as an analog-digital converting technique.
Abstract: Two novel circuit techniques are used. One is a compact analog memory element that is able to store a pair of coordinate values; eighty such elements can be placed on a 65/spl times/65 mil die. The other is a scanning technique that utilizes a resistive ladder network coupled to an array of common- emitter transistors, having obvious applications in other areas, for example as an analog-digital converting technique.
TL;DR: The unifying approach to the derivation of models for field-effect devices contains models for the small- and large-signal behavior of the two major types of field- effect transistor and of other related devices such as the semiconductor current limiter and the pinch resistor.
Abstract: This paper describes a unifying approach to the derivation of models for field-effect devices. The most general model yielded by this approach contains, as special cases, models for the small- and large-signal behavior of the two major types of field-effect transistor and of other related devices such as the semiconductor current limiter and the pinch resistor. From this most general model emerge, by application of particular approximations and constraints, several models proposed earlier for use in computer- aided circuit analysis. The unifying approach thus demonstrates the relationships borne among various existing models for field- effect devices. In addition, it provides a wide diversity of new models of different complexities and degrees of accuracy.
TL;DR: In the design of a class of sine-wave oscillators using resistors, capacitors, and operational amplifiers, there is either a direct tradeoff between the maximum component value and the dynamic range of signals with satisfactory sensitivity performance, or a direct Tradeoff betweenThe maximum componentvalue and the sensitivity performance with satisfactory dynamic range.
Abstract: In the design of a class of sine-wave oscillators using resistors, capacitors, and operational amplifiers, there is either a direct tradeoff between the maximum component value and the dynamic range of signals with satisfactory sensitivity performance, or a direct tradeoff between the maximum component value and the sensitivity performance with satisfactory dynamic range.
TL;DR: The behavior has been studied assuming that the transistor is acting as a nonlinear negative resistance dipole, defined from its I-V characteristics.
Abstract: The behavior has been studied assuming that the transistor is acting as a nonlinear negative resistance dipole, defined from its I-V characteristics. A simple method has been obtained to plot the static characteristic with good accuracy. Then the nonlinear differential equations for a simple switching circuit are graphically solved and the theory is compared with the experimental results.
TL;DR: In this article, the design, construction and performance of a solid-state untuned 2-30 MHz amplifier is described, operating at 28 V dc. Two-tone linearity over the frequency range is -30 dB or better at output powers from 5-60 W.
Abstract: The design, construction and performance of a solid-state untuned 2-30 MHz amplifier is described. Operation is from 28 V dc. Overall CW efficiency is greater than 47 percent at 60-w unfiltered output. Amplifier efficiency for two-tone 60-W PEP output is greater than 31 percent. two-tone linearity over the frequency range is -30 dB or better at output powers from 5-60 W. Broadband transmission-line transformers wound on ferrite toroids are used throughout for impedance matching. Hybrids of similar construction are used for output-power adding.
TL;DR: Each gyrator is used to realize a voltage-controlled current source and the input and output short circuit admittances, y/SUB 11/ and y-SUB 22/ for the complete circuit are made equal to zero by means of passive element matching.
Abstract: Each gyrator is used to realize a voltage-controlled current source. When the two sources are connected in parallel, the input and output short circuit admittances, y/SUB 11/ and y/SUB 22/ for the complete circuit are made equal to zero by means of passive element matching.
TL;DR: In this paper, the authors discuss the trends that have developed in LSI, and the requirements for refinements in process technology, closer process control, and improvements in design that are considered to be essential for the full realization of high LSI reliability.
Abstract: This paper discusses the trends that have developed in LSI, and the requirements for refinements in process technology, closer process control, and improvements in design that are considered to be essential for the full realization of high LSI reliability. Particular attention is paid to advanced multilevel-structure processing and to the use of specially designed test vehicles for purposes of process improvement and process control.
TL;DR: Phototransistor arrays providing video output from a common collector electrode, with the emitters connected to the vertical address strips and the bases capacitively coupled to the horizontal strips, are shown to possess advantages in ease of fabrication and operation.
Abstract: Phototransistor arrays providing video output from a common collector electrode, with the emitters connected to the vertical address strips and the bases capacitively coupled to the horizontal strips, are shown to possess advantages in ease of fabrication and operation.
TL;DR: In this article, a design automation program has been written to optimize the design of dc-coupled monolithic broadband amplifiers, adjusting dc conditions, device geometry, and all passive elements to obtain the maximum small-signal bandwidth consistent with specified low-frequency gain and quiescent power dissipation.
Abstract: A design automation program has been written to optimize the design of dc-coupled monolithic broad-band amplifiers This program adjusts dc conditions, device geometry, and all passive elements to obtain the maximum small-signal bandwidth consistent with specified low-frequency gain and quiescent power dissipation The principal features of the program are a frequency-response analysis subroutine based on a nodal admittance matrix formulation, a precise response sensitivity analysis using the adjoint network, and an optimization subroutine based on the Fletcher-Powell algorithm Two complete design examples, based on the series-series feedback triple and series-shunt feedback pair, are presented For typical integrated-circuit processing, a maximum bandwidth on the order of 100 MHz is obtained for these designs with a voltage gain of 34 dB and 96-mW power dissipation
TL;DR: In this paper, a simple voltage-follower circuit is described, whose offset voltage between input and output terminals is of the same magnitude as the input offset voltage of a bipolar integrated differential amplifier.
Abstract: A simple voltage-follower circuit is described. It is essentially an emitter-follower, whose offset voltage between input and output terminals is of the same magnitude as the input offset voltage of a bipolar integrated differential amplifier.
TL;DR: Developing a circuit representation of the integral charge-control model of bipolar transistors that is topologically the same as that for the Ebers-Moll model is recognized.
Abstract: The integral charge-control model (ICM) of bipolar transistors developed by Gummel and Poon (abstr. B31388 of 1970) describes the device physics compactly, coherently, and more accurately than do the other existing compact models of transistors. The significance of the ICM to circuit analysis is, however, masked by various analytical expressions describing the device physics. This significance is recognized here by developing a circuit representation of the ICM that is topologically the same as that for the Ebers-Moll model.
IBM1
TL;DR: The 128-bit NDRO random-access memory chip used in the IBM System 370, model 145, and System 7 is described and considered to packaging power dissipation and systems environment.
Abstract: The 128-bit NDRO random-access memory chip used in the IBM System 370, model 145, and System 7 is described. Consideration is given to packaging power dissipation and systems environment.
TL;DR: Complete fault protection is accomplished by providing the power transistors with good dc safe operating area, internally limiting the short circuit output currents, and accurately limiting the junction temperature to within 10/spl deg/C of the specified maximum limit.
Abstract: A five-terminal /spl plusmn/15-V monolithic voltage regulator has been developed that incorporates internal frequency compensation and internally provides a /spl plusmn/1 percent output voltage tolerance. In addition, a thermally symmetric layout design of the chip has been used to eliminate the detrimental effects of thermal feedback on the die and ensure that the complementary tracking output voltages will be independent of the power dissipation in the series pass power transistors. Complete fault protection is accomplished by providing the power transistors with good dc safe operating area, internally limiting the short circuit output currents, and accurately limiting the junction temperature to within 10/spl deg/C of the specified maximum limit. Also, a new Zener diode geometry is employed that significantly reduces the noise associated with the reference voltage.