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Showing papers in "IEEE Journal of Solid-state Circuits in 1974"


Journal ArticleDOI
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Abstract: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.

3,008 citations


Journal ArticleDOI
TL;DR: The characterization of surface channel charge-coupled device line imagers with front-surface imaging, interline transfer, and 2-phase stepped oxide, silicon-gate CCD registers is presented in this paper.
Abstract: The characterization of surface channel charge-coupled device line imagers with front-surface imaging, interline transfer, and 2-phase stepped oxide, silicon-gate CCD registers is presented. The analysis, design, and evaluation of 1/spl times/64 CCD line arrays are described in terms of their performance at low light levels. The authors describe the responsivity, resolution, spectral, and noise measurements on silicon-gate CCD sensors and CCD interline shift-registers. The influence of transfer inefficiency and electrical fat-zero insertion on resolution and noise is described at low light levels.

342 citations


Journal ArticleDOI
TL;DR: In this article, the effects of pole zero pairs (doublets) on the frequency response and settling time of operational amplifiers were explored using analytical techniques and computer simulation, and it was shown that doublets which produce only minor changes in circuit frequency response can produce major changes in settling time.
Abstract: The effects of pole-zero pairs (doublets) on the frequency response and settling time of operational amplifiers are explored using analytical techniques and computer simulation. It is shown that doublets which produce only minor changes in circuit frequency response can produce major changes in settling time. The importance of doublet spacing and frequency are examined. It is shown that settling time always improves as doublet spacing is reduced whereas the effect of doublet frequency is different for 0.1 and 0.01 percent error bands. Finally it is shown that simple analytical formulas can be used to estimate the influence of frequency doublets on amplifier settling time.

300 citations


Journal ArticleDOI
TL;DR: In this paper, a study of the IC op amp is presented to explain details of its behavior in a simplified and understandable manner, including thermal feedback effects on gain, basic relationships for bandwidth and slew rate, and a discussion of pole-splitting frequency compensation.
Abstract: A study is made of the integrated circuit operational amplifier (IC op amp) to explain details of its behavior in a simplified and understandable manner. Included are analyses of thermal feedback effects on gain, basic relationships for bandwidth and slew rate, and a discussion of pole-splitting frequency compensation. Sources of second-order bandlimiting in the amplifier are also identified and some approaches to speed and bandwidth improvement are developed. Brief sections are included on new JFET-bipolar circuitry and die area reduction techniques using transconductance reduction.

262 citations


Journal ArticleDOI
TL;DR: A macromodel has been developed for integrated circuit (IC) op amps which provides an excellent pin-for-pin representation and provides simulated circuit responses that have run times which are an order of magnitude faster and less costly in comparison to modeling the op amp at the electronic device level.
Abstract: A macromodel has been developed for integrated circuit (IC) op amps which provides an excellent pin-for-pin representation. The model elements are those which are common to most circuit simulators. The macromodel is a factor of more than six times less complex than the original circuit, and provides simulated circuit responses that have run times which are an order of magnitude faster and less costly in comparison to modeling the op amp at the electronic device level. Expressions for the values of the elements of the macromodel are developed starting from values of typical response characteristics of the op amp. Examples are given for three representative op amps. In addition, the performance of the macromodel in linear and nonlinear systems is presented. For comparison, the simulated circuit performance when modeling at the device level is also demonstrated.

194 citations


Journal ArticleDOI
TL;DR: The linearized transconductance multiplier (LTM) has rapidly gained acceptance as the preferred approach to the realization of monolithic analog multipliers, and its simplicity has commended it for use in low-cost modular designs.
Abstract: Since its conception in 1967, the linearized transconductance multiplier (LTM) has rapidly gained acceptance as the preferred approach to the realization of monolithic analog multipliers, and its simplicity has commended it for use in low-cost modular designs. Accuracies of these units have been limited to about 0.5 to 2 percent, and drift and noise performance have generally been worse than that possible using the dominant alternative technique of pulse-width-height modulation. This paper shows that when careful attention is given to all the sources of error it is possible to attain a five-fold improvement in accuracy and corresponding reductions in the drift and noise levels. Odd-order nonlinearities can be reduced to negligible magnitudes by the use of active feedback, by substituting the usual resistive-bridge feedback path by an amplifier identical to that used as the input stages.

148 citations


Journal ArticleDOI
TL;DR: The composite model is applied empirically to several examples ranging in area from half a slice to many slices, finding that the total silicon area involved could be divided into as few as two or three subareas.
Abstract: The defect density within an integrated circuit slice often exhibits gross variations from area to area. The density may vary from center to periphery, for example, or from side to side. In this paper the composite model is applied empirically to several examples ranging in area from half a slice to many slices. For each example, the total silicon area involved could be divided into as few as two or three subareas. Two methods for accomplishing the decomposition into subareas are described for one example.

118 citations


Journal ArticleDOI
TL;DR: In this article, a monolithic sample/hold amplifier is described, which includes the holding capacitor on the chip, and high performance is achieved by the use of a process which produces bipolar transistors and p-channel silicon-gate FET's (SIGFET's) on the same chip.
Abstract: A monolithic sample/hold amplifier is described which includes the holding capacitor on the chip. System design considerations and tradeoffs are discussed, as well as the circuit design details. High performance is achieved by the use of a process which produces bipolar transistors and p-channel silicon-gate FET's (SIGFET's) on the same chip. Performance characteristics obtained include an acquisition time of 10 /spl mu/s (20-V step), an aperture delay time of 80 ns, and a droop rate of 30 mV/s.

97 citations


Journal ArticleDOI
H. Berger1
TL;DR: The injection model is significant beyond the merged transistor logic (MTL) aspects as it renders a better insight into bipolar devices, particularly into lateral p-n-p and saturated n-p-n transistors.
Abstract: The merged transistor device is represented by assigning separate diodes to the various electron and hole injections along the active p-n junction. Where collection takes place, current sources are introduced. Measurement procedures are described that allow a quantitative separation of the various injections, and hence the determination of the model parameters. Results of such measurements are given. Device terminal parameters, like current gains and storage time constants, can be predicted from the measurements for devices of arbitrary horizontal geometry, so that the injection model can serve as a device optimization tool. As a circuit analysis model it allows representation of the internal device series resistances which would not be possible with an Ebers-Moll model. The injection model is significant beyond the merged transistor logic (MTL) aspects as it renders a better insight into bipolar devices, particularly into lateral p-n-p and saturated n-p-n transistors.

93 citations


Journal ArticleDOI
TL;DR: In this paper, the design of an integrated wide-band variable-gain amplifier with maximum dynamic range is approached by considering three basic bipolar transistor configurations from which all others can be derived.
Abstract: The design of an integrated wide-band variable-gain amplifier with maximum dynamic range is approached by considering three basic bipolar transistor configurations from which all others can be derived. The analysis of noise and of distortion shows the importance of transistor base resistance in all three circuits. On the basis of these analyses, one configuration is shown to yield maximum dynamic range, and this configuration is then used as the basis for the development of a new circuit called the improved automatic-gain control (agc) amplifier. A unique biasing scheme allows a considerable reduction in distortion and noise, together with a significant increase in bandwidth compared with conventional circuits.

88 citations


Journal ArticleDOI
TL;DR: A unique amplifier configuration is examined that fully exploits the intrinsically high signal-to-noise performance of charge-coupled devices (CCD's) and a floating gate amplifier (FGA) is presented.
Abstract: A unique amplifier configuration is examined that fully exploits the intrinsically high signal-to-noise performance of charge-coupled devices (CCD's). In this amplifier, the signal charge is detected with a conducting `floating gate' embedded in the oxide between a bias electrode and the silicon substrate. The change of voltage on the floating gate produced by the signal charge in the CCD channel is then used to modulate the current flow in a metal-oxide-semiconductor (MOS) transistor. The signal charge remains isolated and can be moved downstream in the CCD channel; thus, it can be detected again by other similar structures. Computer analysis, test structure design, and experimental results of a floating gate amplifier (FGA) are presented.

Journal ArticleDOI
TL;DR: VMOS as mentioned in this paper is a new v-groove n-channel MOS logic structure well suited for 5-V high-speed random logic, and it is 20 percent faster, four times smaller in area, and six times lower in power dissipation.
Abstract: VMOS is a new v-groove n-channel MOS logic structure well suited for 5-V high-speed random logic. Compared to a typical gold-doped TTL medium-scale integrated (MSI) circuit, an experimental pin for pin equivalent VMOS circuit is 20 percent faster, four times smaller in area, and six times lower in power dissipation. On-chip VMOS delays are in the 2-3 ns range; off-chip drive capability exceeds 50 MHz with 6 TTL unit loads.

Journal ArticleDOI
TL;DR: A method of optimum chip placement is described, and the results of computer calculations showing yield as a function of chip size are given assuming different defect density distributions.
Abstract: Various attempts have been made to analyze the yield of integrated circuits in the presence of point defects. This paper analyzes the yield considering both radial and angular variation in the defect density. The effect of statistical variations in the average defect density from slice to slice is also included. Different types of defects which affect the yield are reviewed. The degradation in yield due to point defects, line defects, area defects, and defect clusters is considered in detail. A method of optimum chip placement is described, and the results of computer calculations showing yield as a function of chip size are given assuming different defect density distributions. The results are primarily applicable to large integrated circuit chips.

Journal ArticleDOI
TL;DR: The design of a wide-band feedforward amplifier in the frequency range 30-300 MHz is described, and the effect of imperfect loop cancellation and circuit imbalance on gain and terminal impedances is investigated.
Abstract: The design of a wide-band feedforward amplifier in the frequency range 30-300 MHz is described. Expressions are derived for feedforward amplifier sensitivity, and the effect of imperfect loop cancellation is described. The effect of circuit imbalance on gain and terminal impedances is investigated. The circuit is realized in thin-film hybrid form, and measurements show 20 dB of distortion improvement at 300 MHz. Practical aspects of circuit adjustment and operation are considered.

Journal ArticleDOI
TL;DR: A simple device model is derived to represent merged transistor logic (MTL) circuit behavior and it is shown that MTL devices can be basically interpreted as n-p-n transistors having an additional base current source.
Abstract: A simple device model is derived to represent merged transistor logic (MTL) circuit behavior. Using the Ebers-Moll equations, the proper definitions of the various current gains are derived, and it is shown that MTL devices can be basically interpreted as n-p-n transistors having an additional base current source. The relations between the intensity of this source and the current actually supplied are derived. Time behavior is modeled according to the charge control concept. Using this model, circuit delays are given as a function of current gains, collector and emitter time constants, supply current, and of fan-out.

Journal ArticleDOI
W.T. Lynch1, H.J. Boll1
TL;DR: In this article, the authors analyzed dynamic IGFET flip-flop sensors and showed that the optimum latching waveform is an initial voltage step followed by a ramp of gradually increasing slope.
Abstract: Analysis of dynamic IGFET flip-flop charge sensors shows that the optimum latching waveform is an initial voltage step followed by a ramp of gradually increasing slope. Latchup time is approximately inversely proportional to the initial voltage imbalance. Capacitive coupling between the two sides of the flip-flop generates a voltage excursion of the off-side even when there is no off-side conduction. With a 10-V latching ramp, the off-side is no off-side conduction. With a 10-V latching ramp, the off-side voltage excursion is typically about 2 V, and full latchup is attained in about 75 ns for an initial imbalance of 0.5 V. If a small off-side conduction is allowed, then latchup time can be reduced by a factor of two or more. The penalty is a few tenths of a volt added excursion of the off-side voltage. Computer circuit simulations were used to verify the analytic derivations.

Journal ArticleDOI
TL;DR: In this paper, the design of a low-distortion, wideband amplifier with 75/spl Omega/input and output impedances is described, and the advantages of a Darlington connection for low distortion are described.
Abstract: The design of a low-distortion, wide-band amplifier with 75-/spl Omega/ input and output impedances is described. Simultaneous shunt and series feedback is used and design equations are derived for terminal impedances, forward gain, loop gain, and noise figure. The advantages of a Darlington connection for low distortion are described. For 0-dBm signal levels, the amplifier achieves third-order intermodulation products of -88 dB relative to the carrier at 300 MHz and 12 channel cross-modulation (CM) of -77 dB at channel 13.

Journal ArticleDOI
TL;DR: In this paper, a new high-speed monolithic operational amplifier is described which uses an improved feedforward circuit configuration to achieve a total acquisition time (slewing plus settling) of 650 ns with a 10-V input step without compromising dc performance or requiring costly nonstandard processing.
Abstract: A new high-speed monolithic operational amplifier is described which uses an improved feedforward circuit configuration to achieve a total acquisition time (slewing plus settling) of 650 ns with a 10-V input step without compromising dc performance or requiring costly nonstandard processing.

Journal ArticleDOI
D.J. Herrell1
TL;DR: In this article, the design of Josephson tunneling logic (JTL) gates capable of performing the logic functions of AND, OR, INVERT and CARRY is considered, and the design equations are solved for a rectangular Josephson junction in which the geometry was adjusted to ensure that all logical inputs were equivalent.
Abstract: The design of Josephson tunneling logic (JTL) gates capable of performing the logic functions of AND, OR, INVERT and CARRY is considered. The design equations were solved for a rectangular Josephson junction in which the geometry was adjusted to ensure that all logical inputs were equivalent. Experimental JTL gates were found to operate with a logic delay of less than 200 ps, and with a power-delay product of the order of five femtojoules.

Journal ArticleDOI
TL;DR: A technique is proposed for stabilizing the output amplitude of a variable-frequency RC sine-wave oscillator by converting amplitude to a d.c. voltage having only a small ripple content, which requires little filtering.
Abstract: A technique is proposed for stabilizing the output amplitude of a variable-frequency RC sine-wave oscillator. Amplitude settling time is reduced by converting amplitude to a d.c. voltage having only a small ripple content, which requires little filtering. A relationship between amplitude transient response and harmonic distortion is demonstrated, and the results are compared to those obtained by more conventional methods.

Journal ArticleDOI
N.C. De Troye1
TL;DR: Integrated injection logic (I/SUP 2/L) or merged transistor logic (MTL) incorporating lateral p-n-p transistors as current sources and multicollector n-p-n transistor as invertors, are discussed.
Abstract: Integrated injection logic (I/SUP 2/L) or merged transistor logic (MTL) incorporating lateral p-n-p transistors as current sources and multicollector n-p-n transistors as invertors, are discussed. Speed-power products of 0.13 pJ per gate have been measured in a five-stage closed-loop invertor chain, and packing densities of 400 gates/mm/SUP 2/ have been achieved. A layout comparison with MOS logic is presented. A possible way of producing faster circuits is proposed.

Journal ArticleDOI
TL;DR: A high-frequency nonlinear model of FET's is developed in which all sources of nonlinearities, including the output conductance, are accounted for, and it is found that fairly good agreement exists at larger signal levels.
Abstract: A high-frequency nonlinear model of FET's is developed in which all sources of nonlinearities, including the output conductance, are accounted for. The distortion resulting from this model is represented using the Volterra series approach, and a high degree of accuracy between the theory and the measured results is obtained. Although the theory holds only for circuits that exhibit a slight deviation from linearity, it is found that fairly good agreement exists at larger signal levels. Harmonic, intermodulation, and cross-modulation distortion (CMD) that occur in a typical high-frequency single-stage FET amplifier are all analyzed and experimentally verified. It is observed that the CMD that occurs in the FET under consideration is of the AM type.

Journal ArticleDOI
TL;DR: It is shown that the finite bandwidths of the amplifiers are analogous to finite negative Q factors of the passive inductance-capacitance LC counterpart, and a technique is proposed for the compensation of the passband deviation that is caused by this effect.
Abstract: The frequency limitation of coupled-biquadratic active ladder structures is derived in terms of the gain-bandwidth products of the operational amplifiers. It is shown that the finite bandwidths of the amplifiers are analogous to finite negative Q factors of the passive inductance-capacitance LC counterpart, and a technique is proposed for the compensation of the passband deviation that is caused by this effect.

Journal ArticleDOI
TL;DR: In this paper, a review of the basic electrode arrangements for various charge-transfer techniques is presented, and some possible layouts for actual devices are described, and the possibilities of building logic arrays and of using two-dimensional arrays in electrooptical systems are also discussed.
Abstract: Charge-transfer arrays with a truly two-dimensional organization in which an element of information contained in a general cell can be moved in more than one direction to an adjacent cell are proposed. After a review of the basic electrode arrangements for various charge-transfer techniques, some possible layouts for actual devices are described. It is shown that simple orthogonal arrays could readily lead to mass serial/parallel converters. Other arrays in which not all unit cells are identical could perform more complicated processing such as mixing operations or passing maneuvers between two fields of information. The possibilities of building logic arrays and of using two-dimensional arrays in electrooptical systems are also discussed. It is concluded that the introduction of additional degrees of freedom into charge-transfer devices increases their versatility and their potential uses, and that technologies are available for the fabrication of two-dimensional arrays.

Journal ArticleDOI
TL;DR: In this paper, a thermal technique of rms measurement is described which uses the base-emitter junction of a bipolar transistor to sense the temperature change of a monolithic chip due to the power dissipation of a companion diffused resistor.
Abstract: A thermal technique of rms measurement is described which uses the base-emitter junction of a bipolar transistor to sense the temperature change of a monolithic chip due to the power dissipation of a companion diffused resistor. An analysis is presented which provides: 1) design equations for performing error compensation to minimize the nonlinearity of the rms-to-dc conversion, and 2) ac feedback network design to optimize the low frequency cutoff and settling time product. Resulting rms converters had midband accuracies of /spl plusmn/0.05 percent of full scale over a dynamic range of 30 dB, high frequency limits of 100 MHz for 2 percent accuracy, and settling times less than 1 s.

Journal ArticleDOI
TL;DR: A computer-aided technique for optimum placement of components at the layout stage so as to achieve zero nominal temperature coefficient in the performance parameter of interest is described, and other practical design considerations, such as optimum choice of stabilized chip temperature, are considered.
Abstract: A generalized temperature-stabilized substrate integrated circuit system containing heat sources and temperature sensors which are distributed in an arbitrary way in two-dimensions over the surface of the chip is analyzed. A computer-aided technique for optimum placement of these components at the layout stage so as to achieve zero nominal temperature coefficient in the performance parameter of interest is described, and other practical design considerations, such as optimum choice of stabilized chip temperature, are considered. The application of this technique is illustrated with the design of a precision temperature stabilized voltage reference supply. Experimental results from this circuit are presented.

Journal ArticleDOI
TL;DR: A detailed investigation of CCD's for application in the optacon reading aid for the blind includes an analysis of the performance of the transparent electrode structure and the CCD scanning circuitry used to realize the new type of image sensor.
Abstract: A detailed investigation of CCD's for application in the optacon reading aid for the blind has been completed. The results of the investigation include an analysis of the performance of the transparent electrode structure and the CCD scanning circuitry used to realize the new type of image sensor.

Journal ArticleDOI
TL;DR: The volatility of information stored in a charge-coupled device can be avoided by storing the information in metal-nitride-oxide-silicon capacitors added to a CCD.
Abstract: The volatility of information stored in a charge-coupled device can be avoided by storing the information in metal-nitride-oxide-silicon capacitors added to a CCD. In the following, the function, layout, and measured results of test circuits are described, and different layouts of such memory circuits are discussed.

Journal ArticleDOI
TL;DR: In this paper, a static frequency divider is presented as an example of a current hogging logic (CHL) circuit, and the transfer characteristics of an AND-NOR gate are discussed.
Abstract: Logic functions of current hogging logic (CHL) are established by switching the lateral injection current in intermediate collector p-n-p structures. High functional density is achieved, since NOR, NAND, and complex gates can readily be realized and all logic elements can be placed within a common isolation region. CHL is fabricated with a standard buried collector process, and hence is compatible with linear bipolar circuits and other bipolar logic families. Current levels are employed as the logical variables, and the transfer characteristics of an AND-NOR gate are discussed. CHL offers high static and dynamic noise immunity. The paper demonstrates a static frequency divider as an example of an CHL circuit.

Journal ArticleDOI
TL;DR: In this article, the use of the diamond cubic crystal structure is described from the aspect of orientation-dependent etching, which can affect device characteristics, device and circuit isolation, circuit element densities, and process control.
Abstract: Advantageous use of the silicon, diamond cubic crystal structure is described from the aspect of orientation-dependent etching. The use of this technology can affect device characteristics, device and circuit isolation, circuit element densities, and process control. Several laboratories have reported advantageous use of }100{ oriented silicon. This paper discusses the advantageous use of both {100} and {110} silicon orientations. In particular, the {110} technology is discussed from a high packing density aspect as applied to the processing and characteristics of silicon diode array targets with improved television blooming control.