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Showing papers in "IEEE Journal of Solid-state Circuits in 1976"


Journal Article•DOI•
TL;DR: An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails.
Abstract: An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 /spl mu/m/spl times/240 /spl mu/m. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 /spl mu/A. The output impedance is 3.2 M/spl Omega/.

1,726 citations


Journal Article•DOI•
TL;DR: An internally compensated differential operational amplifier is described which has been fabricated using n-channel Al-gate MOS technology and has been designed so that its performance is insensitive to process parameters.
Abstract: An internally compensated differential operational amplifier is described which has been fabricated using n-channel Al-gate MOS technology. Only enhancement mode devices are used, and the circuit has been designed so that its performance is insensitive to process parameters.

155 citations


Journal Article•DOI•
TL;DR: A computer program which predicts the DC and transient performance of monolithic integrated circuits in the presence of electrothermal interactions on the integrated circuit die is described and thermal modeling of the die/package structure and the numerical analysis procedure is discussed.
Abstract: A computer program which predicts the DC and transient performance of monolithic integrated circuits in the presence of electrothermal interactions on the integrated circuit die is described. The thermal modeling of the die/package structure and the numerical analysis procedure is discussed. Experimental and simulation results are compared for monolithic operational amplifiers, voltage regulators, and a temperature-stabilized voltage reference.

139 citations


Journal Article•DOI•
TL;DR: In this article, the performance of integrated high-frequency transistors with an arsenic implanted polysil emitter was compared with data of bipolar transistors made with the conventional planar technique, and it was shown that better emitter efficiency higher current carrying capability, and improved emitter-base breakdown can be achieved.
Abstract: Integrated high-frequency transistors (f/SUB T/>3 GHz) with an arsenic implanted polysil emitter have been investigated. The results are compared with data of bipolar transistors made with the conventional planar technique. It is shown that better emitter efficiency higher current carrying capability, and improved emitter-base breakdown can be achieved for transistors with polysil emitters.

136 citations


Journal Article•DOI•
TL;DR: In this article, a multivibrator with an 80-dB dynamic range was used for V-F conversion with high linearity (0.02 percent) using a single low-current supply and can accept millivolt signals.
Abstract: Voltage-to-frequency (V-F) conversion is achieved with high linearity (0.02 percent) using a precise multivibrator with an 80-dB dynamic range. The IC operates from a single, low-current supply and can accept millivolt signals. A unique thermometer output permits direct conversion of temperature to frequency.

80 citations


Journal Article•DOI•
TL;DR: A bipolar monolithic IC temperature transducer with an operating temperature range of -125/spl deg/C to +200/spl Deg/C has been designed, fabricated, and tested and absolute accuracies of 1 /spl mu/A/K under optimum operating conditions are achieved.
Abstract: A bipolar monolithic IC temperature transducer with an operating temperature range of -125/spl deg/C to +200/spl deg/C has been designed, fabricated, and tested. The two-terminal device, which is fabricated using laser trimmed thin-film-on-silicon technology, is a calibrated temperature dependent current source with an average output impedence of 10 M/spl Omega/ over the 3.5-V to 30-V range of input voltage. Overall absolute accuracies of /spl plusmn/0.5/spl deg/C from -75/spl deg/C to +150/spl deg/C have been achieved on a scale of 1 /spl mu/A/K under optimum operating conditions.

74 citations


Journal Article•DOI•
TL;DR: A technique for pulse code modulation encoding according to the 15-segment approximation to the μ-255 nonlinear encoding law makes possible the realization of a one-channel encoder together with the associated sample/hold function as a single NMOS integrated circuit.
Abstract: A technique for pulse code modulation (PCM) encoding according to the 15-segment approximation to the /spl mu/-255 nonlinear encoding law is described. The technique makes possible the realization of a one-channel encoder together with the associated sample/hold function as a single NMOS integrated circuit. The requirements imposed on the individual components for satisfactory system performance are investigated, and it is shown that a performance can be achieved which is comparable with that required in toll quality PCM telephone transmission. Experimental results from a partially integrated prototype are presented.

70 citations


Journal Article•DOI•
TL;DR: Comparison of experimental and theoretical results shows that the model accurately predicts the device I/V characteristics, but the range of validity of the model is limited primarily by high current saturation effects.
Abstract: High-voltage double diffused metal-oxide semiconductor transistors (DMOST's) have been fabricated with drain-source breakdown voltage greater than 200 V. This paper describes an experimental and theoretical study of the current-voltage behavior of these devices leading to a two-component MOS field effect transistor (MOSFET)-resistor model appropriate for computer-aided circuit design. The effects of velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel, and of spreading resistance in the drift region are considered. Parameter extraction for experimentally characterizing these effects is described. Comparison of experimental and theoretical results shows that the model accurately predicts the device I/V characteristics. The range of validity of the model is limited primarily by high current saturation effects.

63 citations


Journal Article•DOI•
TL;DR: The performance of a differential pair with emitter degeneration as a triangle-sine wave converter is analyzed and selection of operating conditions for optimum performance such that total harmonic distortion as low as 0.2 percent has been measured.
Abstract: The performance of a differential pair with emitter degeneration as a triangle-sine wave converter is analyzed. Equations describing the circuit operation are derived and solved both analytically and by computer. This allows selection of operating conditions for optimum performance such that total harmonic distortion as low as 0.2 percent has been measured.

54 citations


Journal Article•DOI•
TL;DR: In this article, the authors discuss the noise measured at the output of a buried channel charge-coupled device (BCCD) linear shift register, which arises from four sources; the electrical insertion of signal charge, the output amplifier, dark current, and bulk state trapping.
Abstract: The authors discuss the noise measured at the output of a buried channel charge-coupled device (BCCD) linear shift register. The measured noise arises from four sources; the electrical insertion of signal charge, the output amplifier, dark current, and bulk state trapping. In making these measurements the concept of correlated double sampling was used in an output circuit which had a noise level which was equivalent to less than 30 noise electrons.

54 citations


Journal Article•DOI•
TL;DR: In this article, a brief review of the noise-generating mechanisms intrinsic to the GaAs FET, an enumeration is given of the various parasitic elements associated with the FET which affect the noise performance.
Abstract: After a brief review of the noise-generating mechanisms intrinsic to the GaAs FET, an enumeration is given of the various parasitic elements associated with the FET which affect the noise performance. These elements include, among others, the gate metallisation and source contact resistances, drain-gate feedback capacitance, and source lead inductance. Numerous graphs are presented to illustrate the effects of these elements and the various design parameters on the noise performance. A comparison is made between the theoretically predicted and the measured noise performance of microwave GaAs FET's. The best state-of-the-art noise performance as reported by various laboratories is illustrated graphically for single-stage and multistage FET amplifiers. Finally, some speculation is attempted in regard to the possible reductions in noise figure to be expected from technological and design improvements of GaAs FET's.

Journal Article•DOI•
TL;DR: The operation and design of 500-stage charge-coupled device (CCD) transversal filters are described and indicate that sample rates from 25 Hz to 10 MHz are possible with a dynamic range approaching 100 dB while retaining high linearity.
Abstract: The operation and design of 500-stage charge-coupled device (CCD) transversal filters are described. The filters have been mask programmed for implementing two spectral analysis techniques: 1) bandpass filtering and 2) Fourier analysis using the chirp z transform (CZT) algorithm. The bandpass filter has a measured fractional 3 dB bandwidth of 0.0108 and 38 dB sidelobe rejection. The dynamic range is 75 dB with less than 45 dB total harmonic distortion. A sliding transform is defined which is useful for calculations of the power spectral density and is shown to be particularly advantageous in a CCD-CZT implementation. Using the sliding transform, a 500-point spectrum is calculated using CCD's with resolutions which can be varied from 1-200 Hz. The dynamic range of the power spectral output was measured to be 80 dB. A discussion is given of the performance limitation of a general CCD filter due to the inherent characteristics of the device. The results are evaluated for the 500-stage devices described above and indicate that sample rates from 25 Hz to 10 MHz are possible with a dynamic range approaching 100 dB while retaining high linearity.

Journal Article•DOI•
TL;DR: A process technology for radiation-hardened CMOS integrated circuits has been defined and the device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.
Abstract: A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.

Journal Article•DOI•
TL;DR: A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed.
Abstract: A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.

Journal Article•DOI•
D.W. Widmann1•
TL;DR: A special lift-off technique for realizing small metal interconnection geometries for integrated circuits is described, and SEM micrographs of Al/Si conductor patterns are presented.
Abstract: A special lift-off technique for realizing small metal interconnection geometries for integrated circuits is described. 0.6-/spl mu/m gaps between metal conductors can be obtained even at 0.8-/spl mu/m metal layer thickness. The slopes of the conductors are tapered. Etching problems inherent in alloy films or sandwiched layers such as Al/Si or Al/Cu/Si are avoided by the technique proposed. SEM micrographs of Al/Si conductor patterns are presented.

Journal Article•DOI•
TL;DR: Using well-known principles a configuration has been developed for an IC reference voltage source with good performance with respect to the temperature dependency and 1/f noise and a bread-board model of this configuration has be tested.
Abstract: Using well-known principles a configuration has been developed for an IC reference voltage source with good performance with respect to the temperature dependency and 1/f noise. A bread-board model of this configuration has been tested. In the temperature range of 0-70/spl deg/C, the output voltage variations were less than /spl plusmn/70 ppm at an output voltage of about 2.5 V and zero load current. Low-frequency noise in a bandwidth 0.003 Hz

Journal Article•DOI•
TL;DR: This work concludes with a description of an associative logic device developed using bipolar technology, which makes possible the efficient realization of multiple output, multilevel, combinational, and sequential networks.
Abstract: While retaining the regular interconnection structure of read-only memory and programmable logic array devices, associative logic makes possible the efficient realization of multiple output, multilevel, combinational, and sequential networks. The extreme versatility of associative logic is provided by internal feedback and matrix segmentation, both characteristic features of the new device. Internal feedback permits networks to be realized in two or more logic levels without the need for external output-input connections. It also makes practical the formation of memory circuits within the matrix. Segmentation permits formation of collinear but functionally independent line segments, thereby improving the areal efficiency of monolithic devices. Consideration of associative logic proceeds from a review of logic implementation by means of memory devices and concludes with a description of an associative logic device developed using bipolar technology.

Journal Article•DOI•
TL;DR: A cascade ratioless circuit configuration is used, which is process compatible with silicon-gate metal-oxide semiconductor (MOS) large-scale integration (LSI) using depletion load MOSTs, which describes a new read-only memory (ROM) with minimum geometry.
Abstract: Describes a new read-only memory (ROM) with minimum geometry. A cascade ratioless circuit configuration is used, which is process compatible with silicon-gate metal-oxide semiconductor (MOS) large-scale integration (LSI) using depletion load MOSTs. The content of a memory cell in the new ROM is determined by the choice of the MOST threshold mode, either an enhancement or depletion mode; this differs from the conventional ROM structure where the content of a memory cell is distinguished by the thickness of gate oxide. The size of a single bit of the ROM is only 196 /spl mu/m/SUP 2/ and is a reduction of 45 percent compared to a conventional silicon-gate ROM.

Journal Article•DOI•
TL;DR: In this paper, laser beam coding of high-speed bipolar silicon integrated circuit memories is described, which is accomplished by the selective vaporization of Ti-Pt links connecting the contact pads of each memory cell to the bit lines.
Abstract: Laser beam coding of high-speed bipolar silicon integrated circuit memories is described. Coding is accomplished by the selective vaporization of Ti-Pt links connecting the contact pads of each memory cell to Ti-Pt-Au bit lines. Vaporized link resistances of >10/SUP 9/ /spl Omega/ can be consistently obtained, with no melting of the adjacent gold patterns. Parameters that have been found to be relevant to the link vaporization process are described including the number of laser pulses per link, beam spot size, thickness of the gold metallization, and pulse energy. The laser coding process is especially useful for applications where relatively small numbers of chips of each of many codes are needed, since only one photolithographic mask set is required.

Journal Article•DOI•
TL;DR: The design of a monolithic operational amplifier, which combines a large bandwidth and a high output current, is described, and provides the possibility for achieving higher output currents.
Abstract: The design of a monolithic operational amplifier, which combines a large bandwidth and a high output current, is described. The output stage is equipped with n-p-n transistors only, biased in class-AB by an internal common-mode feedback loop. The intermediate stage consists of a unity-current-gain split-frequency-band voltage level shift. An integrated version, intended for driving 50-/spl Omega/ coaxial line systems, achieves a bandwidth of 25 MHz and 100-mA output current. The principle described provides the possibility for achieving higher output currents.

Journal Article•DOI•
TL;DR: In this article, a novel circuit configuration for indirect or slope-type analog-to-digital converters is described, which can be implemented in a single low-cost single-polarity MOS chip.
Abstract: A novel circuit configuration for indirect or slope-type analog-to-digital converters (ADC's) is described. Due to the simplicity of the analog requirements, this technique lends itself to implementation in a single low-cost single-polarity MOS chip. A breadboard version has been operated with 11 bit accuracy at a sample rate of 20/s.

Journal Article•DOI•
TL;DR: A macromodel for integrated-circuit comparators, suitable for use with typical present-day (1976) circuit simulators, is presented that can provide up to an order of magnitude reduction in CPU time and matrix size for CAD.
Abstract: A macromodel for integrated-circuit comparators, suitable for use with typical present-day (1976) circuit simulators, is presented. The macromodel can provide up to an order of magnitude reduction in CPU time and matrix size for CAD. Good agreement (typically within 10 percent) between experimental and macromodel transient response parameters is obtained. A detailed macromodel design procedure is presented that enables the macromodel parameters to be found from typical data-sheet or easily-measured parameters.

Journal Article•DOI•
TL;DR: A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package and a special refresh mode is possible in which all 256 sense amplifiers are active, and the entire memory can be refreshed in 64 address cycles.
Abstract: A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The chip size is 145 by 234 mils. A low-power sense amplifier is used for each 64 memory cells. A special refresh mode is possible in which all 256 sense amplifiers are active, and the entire memory can be refreshed in 64 address cycles.

Journal Article•DOI•
TL;DR: Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed, and Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-m-m transistor and for the influences on the current noise margin.
Abstract: High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-p-n transistor and for the influences on the current noise margin. A tradeoff between noise margin and speed is then made. Besides the reduction in delay time, another attractive aspect of this approach is that it allows a simple layout design. By using separate p-n-p and n-p-n transistors, the position of the n-p-n transistors can be adapted to the logic wiring because there is no limitation in the number of crossovers. Some experimental results are given. A minimum value of the propagation delay time of 3 ns has been measured.

Journal Article•DOI•
TL;DR: Experimental and analytical studies suggest that eight of sixteen level operation should be feasible with refresh operations every 0.1 to 1 s; cell area can be under 2 mil/SUP 2/.
Abstract: A memory cell capable of storing multilevel or analog information and providing random-access operation with nondestructive readout has been studied. It uses a single junction field-effect transistor (JFET) as the storage cell. Experimental and analytical studies suggest that eight of sixteen level operation should be feasible with refresh operations every 0.1 to 1 s; cell area can be under 2 mil/SUP 2/. Tracking voltage and current reference circuitry is used to accommodate variations in fabrication processing and operating temperature.

Journal Article•DOI•
TL;DR: Some of the design considerations for charge-transfer split-electrode transversal filters are discussed, and the performance of two low-pass filters using these readout circuits is given.
Abstract: Some of the design considerations for charge-transfer split-electrode transversal filters are discussed. Clock frequency, filter length, and chip area are important design parameters. The relationship of these parameters to filter performance and accuracy is described. Both random and tap weight quantization errors are considered, and the optimum filter length is related to tap weight error. A parallel charge-transfer channel, which balances both capacitance and background charge, and a coupling diffusion between split electrodes greatly improves accuracy. A one-phase clock is used to simplify the readout circuitry. Two off-chip readout circuits are described, and the performance of two low-pass filters using these readout circuits is given. Signal to noise ratios of 90 dB/kHz and an overall linearity of 60 dB have been achieved with this readout circuitry.

Journal Article•DOI•
TL;DR: In this paper, the parametric performance of the I/SUP 2/L structure for common linear circuit voltages was studied. But the performance was limited to three and gate delay to 100 ns for the process which attained 30-V breakdowns.
Abstract: The processing, a.c. and d.c. characteristics of I/SUP 2/L structures integrated with common analog circuit elements are studied. Since the required breakdown voltage of the analog circuitry normally dictates the resistivity and thickness of the silicon epitaxial layer, the authors studied the parametric performance of the I/SUP 2/L structure for common linear circuit voltages. Design criteria, processing, and device performance are presented for I/SUP 2/L structures built on several different types of material. The I/SUP 2/L performance achieved in the linear compatible technology easily allowed a fan-out of four and gate propagation delay less than 50 ns with standard device breakdowns of 20 V; but fan-out is limited to three and gate delay to 100 ns for the process which attained 30-V breakdowns.

Journal Article•DOI•
F. Barson1•
TL;DR: By far the most interesting, and the most troublesome, incidence of emitter-collector shorts is that due to "pipes."
Abstract: Although emitter-collector shorts may result from a number of processing problems, the phenomenon known as `pipes' represents one of the most interesting and most troublesome sources of such electrical shorts in bipolar circuits. In this review paper, several observations on the nature and causes of pipes are discussed, as well as means to evaluate their incidence and to control their occurrence.

Journal Article•DOI•
TL;DR: It appears that geometries of about 1 /spl mu/m lead to the best compromise for fast switching and optimized LSI organization.
Abstract: Using a simple channel implantation step, the choice of the threshold voltage determines speed and power. Illustrations are given by the example of a 3-input NOR-gate with 1/spl times/5-/spl mu/m/SUP 2/ channel geometry for the switching transistors. A design with dual threshold voltages allowing the optimization of power consumption while keeping subnanosecond propagation delay times is presented and applied to a speed- and power-optimized dual-type MESFET NOR-gate. Examples are presented of experimental d.c. characteristics measured on fabricated samples exhibiting an average power consumption of 150 /spl mu/W. A propagation delay time of 0.8 ns is deduced for a fan-out of 3. This performance is discussed in conjunction with a set of parameters including geometry, technological reproducibility, and circuit design requirements. It appears that geometries of about 1 /spl mu/m lead to the best compromise for fast switching and optimized LSI organization.

Journal Article•DOI•
TL;DR: The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate and possesses significant advantages in packing density and potentially higher yield.
Abstract: A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAM's.