# Showing papers in "IEEE Journal of Solid-state Circuits in 1979"

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IBM

^{1}TL;DR: In this paper, the important design parameters relating to Drain-Induced Barrier lowering (DIBL) are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results.

Abstract: Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.

206Â citations

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IBM

^{1}TL;DR: In this article, the impurity doping profile of the transistor was optimized to optimize the performance of the logic circuit at a specific power dissipation level and a given lithographic line width.

Abstract: This design optimization scheme provides a procedure for tailoring the impurity doping profile of the transistor so that the performance of the logic circuit can be optimized at a specific power dissipation level and a given lithographic line width. It is shown that the condition of the optimized circuit performance dictates a set of relationships between the transistor structure, the logic voltage swing, and the value of the circuit elements. This paper further discusses the relation between the circuit properties and the transistor size, which becomes smaller as the lithography advances. It is concluded that as the horizontal dimensions are reduced, the vertical dimension of the transistor must be reduced, the impurity density increased, and the current density increased in order to increase the circuit speed. A simple relationship between the lithographic line width and the vertical structure is given which enables one to predict the power-speed performance for the reduced structure.

175Â citations

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TL;DR: In this article, a voltage source that is proportional to absolute temperature (PTAT) was proposed. But the voltage source was not designed to operate down to 1.3 V with a current drain below 1 /spl mu/A.

Abstract: The CMOS bandgap voltage reference described here uses the bipolar substrate-transistor and the bipolar-like source-to-drain transfer characteristics of MOS transistors in weak inversion to implement a voltage source that is proportional to absolute temperature (PTAT). A first version of PTAT source is derived from a circuit described previously. A second version is based on a novel cell that can be stacked to obtain the desired voltage. Both versions operate down to 1.3 V with a current drain below 1 /spl mu/A. A stability of 3 mV over 100/spl deg/C has been obtained with a few nonadjusted samples. Experimental results suggest some possible improvements to extend this stability to every circuit.

163Â citations

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ETH Zurich

^{1}TL;DR: Techniques for improving the gain of MOS amplifiers are discussed and an experimental single stage amplifier was realized using CMOS transistor arrays which achieved gain of 3200.

Abstract: Techniques for improving the gain of MOS amplifiers are discussed. These techniques depend on technology used. An experimental single stage amplifier was realized using CMOS transistor arrays which achieved gain of 3200.

122Â citations

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TL;DR: Standard process CMOS/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A/D converter that may be interconnected in series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates.

Abstract: Standard process CMOS/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A/D converter. Two chips may be interconnected in a series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates. Design factors and accuracy requirements are reviewed.

121Â citations

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TL;DR: A new successive approximation analog-to-digital conversion technique compatible with most MOS process technologies is described, which combines a string of equal value diffused resistors and a binary ratioed capacitor array in a unique circuit configuration so that 12-bit monotonicity is achieved with only 8-bit ratio-accurate circuit elements.

Abstract: A new successive approximation analog-to-digital conversion technique compatible with most MOS process technologies is described. This technique combines a string of equal value diffused resistors and a binary ratioed capacitor array in a unique circuit configuration so that 12-bit monotonicity is achieved with only 8-bit ratio-accurate circuit elements. The comparator is realized by a chopper-stabilized amplifier to reduce the inherently high input offset voltages of MOS amplifiers. Typical performance characteristics taken from a sample of ICs are presented; 12-bit monotonic conversion with differential nonlinearity less than 1/2 LSB is completed in 50 /spl mu/s. The die area, less logic, is 12000 mil/SUP 2/. Because of assured 12-bit monotonicity, this converter should find applications of closed-loop control systems. It seems feasible to extend this technique to 14-bit resolution for use in applications such as digital audio systems.

107Â citations

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Philips

^{1}TL;DR: It is found that the dynamic noise margins increase for shorter noise pulses; a first-order explanation of this phenomenon is given.

Abstract: Explaining four basic types of noise, and by showing the various methods, together with boundary conditions, which can be used to find the worst case noise margins A flip-flop setup is advised which can be used for measurements and computer simulations, both for static and dynamic noise margins Also configurations with fan-in and fan-out larger than 1 can be handled with this flip-flop method In general, it is found that the dynamic noise margins increase for shorter noise pulses; a first-order explanation of this phenomenon is given Also, energy noise margins are considered The theoretical considerations are completed with computer simulations and measurements of the static and dynamic noise margins of integrated Schottky logic (ISL), as an example

103Â citations

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TL;DR: A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit which results in a fully integrable A/ D function.

Abstract: A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit. The small delay in the new circuit allows digital signal sampling by latching comparators. A sample and hold unit is not needed which results in a fully integrable A/D function. Analog input signals up to 5 MHz can be digitally sampled with sampling frequencies up to 50 MHz. A double layer metallization process is used to reduce the die size to 2.4/spl times/2.5 mm.

86Â citations

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TL;DR: In this paper, the structure of a complete process simulator for modeling IC technologies is described, which includes ion implantation, oxidation, diffusion, epitaxy, and etching can be simulated.

Abstract: The structure of a complete process simulator for modelling IC technologies is described. Multiple-step sequences which include ion implantation, oxidation, diffusion, epitaxy, and etching can be simulated. Features of individual process models for each of the steps are described in detail. Special emphasis is given to extrinsic diffusion phenomena for arsenic and phosphorus including coupling to boron. The kinetics of oxidation including concentration dependence and interaction of oxide growth with impurity migration are considered as well as the segregation phenomena. The problem of segregation for moving boundary problems in general is reviewed. As example, a bipolar process development using both surface deposition and implanted-phosphorus emitters is presented. Experimental results show that profile shapes, junction depths, and integrated base doping are extremely sensitive to the emitter diffusion as predicted by simulation.

80Â citations

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IBM

^{1}TL;DR: In this article, the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFETs is discussed, and the effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data.

Abstract: The authors discuss the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFETs. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.

79Â citations

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TL;DR: The filter is designed so that binary changes in the sampling frequency provide new sets of center frequencies which smoothly continue the logarithmic progression, and the accuracy and reproducibility inherent in the switched capacitor approach are retained.

Abstract: Techniques are presented for the design of a second-order switched capacitor filter which has its frequency response parameters programmed by the application of digital control signals. Two different types of weighted capacitor arrays are used to achieve programmability in the center frequency, peak gain, and selectivity. Experimental results are given for an integrated NMOS version with eight logarithmically-spaced center frequencies programmed by a 3 bit digital word, and 64 Q and gain values programmed by two 6 bit words. The filter is designed so that binary changes in the sampling frequency provide new sets of center frequencies which smoothly continue the logarithmic progression. Since the response depends on monolithic MOS capacitor ratios, the accuracy and reproducibility inherent in the switched capacitor approach are retained.

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TL;DR: The direct form switched-capacitor offers some useful advantages in comparison to the switched-Capacitor integrator approach, including the rejection of MOS amplifier noise and power supply noise below one-half the sampling rate, less silicon area especially when implementing high Q poles, and potential for multiplexing two or more filters.

Abstract: A new technique enabling the integration of audio frequency filters using standard MOS technology is described. This approach uses ratioed MOS capacitors, MOS amplifiers and switches to realize precision multiplication, summation, and delay functions. With these elements an analog sampled-data direct-form recursive filter, having the general biquadratic transfer function, was integrated in MNOS technology. This filter had a Q=19/spl plusmn/1 without external trimming and it could be electrically programmed into low-pass, bandpass, and high-pass responses. This biquadratic section can be used as a building block for higher order filters. The direct form switched-capacitor offers some useful advantages in comparison to the switched-capacitor integrator approach. These are the rejection of MOS amplifier noise and power supply noise below one-half the sampling rate, less silicon area especially when implementing high Q poles, and potential for multiplexing two or more filters.

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TL;DR: The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's.

Abstract: Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.

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TL;DR: A simple micropower CMOS bandgap voltage reference is described, which utilizes MOS devices operating in the weak inversion region in conjunction with a process compatible bipolar device.

Abstract: A simple micropower CMOS bandgap voltage reference is described. The reference utilizes MOS devices operating in the weak inversion region in conjunction with a process compatible bipolar device. The voltage reference is insensitive to threshold and mobility variations and is independent of the slope factor which characterizes weak inversion.

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TL;DR: A two-stage weighted capacitor network for A/D and D/A conversion utilizing a feedback amplifier and a discussion of the comparative accuracy and area of one- and two- stage weighted capacitor DAC's on the basis of capacitor tracking is given.

Abstract: A two-stage weighted capacitor network for A/D and D/A conversion utilizing a feedback amplifier is described. The two-stage weighted capacitor DAC requires a smaller range of capacitor values then the conventional weighted capacitor DAC and is not subject to the nonlinear effects of parasitic capacitance. Experimental results of such a DAC implemented using a conventional n-channel metal-gate MOS process are presented. A discussion of the comparative accuracy and area of one- and two-stage weighted capacitor DAC's on the basis of capacitor tracking is given.

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IBM

^{1}TL;DR: In this paper, an alternative approach which combines a doped polycrystalline silicon layer with a high-conductivity metal silicide such as WSi/SUB 2/ (polycide) is described.

Abstract: For pt.VI see ibid., vol.SC14, no.2, p.282 (1979). A major limitation of polycrystalline silicon as a gate material for VLSI applications is its limited conductivity which restricts its usefulness as an interconnection level. An alternative approach which combines a doped polycrystalline silicon layer with a high-conductivity metal silicide such as WSi/SUB 2/ (polycide) is described. Such polycide layers are demonstrated to provide at least an order of magnitude improvement in interconnection resistance relative to polycrystalline silicon while maintaining the reliability of the polycrystalline silicon gate and the ability to form passivating oxide layers under typical polycrystalline silicon processing conditions.

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TL;DR: In this paper, a family of novel Josephson logic circuits called current injection logic (CIL) is presented, which combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities.

Abstract: A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations.

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Hitachi

^{1}TL;DR: In this article, the analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification.

Abstract: An approximate analytical solution for the surface potential is used to derive the threshold voltage. It is shown that the surface potential depends exponentially on the distance from the drain, and this causes the threshold voltage to decrease exponentially with decreasing channel length. The analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification. The breakdown voltage of a short-channel n-MOSFET is lowered by a positive feedback effect of excess substrate current. From two-dimensional analysis of this mechanism, a simple expression of the breakdown voltage is derived. Using this model, the scaling down of MOSFETs is discussed. The simple models of threshold and breakdown voltage of short-channel MOSFETs are helpful both for circuit-oriented analysis and process diagnosis where statistical use of the model is often needed.

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TL;DR: Two illustrative systems are analyzed in detail: a RAM-based system and an associative system; it is shown that in each case an optimum design is possible using the area-time product as a cost function.

Abstract: Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic silicon chip. Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths place a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of the many alternative structures. Two illustrative systems are analyzed in detail: a RAM-based system and an associative system. It is shown that in each case an optimum design is possible using the area-time product as a cost function.

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TL;DR: It is found that the effects of AC crowding and nonlinearity combine to cause DC crowding where the new rectification induced DC current distribution favors the perimeter of the emitter.

Abstract: Describes the rectification response of a bipolar transistor to a small AC signal applied at the base. An RC transmission line model based upon device material and geometrical properties is used to calculate the AC voltage distribution across the emitter. Small changes in the DC operating point at each location across the emitter are then calculated and summed to obtain the terminal characteristic. It is found that the effects of AC crowding and nonlinearity combine to cause DC crowding where the new rectification induced DC current distribution favors the perimeter of the emitter. A model based upon the hybrid pi format is found to be consistent with RF distribution and resultant crowding equations. Also, it is shown how a high frequency rectification response measurement, which, because of severe AC crowding, is edge sensitive, may be used to study recombination near the edge of the emitter.

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TL;DR: In this paper, the design and measured performance of a fully parallel monolithic 8-bit A/D converter with a triple-diffused technology was described, and the required comparators and combining logic were designed and fabricated with a standard high-performance triple-differentiated technology.

Abstract: The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.

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TL;DR: A monolithic 14-bit D/A converter using `dynamic element matching' to obtain a high accuracy and good long-term stability is described.

Abstract: A monolithic 14-bit D/A converter using `dynamic element matching' to obtain a high accuracy and good long-term stability is described. Over a temperature range from -50/spl deg/ to 70/spl deg/C the nonlinearity is less than one-half least significant bit (/SUP 1///SUB 2/LSB). Dynamic tests show a distortion at a level of about -90 dB with respect to the maximum sinewave output. Nearly no glitches are found, so the converter can be operated without a deglitcher circuit. The chip, with a size of 3.1/spl times/3.2 mm, contains all elements needed, except the output amplifier and digital input latches.

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TL;DR: Experimental results show the one-chip PCM codec circuit to meet accepted requirements and operate with very low power requirements.

Abstract: Describes a one-chip PCM codec circuit which has been implemented in the CMOS process. The design uses two separate linear digital-to-analog converters, made with charge redistribution techniques. Experimental results show the circuit to meet accepted requirements and operate with very low power requirements.

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TL;DR: In this article, three switched-capacitor circuits are described which perform all filtering functions in a PCM voice CODEC, which use novel integrators and/or state-variable sections, which desensitize the overall response against stray capacitance effects.

Abstract: Three switched-capacitor circuits are described which perform all filtering functions in a PCM voice CODEC. They use novel integrators and/or state-variable sections, which desensitize the overall response against stray-capacitance effects. All filters are fully integrated on a CMOS test chip. The basic design considerations and the measured performance are discussed.

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IBM

^{1}TL;DR: In this article, the capabilities of technology are viewed in the perspective of the problems to provide a forecast of the levels of integration that will be found in large computing systems, and some more speculative system assumptions are used to estimate the performance of the systems.

Abstract: Technological trends are extrapolated to the end of this century. Problems of utilizing high levels of integration are noted, and the capabilities of technology are viewed in the perspective of the problems to provide a forecast of the levels of integration that will be found in large computing systems. A physical model and some more speculative system assumptions are used to estimate the performance of the systems. The physical characteristics forecast for the system are summarized.

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TL;DR: Integrated Schottky logic (ISL) as mentioned in this paper is a new 200 mV voltage-swing LSI logic that can be made in standard Schottkey processes with a double-layer metallization.

Abstract: Integrated Schottky logic (ISL) is a new 200 mV voltage-swing LSI logic that can be made in standard Schottky processes with a double-layer metallization. It fills the gap between low-power Schottky TTL and I/SUP 2/L for those circuits where low-power Schottky TTL consumes too much power and takes up too much chip area, and when I/SUP 2/L does not attain the required speed. An ISL gate consists of a current source and a set of Schottky output diodes (wired AND gate). Minimum propagation delay times of 2.7 ns at 200 /spl mu/A/gate are obtained, with a speed-power product of 1.2 pJ. The packing density of ISL is 120 to 180 gates/mm/SUP 2/. The logic can be combined with ECL, I/SUP 2/L, and TTL on the same chip, and can also be made in analog processes.

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TL;DR: Wu et al. as discussed by the authors proposed a new type of the NELS (n-channel enhancement mode list of SYMROI,S with load operated at saturation)-connected A-type differential negative resistance MOSFET, using the merged integrated circuit of a NELS inverter and an n-channel MOS driver.

Abstract: A new type of the NELS (n-channel enhancement mode LIST OF SYMROI,S with load operated at saturation)-connected A-type differential negative resistance MOSFET, using the merged integrated circuit of a NELS inverter and an n-channel enhancement MOS driver, is studied both experimentally and theoretically. The principal operation of the lambda MOSFET device is characterized by the simple circuit model and device physics. The important deviceproperties, such as the peak voltage, the peak current, the vafley voltage, and the negative resistance, are derived in terms of the known device parameters. Comparisons between characteristics of the fabricated device and the theoretical model are made, which show the theoretical anaiyses are in good agreement with the observed device characteristics. Manuscript received December 8, 1978; revised June 22, 1979.This research was supported by the Natiomd Sciences Council, Republic of China, under Contract NSC-65E-0404-04 (01). The authors are with the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, Republic of China. co Go Gol G02 G03 Gr IDs IP IU K L NA Q,, QB Gate oxide capacitance per unit area. Drain-to-source conductance with zero drain voltage. Go of transistor Q 1 for the NELS-connected structure. Go of transistor Q2 for the NELS-connected structure. GO of transistor Q3 for the NELS-connected structure. Ratio of G02 and GO~. Drain-source current. Peak current. Valley current. Modifying substrate factor. Channel length. Doping concentration of p-type substrate. Surface state charge density. Surface depletion layer charge density. 0018-9200/79/1 200-1094$00.75 @ 1979 IEEE WU AND LAI: NEGATIVE RESISTANCE MOSFET DEVICE 1095 Electronic charge. Negative differential resistance. Drain-source bias voltage. Flat-band voltage of MOS capacitor. Gate-source bias voltage. Applied gate voltage for the NELS-connected structure. Peak voltage. Threshold voltage. Valley voltage. Channel width. The potential difference between Fermi-potential and the intrinsic potential of p-type substrates at the flatband condition. Metal-semiconductor work function difference,, Dielectric permittivity of silicon substrate. Surface mobility of the electron. Field effect mobility.

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TL;DR: Experimental results show the circuit to meet accepted requirements of the monolithic voice CODEC.

Abstract: Architecture and design of a monolithic voice CODEC is described. The CODEC consists of 2 chips-the transmit chip includes the companding coder (nonlinear A/D) along with filtering functions, and the receive chip consists of the expanding decoder (nonlinear D/A) chip with its smoothing filter. Experimental results show the circuit to meet accepted requirements.

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TL;DR: In this article, an approach was described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions, based on measurements of the injection current as a function of voltage and from long-term stress experiments.

Abstract: For pt.III see ibid., vol.SC14, no.2, p.255 (1979). An approach is described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions. The approach was followed in determining the room-temperature and the 77K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 /spl mu/m. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments.

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TL;DR: Equivalent input noise voltages of MOS amplifiers working in a low-frequency range have been calculated in the three basic technologies, i.e., single-channel enhancement-load, single- channel depletion-load and CMOS.

Abstract: Equivalent input noise voltages of MOS amplifiers working in a low-frequency range have been calculated in the three basic technologies, i.e., single-channel enhancement-load, single-channel depletion-load and CMOS. Means of reducing that noise are discussed and practical results given for CMOS technology.