scispace - formally typeset
Search or ask a question

Showing papers in "IEEE Journal of Solid-state Circuits in 1982"


Journal Article•DOI•
R.H. Krambeck1, C.M. Lee1, H.-F.S. Law1•
TL;DR: A new circuit type, the CMOS domino circuit, is described, which involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once.
Abstract: Characteristics of various CMOS and NMOS circuit techniques are described, along with the shortcomings of each. Then a new circuit type, the CMOS domino circuit is described. This involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once. As a result, complex clocking schemes are not needed and the full inherent speed of the dynamic gate can be utilized. The circuit is most valuable where gates are complex and have high fan-out such as in arithmetic units. Examples are shown of the use of domino circuits in an 8-bit ALU, where simulations indicate a speed advantage of 1.5 to 2 over traditional circuits, and in a 32-bit ALU where a worst case add in 124 ns was projected and a time less than 100 ns was achieved.

502 citations


Journal Article•DOI•
TL;DR: In this paper, an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level is presented, focusing on CMOS amplifiers because of their more widespread use.
Abstract: Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar-derived two-stage architecture. Alternative circuit approaches for optimization of particular performance aspects are summarized, and examples are given.

493 citations


Journal Article•DOI•
TL;DR: In this paper, two transconductance amplifiers are presented in which the concept of an input dependent bias current has been introduced, and the amplifiers combine a very low standby power dissipation with a high driving capability.
Abstract: Two transconductance amplifiers are presented in which the concept of an input dependent bias current has been introduced. As a result, these amplifiers combine a very low standby power dissipation with a high driving capability. The first amplifier, suited for SC filters, is fairly small (0.075 mm/SUP 2/) and has a slew rate which is more than an order of magnitude better than micropower amplifiers presented earlier. The second amplifier can be used as a micropower buffer. Nearly the whole supply current is used to charge the load capacitor so that this amplifier has a high efficiency.

284 citations


Journal Article•DOI•
TL;DR: In this paper, a precision CMOS voltage comparator circuit is proposed to provide stable supply-independent DC bias voltages and controlled internal voltage swings for the comparator, and an actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparators for applications in differential A/D converter systems.
Abstract: Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings for the comparator. These techniques are necessary in order to eliminate harmful bootstrapping effects which can potentially occur in all AC coupled MOS analog circuits. An actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparator for applications in differential A/D converter systems. A general approach for selecting the gain in AC-coupled gain stages is also presented. The comparator circuit has been implemented in a standard metal-gate CMOS process. The measured comparator resolution is less than 1 mV, and the allowable supply voltages range from 3.5 to 10 V.

187 citations


Journal Article•DOI•
J. Fischer1•
TL;DR: The noise response of switched capacitor networks is reviewed with emphasis on simplifying approximations suitable for SPICE noise simulation, which shows close agreement between predicted and measured noise responses for several monolithic SCNs.
Abstract: The noise response of switched capacitor networks (SCNs) is reviewed with emphasis on simplifying approximations suitable for SPICE noise simulation. The techniques developed cover all op-amp noise sources, as well as capacitor switching noise. The close agreement between predicted and measured noise responses for several monolithic SCNs bears out the validity of these simulation techniques.

170 citations


Journal Article•DOI•
TL;DR: A new NMOS PCM codec filter uses low-noise fully differential circuits to achieve supply rejection of 36 dB and idle channel noise of 6 dB/SUB rnc0/.
Abstract: A new NMOS PCM codec filter uses low-noise fully differential circuits to achieve supply rejection of 36 dB and idle channel noise of 6 dB/SUB rnc0/. The die size is 24 mm/SUP 2/ and the active standby power is 150 mW/5 mW.

166 citations


Journal Article•DOI•
TL;DR: In this paper, the effects of random edge variations and deviations of oxide thickness and permittivity are examined, and it is shown that edge effects introduce a relative capacitance error /spl Delta C/C/spl alpha C/SUP -3/4/, while the oxide variations cause /spl C/c/spl α C/ SUP -1/2/.
Abstract: The effects of random edge variations and deviations of oxide thickness and permittivity are examined. Making only a few basic assumptions, it is shown that edge effects introduce a relative capacitance error /spl Delta/C/C/spl alpha/C/SUP -3/4/, while the oxide variations cause /spl Delta/C/C/spl alpha/C/SUP -1/2/. Error bounds are derived for C in terms of the variances of the linear dimensions and oxide permittivity. For a capacitor C realized as a parallel connection of n unit capacitors of values C/n, the relative error caused by edge effects is n/SUP 1/4/ times larger than for a single capacitor of value C. The relative error due to oxide variations remains the same for the two realizations. All theoretical results agree with physical consideration, as well as the Monte Carlo simulations performed.

153 citations


Journal Article•DOI•
TL;DR: Calculations of time delay for interconnections made of poly-Si, WSi2, W, and Al indicate that as the chip area is increased and other device-related dimensions are decreased the interconnection time delay becomes significant compared to the device time delay and in extreme cases dominates the chip performance.
Abstract: Effect of scaling of dimensions, i.e., increase in chip size and decrease in minimum feature size, on the RC time delay associated with interconnections in VLSIC's has been investigated. Analytical expressions have been developed to relate this time delay to various elements of technology, i.e., interconnection material, minimum feature size, chip area, length of the interconnect, etc. Empirical expressions to predict the trends of the technological elements as a function of chronological time have been developed. Calculations of time delay for interconnections made of poly-Si, WSi/sub 2/, W, and Al have been done and they indicate that as the chip area is increased and other device-related dimensions are decreased the interconnection time delay becomes significant compared to the device time delay and in extreme cases dominates the chip performance.

139 citations


Journal Article•DOI•
TL;DR: A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented, and closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.
Abstract: A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented. A simple closed-form expression for the variation of threshold voltage as a function of drain voltage, substrate bias, channel length, oxide thickness, and channel doping is derived. An exponential dependence on channel length and a linear dependence on drain and substrate biases is prediced for the reduction in the short-channel threshold voltage. These results are in qualitative and quantitative agreement with simulated and experimental results reported in literature. The predictions for the threshold voltage and subthreshold drain current are in close agreement with measured characteristics of MOS transistors down to submicron dimensions. The closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.

138 citations


Journal Article•DOI•
TL;DR: In this article, a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology is described, which is intended for use as a sample and hold amplifier for low level signals in data acquisition systems.
Abstract: Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.

113 citations


Journal Article•DOI•
TL;DR: A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips based on a model for the distribution of faults on a chip, which implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment.
Abstract: A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips. It is based on a model for the distribution of faults on a chip. The model requires two parameters, the average number (n/SUB 0/) of faults on a faulty chip and the yield (y) of good chips. It is assumed that the yield either is known or can be calculated from the available formulas. The other parameter, n/SUB 0/, is determined from an experimental procedure. Once the model is fully characterized, it allows calculation of the field reject rate as a function of the fault coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example.

Journal Article•DOI•
S. Liu1, L.W. Nagel1•
TL;DR: Presents first-order large-signal MOSFET models and derives corresponding small-Signal models, related to operating-point bias and to the parameters of the IC process used to fabricate the device, and explores the impact upon small- signal performance of many second-order effects present in small-geometry MOSfETs.
Abstract: Presents first-order large-signal MOSFET models and derives corresponding small-signal models. The parameters of the small-signal models are related to operating-point bias and to the parameters of the IC process used to fabricate the device. The impact upon small-signal performance of many second-order effects present in small-geometry MOSFETs is explored. A representative analog circuit, fabricated with a 1 /spl mu/m feature-size NMOS technology, is analyzed using the small-signal models derived. Results of approximate analysis, without the use of computer aids, are compared with detailed computer simulation results.

Journal Article•DOI•
TL;DR: The settling behavior of a pole-splitting compensated operational amplifier is analyzed using a second-order (two-pole) transfer function and it is shown that although the slewing period of the amplifier is well approximated by the commonly used formula for slew rate, the settling behavior after theslewing period can only be fully explained using asecond-order transfer function.
Abstract: The settling behavior of a pole-splitting compensated operational amplifier is analyzed using a second-order (two-pole) transfer function. It is shown that although the slewing period of the amplifier is well approximated by the commonly used formula for slew rate, the settling behavior after the slewing period can only be fully explained using a second-order transfer function. Simple criteria relating the circuit parameters to the damping ratio of a second-order feedback system are given. Analytical expressions for the amplifier responses and settling times are derived. The analysis is justified by close correspondence with computer simulations.

Journal Article•DOI•
TL;DR: In this paper, a bandgap-voltage reference implemented with a new accurate circuit configuration for compensating the thermal nonlinearity of the base-emitter voltage is described, achieving a temperature coefficient of 0.5 ppm/spl deg/C over the temperature range -25 to +85/spl/C.
Abstract: A bandgap-voltage reference implemented with a new accurate circuit configuration for compensating the thermal nonlinearity of the base-emitter voltage is described. With this device, a temperature coefficient of 0.5 ppm//spl deg/C over the temperature range -25 to +85/spl deg/C has been achieved. The minimum required supply voltage amounts to only 5.5 V.

Journal Article•DOI•
TL;DR: A bipolar monolithic microsystem is described which provides direct analog synthesis of all trigonometric functions and their inverses, based on the ratio of two sines, generated by a novel sine-shaping network.
Abstract: A bipolar monolithic microsystem is described which provides direct analog synthesis of all trigonometric functions and their inverses. The new technique is based on the ratio of two sines, generated by a novel sine-shaping network. The circuit offers high accuracy and 1.5 MHz bandwidth in an easily programmed 16-pin DIP.

Journal Article•DOI•
Paul J. Tsang1, S. Ogura1, W.W. Walker1, J.F. Shepard1, D.L. Critchlow1 •
TL;DR: A fabrication process for the Lightly Doped Drain/Source Field Effect Transistor, LDDFET, that utilizes RIE produced SiO/sub 2/ sidewall spacers is described in this paper.
Abstract: A fabrication process for the Lightly Doped Drain/Source Field-Effect Transistor, LDDFET, that utilizes RIE produced SiO/sub 2/ sidewall spacers is described. The process is compatible with most conventional polysilicon-gated FET processes and needs no additional photo-masking steps. Excellent control and reproducibility of the n/sup -/ region of the LDD device are obtained. Measurements from dynamic clock generators have shown that LDDFET's have as much as 1.9x performance advantage over conventional devices.

Journal Article•DOI•
TL;DR: Presents a synchronous solution for clocking VLSI systems organized as distributed systems to resynchronize the phase of each module clock on the transitions of the communication clock by a phase locked loop circuitry added to each module.
Abstract: Presents a synchronous solution for clocking VLSI systems organized as distributed systems. This solution avoids the drawbacks of the self-timed approach. These VLSI systems are constituted of modules which represent synchronous areas driven by their own fast clock, interconnected by a synchronous communication mechanism driven by a slow clock. In order to avoid the risk of metastability in flip-flop between the modules and the communication mechanism, the author suggests to resynchronize the phase of each module clock on the transitions of the communication clock by a phase locked loop circuitry added to each module.

Journal Article•DOI•
J.O. Voorman1, W.H.A. Bruls1, P.J. Barth1•
TL;DR: In this paper, the integration of electronic transconductors and capacitors has been used to simulate inductor capacitors for analog low-pass filters, which are on-chip compatible with analog and digital parts.
Abstract: Monolithic analog filters are described which are based on the integration of electronic transconductors and capacitors. The method used allows simulation of inductor capacitor filters. The transconductors are voltage-controlled current sources provided with a scaling multiplier. The value of one external resistor and matching of integrated elements determine the transconductances. Capacitors are made with an oxide/nitride dielectric on the low-ohmic emitter diffusion and with an aluminium top electrode. Applications include PCM low-pass filters, viewdata modem filters, etc. The method is extendable from the audio band up to video frequencies. Simple breadboarding, no need for special CAD, and an extremely low supply power consumption are features of the filter type. The filters are on-chip compatible with analog and digital system parts.

Journal Article•DOI•
TL;DR: A four-quadrant NMOS analog multiplier, which achieves linearity better than 0.3 percent at 75 percent of full-scale swing, a bandwidth of DC to 1.5 MHz, and output noise 77 dB below full scale is described.
Abstract: A four-quadrant NMOS analog multiplier, which achieves linearity better than 0.3 percent at 75 percent of full-scale swing, a bandwidth of DC to 1.5 MHz, and output noise 77 dB below full scale is described. Active area is 450 mils/SUP 2/.

Journal Article•DOI•
TL;DR: Conditions are outlined under which propagation delays in VLSI circuits can be achieved that are logarithmic in the wire lengths, imposed by area requirements and the velocity of light.
Abstract: Conditions are outlined under which propagation delays in VLSI circuits can be achieved that are logarithmic in the wire lengths. These conditions are imposed by area requirements and the velocity of light.

Journal Article•DOI•
R.W. Keyes1•
TL;DR: Characteristics of a chip that is physically dominated by wires are examined and it is found that high integrated complex logic chips contain large amounts of wiring.
Abstract: Highly integrated complex logic chips contain large amounts of wiring. Characteristics of a chip that is physically dominated by wires are examined.

Journal Article•DOI•
TL;DR: In this paper, the authors investigated the dependence of channel hot-carrier generation on MOSFET structure by measuring the gate current and the substrate current as low as on the order of 10/sup -15/ A and showed that the measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO/sub 2/ energy barrier.
Abstract: This paper reports on investigation of channel hot-carrier generation for various device structures The dependence of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10/sup -15/ A The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO/sub 2/ energy barrier The substrate current due to hot-hole injection into the substrate is also modeled analytically On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons

Journal Article•DOI•
TL;DR: A set of three processor chips capable of performing 32 and 64 bit floating point add/subtract, multiply, and divide operations, designed for use in Hewlett-Packard computer and instrument systems.
Abstract: Describes a set of three processor chips capable of performing 32 and 64 bit floating point add/subtract, multiply, and divide operations. The chips can perform over one million scalar floating point operations per second, and over four million vector operations per second. The set is implemented in a four micron CMOS-on-sapphire process. Each chip has between 30000 and 60000 devices, and is about 250 mils on a side. Although asynchronous data paths are used within the chips, their interface to external system buses is synchronous with a maximum data bandwidth of over 70 Mbytes/s. The set has been designed for use in Hewlett-Packard computer and instrument systems.

Journal Article•DOI•
T.R. Viswanathan, S. Murtuza1, V.H. Syed1, J. Berry1, M. Staszel1 •
TL;DR: A novel approach to digital transduction of physical quantities using a switched-capacitor frequency control loop is presented and a few applications are outlined with supporting experimental results.
Abstract: A novel approach to digital transduction of physical quantities using a switched-capacitor frequency control loop is presented. The operation of the loop as well as its properties are explained. A few applications are outlined with supporting experimental results.

Journal Article•DOI•
TL;DR: The authors have analyzed in detail the propagation of signals on disperse lines and concluded that both current and projected silicon technologies fall within the realm of the capacitive model where a dispersive line can be replaced by a capacitance proportional to its length.
Abstract: Evaluates various proposed VLSI models of computation. While there is a consensus on the appraisal of chip area, controversy remains with regard to computation time. Thus, the authors have analyzed in detail the propagation of signals on disperse lines. The results are expressed in terms of adimensional parameters characteristic of any given fabrication technology. The conclusion is that both current and projected silicon technologies fall within the realm of the capacitive model where a dispersive line can be replaced by a capacitance proportional to its length. Diffusion phenomena therefore appear to exceed the present VLSI horizon.

Journal Article•DOI•
TL;DR: The authors propose a simple model for the operation of MOSFETs in both weak and strong inversion, which shows better agreement to experimental results than previous models in the subthreshold and threshold regions.
Abstract: The authors propose a simple model for the operation of MOSFETs in both weak and strong inversion. The proposed model shows better agreement to experimental results than previous models in the subthreshold and threshold regions, and is well suited for use in circuit simulation programs; the authors have implemented it in MSINC and SPICE programs, and simulation results are compared to experimental data for a micropower amplifier.

Journal Article•DOI•
TL;DR: In this paper, the flip-flop resolving time parameters, required for calculation of synchronizer performance and reliability, are measured by wafer probing, without the need for dicing or bonding, by incorporation of test structures on an IC along with the flipflop to be measured.
Abstract: Integrated circuit flip-flop resolving time parameters, required for calculation of synchronizer performance and reliability, are measured by wafer probing, without the need for dicing or bonding, by incorporation of test structures on an IC along with the flip-flop to be measured. The circuit has five digital inputs, five digital outputs, including one for frequency measurements, and two analog inputs plus power and ground connections. Several delays that are fabricated as part of the test circuit, including a voltage controlled delay with a few picosecond resolution, are calibrated as part of the test procedure by grating them into and out of the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted, from the period of the ring oscillator with the delay included. A frequency divider is fabricated as part of the test structure to reduce the output of the ring oscillator to less than 200 kHz so no high-frequency inputs of outputs from the IC are required.

Journal Article•DOI•
TL;DR: A very low power biquadratic SC filter section designed for LF or FLF structures has been developed using improved CMOS invertors together with a three phase clocking sequence.
Abstract: The implementation of the double correlated sampling noise reduction technique in conventional strays-insensitive switched capacitor biquad building blocks is described. The function is performed by an offset cancellation circuit which is incorporated into the structure without the use of any additional capacitor, only minor modifications in the switching topology, and one supplementary clock phase. Consequently, a significant reduction of the low-frequency (1/f) noise is made possible and the usual differential amplifiers may be replaced by simple inverting amplifiers operated in class AB, featuring high-speed, low-quiescent power dissipation and low noise. An experimental micropower SC biquadratic filter section designed for `leapfrog' or `follow-the-leader feedback' structures has been developed using high gain (>80 dB) CMOS push/pull inverting amplifiers together with a three-phase clocking sequence. The integrated circuit, implemented in a low-voltage Si-gate CMOS process, achieves excellent accuracy and less than 5 /spl mu/W power dissipation with a 32 kHz sampling rate and /spl plusmn/1.5 V supplies; dynamic range is 66 dB.

Journal Article•DOI•
TL;DR: The authors have developed a novel table look-up MOSFET model which meets both requirements of a good accuracy and short computation time.
Abstract: A three-dimensional table look-up MOSFET modeling technique is described. The table, which is able to deal with future submicron devices, is constructed with a few thousand work memory capacity requirement by suppressing data redundancy. Sufficiently high accuracy, with less than point several percent error, is achieved by using a special interpolation, which is called curve shape fitting technique. Computational time to perform the interpolation from the table is much less than that for the analytical model.

Journal Article•DOI•
TL;DR: A circuit with a reduced number of components and optimized power has been used for the 20 MHz conversion speed, fully parallel, analog-to-digital converter device which has been designed for use at video speed.
Abstract: Describes a 20 MHz conversion speed, fully parallel, analog-to-digital converter device which has been designed for use at video speed. Laser trimming technology has been adopted to improve nonlinearity errors brought about by reference voltage distortion to less than 1 mV to realize a /SUP 1///SUB 2/ LSB accuracy for the 10-bit A/D converter. The large number of comparator stages required by a parallel converter leads to a high number of components and large power dissipation. Therefore, a circuit with a reduced number of components and optimized power has been used. The process employed is a 3 /spl mu/m bipolar process, which integrates about 40000 elements onto a 9.2/spl times/9.8 mm chip.