# Showing papers in "IEEE Journal of Solid-state Circuits in 1984"

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Philips

^{1}TL;DR: In this paper, a simple formula is derived for quick calculation of the maximum short-circuit dissipation of static CMOS circuits, based on the behavior of the inverter when loaded with different capacitances.

Abstract: A simple formula is derived for quick calculation of the maximum short-circuit dissipation of static CMOS circuits. A detailed discussion of this short-circuit dissipation is given based on the behavior of the inverter when loaded with different capacitances. It was found that if each inverter of a string is designed in such a way that the input and output rise and fall times are equal, the short-circuit dissipation will be much less than the dynamic dissipation (<20%). This result has been applied to a practical design of a CMOS driving circuit (buffer), which is commonly built up of a string of inverters. An expression has also been derived for a tapering factor between two successive inverters of such a string to minimize parasitic power dissipation. Finally, it is concluded that optimization in terms of power dissipation leads to a better overall performance (in terms of speed, power, and area) than is possible by minimization of the propagation delay.

756Â citations

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TL;DR: Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described.

Abstract: Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described. The code density test produces a histogram of the digital output codes of an ADC sampling a known input. The code density can be interpreted to compute the differential and integral nonlinearities, gain error, offset error, and internal noise. Conversion-rate and frequency-dependent behavior can also be measured.

527Â citations

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TL;DR: Fully integrated, high-frequency continuous-time filters can be realized in MOS technology using a frequency-locking approach to stabilize the time constants using a phase-locked loop.

Abstract: Fully integrated, high-frequency continuous-time filters can be realized in MOS technology using a frequency-locking approach to stabilize the time constants. A simple, fully differential integrator, optimized for phase-error cancellation, forms the basic element; a complete filter consists of intercoupled integrators. The center frequency of the filter is locked to an external reference frequency by a phase-locked loop. A prototype sixth-order bandpass filter with a center frequency of 500 kHz dissipates 55 mW and occupies 4 mm/SUP 2/ in a 6-/spl mu/m CMOS technology.

403Â citations

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TL;DR: A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described and 15-bit resolution and linearity at a 12-kHz sampling rate is demonstrated.

Abstract: A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 /spl mu/V in 3 /spl mu/s. An experimental converter fabricated using a 6-/spl mu/m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate.

360Â citations

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TL;DR: Results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.

Abstract: Explicit formulas are derived using statistical methods for the random errors affecting capacitance and current ratios in MOS integrated circuits. They give the dependence of each error source on the physical dimensions, the standard deviations of the fabrication parameters, the bias conditions, etc. Experimental results, obtained for both matched capacitors and matched current sources using a 3.5-/spl mu/m NMOS technology, confirmed the theoretical predictions. Random effects represent the ultimate limitation on the achievable accuracy of switched-capacitor filters, D/A converters, and other MOS analog integrated circuits. The results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.

339Â citations

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TL;DR: An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology.

Abstract: An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS integrator and exchange of capacitors. A first-order cancellation of the charge injection effect from MOS transistor switches is attained with a combination of differential circuit implementation and an optimum timing scheme. An experimental prototype has been fabricated with a standard 5-/spl mu/m n-well CMOS process. It achieves 12-bit resolution at a sampling rate of 8 kHz. The analog chip area measures 2400 mils/SUP 2/.

325Â citations

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TL;DR: In this paper, two circuits are presented that overcome the power-supply rejection ratio (PSRR) problems of the earlier amplifier: one for virtual ground applications such as switched-capacitor integrators, the other for buffer applications requiring wide common-mode input range.

Abstract: Internally compensated CMOS op amps have been widely used in sampled-analog signal processing applications over the past several years. However, the popular two-stage op amp suffers from poor AC power supply rejection to one of the power rails. Two circuits are presented that overcome the power-supply rejection ratio (PSRR) problems of the earlier amplifier: one for virtual ground applications such as switched-capacitor integrators, the other for buffer applications requiring wide common-mode input range. Small signal analysis is developed for the open-loop and PSRR responses of the two amplifiers. In addition, design guidelines are suggested and test results are presented.

210Â citations

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TL;DR: In this paper, a concise analytical expression for switch-induced error voltage on a switched capacitor is derived from the distributed MOSFET model, which can be interpreted in terms of a simple lumped equivalent circuit.

Abstract: A concise analytical expression for switch-induced error voltage on a switched capacitor is derived from the distributed MOSFET model. The result can be interpreted in terms of a simple lumped equivalent circuit. With this expression the dependence is investigated of the error voltage on process parameters and on switch turnoff rate, source resistance, and other circuit parameters. These results can be used to quickly predict the error voltage. The analytical expression is in close agreement with computer simulations and experiments.

200Â citations

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TL;DR: Using a 3.5-/spl mu/m gate length complementary metal-oxide-semiconductor/silicon-on-sapphire technology, a single-chip, radiation-hardened, direct digital frequency synthesizer has been developed.

Abstract: Using a 3.5-/spl mu/m gate length complementary metal-oxide-semiconductor/silicon-on-sapphire technology, a single-chip, radiation-hardened, direct digital frequency synthesizer has been developed. The circuit is a critical component of a fast-tuning wideband frequency synthesizer for spread spectrum satellite communications. During each clock period the chip generates a new digitized sample of a sine wave, whose frequency is variable in 2/SUP 20/ steps from DC to one-half the clock frequency. Operation at up to 7.5 MHz is possible in a worst-case environment, including ionizing radiation levels up to 3/spl times/10/SUP 5/ rads(Si). A computationally efficient algorithm was chosen, resulting in 12-bit output precision with only 1084 logic gates and 3840 bits of on-chip read-only memory. The accuracy of the algorithm is sufficient to maintain in-band spurious frequency components below -65 dBc. At 300 mW, the chip replaces an MSI implementation which uses 25 integrated circuits and consumes 3.5 W.

175Â citations

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TL;DR: An MOS ternary-logic family comprising a set of inverters, NOR gates, and NAND gates is proposed, and an implementation of the cyclic convolution is concluded, an application in which a significant advantage can be gained through the use of ternaries digital hardware.

Abstract: An MOS ternary-logic family comprising a set of inverters, NOR gates, and NAND gates is proposed. These gates are used to design basic ternary arithmetic and memory circuits. The circuits thus obtained are then used to synthesize complex ternary arithmetic circuits and shift registers. The ternary circuits developed are shown to have some significant advantages relative to other known ternary circuits; these include low power dissipation and reduced propagation delay and component count. For a given dynamic range, the complexity of the new ternary circuits is shown to be comparable to that of corresponding binary circuits. Nevertheless, the associated reduction in the wordlength in the case of the ternary circuits tends to alleviate to a large extent the pin limitation problem associated with VLSI implementation. The authors conclude with an implementation of the cyclic convolution, an application in which a significant advantage can be gained through the use of ternary digital hardware.

166Â citations

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TL;DR: A semicustom delay commutator circuit to support the implementation of high-speed fast Fourier transform processors based on the radix 4 pipeline FFT algorithm of J.H. McClellan and R.J. Purdy (1978) is described.

Abstract: The development is described of a semicustom delay commutator circuit to support the implementation of high-speed fast Fourier transform processors based on the radix 4 pipeline FFT algorithm of J.H. McClellan and R.J. Purdy (1978). The delay commutator is a 108000-transistor circuit comprising 12288 shift register stages and approximately 2000 gates of random logic realized with 2.5-micrometer design rule CMOS standard cell technology. It operates at a 10-MHz clock rate, which processes data at a 40-MHz rate. The delay commutator is suitable for implementing processors that compute transforms of 16, 64, 256, 1024, and 4096 (complex) points. It is implemented as a 4-bit-wide data slice to facilitate cocatenation to accommodate common data word sizes and to use a standard 48-pin dual-in-line package.

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TL;DR: In this article, a silicon photodetector structure utilizing the MOSFET subthreshold effect is discussed, which can be integrated on the same chip with CCDs, providing an analog voltage signal over a wide dynamic range.

Abstract: A silicon photodetector structure utilizing the MOSFET subthreshold effect is discussed. This photodetector, which can be integrated on the same chip with MOSFET circuits or CCDs, provides an analog voltage signal over a wide dynamic range. Photodetector and arrays showed, in the visible spectrum an incoming radiation-detection light-intensity dynamic range of greater than 10/SUP 7/. In addition, the photodetector device was used to realize CCD and self-scanned MOSFET linear arrays. The theory of the new photodetector device and its use in forming linear imaging arrays are discussed. Experimental results are presented.

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AT&T

^{1}TL;DR: Two front-end amplifiers for fiber optics applications at gigabit data rates were fabricated in fine-line NMOS, operating at less than their designed frequency because of discrepancies between expected and measured transconductances.

Abstract: Two front-end amplifiers for fiber optics applications at gigabit data rates were fabricated in fine-line NMOS. One was designed for operation at 1 Gb/s and a simpler circuit was designed for 1.7 Gb/s, with the function of amplifying a photocurrent into an output voltage. An automatic gain control (AGC) optionally follows the first amplifier. The bandwidth of the first amplifier was measured to be 920 MHz, with optical operation at 800 Mb/s at an optical sensitivity of -28 dB using a pin detector for light at 1.3 /spl mu/m wavelength. The bandwidth of the second amplifier 32 dB at a bandwidth of 870 MHz. Both circuits operated at less than their designed frequency because of discrepancies between expected and measured transconductances.

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TL;DR: A monolithic circuit has been developed which accepts 16 parallel voltage inputs having values which may be as small as 15 mV or as large as 15 V, and generates 16 concurrent output voltages with a peak amplitude controllable by the user.

Abstract: A monolithic circuit has been developed which accepts 16 parallel voltage inputs having values which may be as small as 15 mV or as large as 15 V, and generates 16 concurrent output voltages which are in the same ratios as the inputs with a peak amplitude controllable by the user. Response time is in the region of 1 /spl mu/s at full scale. The chip includes provisions for expansion to any number of channels. Operation is from supplies of /spl plusmn/3 to 15 V at a quiescent current of 125 /spl mu/A. Details of the design principles and peripheral circuitry are provided. Measurements of static accuracy and dynamic performance demonstrate that this approach may often simplify preprocessing of signal arrays in pattern-recognition applications.

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TL;DR: An algorithm is presented which facilitates an intelligent compromise between the delay time and the silicon area of a logic chain and can interactively assist the designer in the selection of logic pattern, the number of stages, and the sizes of the transistors.

Abstract: Delay-time optimization for integrated circuits is discussed. A design truly optimized for delay time is seldom practical because the silicon area increases very rapidly when the minimum delay time is approached. The author presents an algorithm which facilitates an intelligent compromise between the delay time and the silicon area of a logic chain. A computer software based on this algorithm can interactively assist the designer in the selection of logic pattern, the number of stages, and the sizes of the transistors. Some basic assumptions are made in this algorithm in order to keep the mathematics manageable. Consequently, some random parameters related to layout and interconnection are not addressed. The intended use of this algorithm is to guide the designer to arrive at an approximately optimized design during the logic definition stage and before the layout stage. Later, when the layout is completed, a circuit simulator should be used to fine-tune the design by incorporating these random layout parameters.

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TL;DR: Calculations and measurements show that in the T-cell integrator, capacitive area is conveniently traded off against amplifier specifications as open-loop and slew rate; power consumption is not necessarily compromised by these specifications.

Abstract: A switched-capacitor integrator circuit with very high time constant using capacitive T-cells, is presented. According to a set of design equations and constraints, a test circuit previously needing an excessive capacitive ratio of over 700 has been integrated with a capacitance spread of only 25. Contrary to other designs, a simple clocking scheme is sufficient. Calculations and measurements show that in the T-cell integrator, capacitive area is conveniently traded off against amplifier specifications as open-loop and slew rate; power consumption is not necessarily compromised by these specifications. Integration of an experimental test circuit has given evidence of the ease of implementing this technique in larger systems.

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TL;DR: It is shown that the properly compensated circuit can in principle produce thermal drift which is less than 10 p.p.m.//spl deg/C and significant improvements in performance can be achieved if the op-amp offset contribution to the output voltage is reduced or eliminated.

Abstract: The simple circuit uses naturally occurring vertical n-p-n bipolar transistors as reference diodes. Use is made of p-tub diffusions as temperature-dependent resistors to provide current bias, and an op-amp is used for voltage gain. Only two reference diodes, three p-tube resistors, and one op-amp are necessary to produce a reference with fixed voltage of -1.3 V. An additional op-amp with two p-tub resistors will adjust the output to any desired value. The criteria for temperature compensation are presented and it is shown that the properly compensated circuit can in principle produce thermal drift which is less than 10 p.p.m.//spl deg/C. Process sensitivity analysis shows that in practical applications it is possible to control the output to better than 2%, while keeping thermal drift below 40 p.p.m.//spl deg/C. Test circuits have been designed and fabricated. The output voltage produced was -1.3/spl plusmn/0.025 V with thermal drift less than 7 mV from 0/spl deg/C to 125/spl deg/C. Significant improvements in performance, at modest cost in circuit complexity, can be achieved if the op-amp offset contribution to the output voltage is reduced or eliminated.

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TL;DR: A frequency translation technique that effectively enhances the Q of the filter to >100 is presented, which is applicable to the design of a filter with an effective Q of much greater than 100.

Abstract: A circuit for extracting signaling information from its associated voice channel in frequency-division multiplexing has been integrated in metal gate CMOS technology. It uses a frequency translation technique that effectively enhances the Q of the filter to >100. It contains a programmable prefilter, a programmable modulator, and a highly selective bandpass filter. The frequency translation was accomplished through the use of a balanced modulator, which is well suited to a switched-capacitor realization. Design considerations that must be addressed in choosing an optimum architecture and a method of analyzing the ill effects of aliasing in a sampled data modulator were also presented. The technique described here is applicable to the design of a filter with an effective Q of much greater than 100.

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TL;DR: This paper shows that no configuration of linear circuit elements can provide zero voltage and zero current at both transitions of the switch, if nonzero output power is to be delivered to a load and the minimum jump magnitude is derived.

Abstract: The class-E switching-mode tuned power RF amplifier achieves high efficiency (ideally 100%) even if the switching times of the active device are appreciable fractions of the period of the output waveform, by shaping the switch voltage and current waveforms so that the voltage and current transitions are displaced in time from each other. As a second-order factor, nonideal waveform shaping results in power dissipation. That dissipation could be minimized if the nonideal voltage and current waveforms could be made to have zero values at the times the switch is turned on and off. This paper shows that no configuration of linear circuit elements can provide zero voltage and zero current at both transitions of the switch, if nonzero output power is to be delivered to a load. Therefore, a jump of current and/or voltage must be tolerated at the switch turn-off and/or turn-on; the minimum jump magnitude is derived. That jump imposes a lower bound on the power dissipation, determined by the degree of nonideality of the waveform shaping. Also derived is a new general equation for the output power of a single-ended switching-mode tuned power amplifier.

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IBM

^{1}TL;DR: In this paper, the bit line is precharged to half V/SUB DD/ for high-performance high-density CMOS DRAMs, which has several unique advantages, especially for high performance high density CMOSDRAMs.

Abstract: A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.

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TL;DR: Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.

Abstract: A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.

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TL;DR: An analysis of some of the mechanisms associated with this effect and the usefulness of some forms of common mode feedback are discussed and experimental results obtained from a CMOS integrated circuit realization are included.

Abstract: The principal motivation of using a fully differential configuration is to reduce power supply coupling. For this reason, an analysis of some of the mechanisms associated with this effect and the usefulness of some forms of common mode feedback are discussed. Experimental results obtained from a CMOS integrated circuit realization are also included. The circuit achieves 50 dB of power supply rejection ratio across the passband.

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TL;DR: The authors describe a complete method for predicting synchronization-error probabilities using circuit simulation and theoretical analysis that enhances the understanding of the synchronization process and the reliability of the predictions.

Abstract: Synchronization errors occur when asynchronous digital signals are received by clocked digital systems Digital synchronizers are designed to minimize the probability of such errors Empirical determination of error probabilities, as used in the past, is not a viable method for large-scale integrated circuit because it is cumbersome, interferes with the circuit performance, and does not account for tolerances of circuit parameters The authors describe a complete method for predicting synchronization-error probabilities using circuit simulation and theoretical analysis The analysis includes the efforts of random noise The simulation model readily takes into account tolerances of the circuit parameters The direct observability of all parameters of the model enhances the understanding of the synchronization process and the reliability of the predictions

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TL;DR: A parametric model is presented which covers the subthreshold and strong inversion regions with a continuous transition between these regions with the effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel-length modulation.

Abstract: The authors present a parametric model which covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel-length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.

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TL;DR: A fast, low-power 32K/spl times/8-bit CMOS static RAM with a high-resistive polyload 4-transistor cell has been developed utilizing a dynamic double word line (DDWL) scheme that reduces the core area delay time and operating power to about 1/2 of that of a conventional device.

Abstract: A fast, low-power 32K/spl times/8-bit CMOS static RAM with a high-resistive polyload 4-transistor cell has been developed utilizing a dynamic double word line (DDWL) scheme. This scheme combines an automatic power down circuitry and double word line structure. The DDWL, together with bit line and sense line equilibration, reduces the core area delay time and operating power to about 1/2 and 1/15 that of a conventional device, respectively. A newly developed fault-tolerant circuitry improves fabrication yield without degrading the access time. As for a fabrication process, an advanced 1.2-/spl mu/m p-well CMOS technology is developed to realize the ULSI RAM, integrating 1,600,000 elements on a 6.68/spl times/8.86 mm/SUP 2/ chip. The RAM offers, typically, 46 ns access time, 10 mW operating power and 30 /spl mu/W standby power.

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TL;DR: The authors emphasize the circuit innovations of some key analog functions realized on the chip, specifically, the operational amplifier family, the precision bandgap reference circuit, and the line balancing function.

Abstract: A CMOS analog VLSI chip for telecommunications applications has been designed in which many desirable line card features are programmable through a unique interface from the central switching office. The authors emphasize the circuit innovations of some key analog functions realized on the chip, specifically, the operational amplifier family, the precision bandgap reference circuit, and the line balancing function. The die size of the analog VLSI is approximately 50000 mils/SUP 2/, and the active power dissipation is 80 mW with a 1 mW standby mode.

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TL;DR: The Pierce oscillator as discussed by the authors uses only one package pin and no external components other than the crystal need be dedicated to the oscillator, and can be implemented in either NMOS or CMOS technologies using only a moderate amount of silicon area.

Abstract: The oscillator features the same stability, reliability, and ease of use as the common Pierce oscillator; however, only one package pin and no external components other than the crystal need be dedicated to the oscillator. The design is quite general, and may be implemented in either NMOS or CMOS technologies, using only a moderate amount of silicon area. Design examples are given, and the fabrication results are presented.

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TL;DR: A four-state ROM is described which reduces conventional two- state ROM matrix size by 50% by varying device thresholds using multiple ion implants.

Abstract: A four-state ROM is described which reduces conventional two-state ROM matrix size by 50%. The four states are encoded in the matrix by varying device thresholds using multiple ion implants. This is called multilevel technology. The detection of matrix device type is determined by the length of time required for a linearly ramped word line to rise from 0 V to the point where the matrix device is turned on. Peripheral circuitry has been devised to measure this time period and output the device type as a two-bit binary code. A 128K ROM which incorporates the new multilevel matrix cell has been fabricated in 6-/spl mu/m metal gate technology. Die size of the ROM is 208/spl times/213 mils/SUP 2/.

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TL;DR: A monolithic 8-bit two-step flash type A/D converter has been designed to obtain full resolution and good linearity at high frequencies and a double folding analog signal processing system is used.

Abstract: A monolithic 8-bit two-step flash type A/D converter has been designed. To obtain full resolution and good linearity at high frequencies, a double folding analog signal processing system is used. Delay time errors between the coarse and the fine quantizes used can be corrected for in this system. An on-chip input amplifier allows adjustment of the input sensitivity with a high input impedance and a low input capacitance. the 3 x 4.2 mm/sup 2/ chip made in a standard bipolar technology consumes 100 mA from a 5.2 V supply.

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TL;DR: The current efficiency of several amplifiers is studied using the IDAC amplifier synthesis program and experimental results of integrated amplifiers are compared with the performances predicted by IDAC and SPICE2.

Abstract: The current efficiency of several amplifiers is studied using the IDAC amplifier synthesis program. The possibilities and features of IDAC are briefly discussed and some important simulation results are presented. A current excess factor is defined to compare performance independently of gain-bandwidth product and capacitive load. Experimental results of integrated amplifiers are compared with the performances predicted by IDAC and SPICE2. Finally, it is shown how the current efficiency can be further improved.