Showing papers in "IEEE Journal of Solid-state Circuits in 1986"

Characterisation and modeling of mismatch in MOS transistors for precision analog design

Abstract: A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.

Continuous-time MOSFET-C filters in VLSI

Abstract: The desirable features of fully integrated, VLSI-compatible continuous-time filters are discussed. A recently proposed integrated continuous-time filter technique is reviewed, in which MOS transistors are used in place of resistors along with the nonlinearity cancellation and on-chip automatic tuning. The filters obtained using this technique are compared to switched-capacitor filters, digital filters, and continuous-time filters using different techniques. Representative experimental results are given, demonstrating the high performance that can be achieved.

An 80-MHz 8-bit CMOS D/A converter

Abstract: A high-speed 8-bit D/A converter has been fabricated in a 2-/spl mu/m CMOS technology. In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence called symmetrical switching have been used. The mismatch problem of small-size transistors has been relaxed by this matrix configuration. The linearity error caused by an undesirable current distribution of the current sources has been reduced by symmetrical switching. A high-speed decoding circuit and a fast-setting current source have been developed. The experimental results show that the maximum conversion rate is 80 MHz, a typical DC integral linearity error is 0.38 LSB, a typical DC differential linearity error is 0.22 LSB, and the maximum power consumption is 145 mW. The chip size is 1.85 mm/spl times/2.05 mm.

Accurate simulation of power dissipation in VLSI circuits

Abstract: It becomes increasingly more important to reduce the power dissipation as the number of devices in VLSI increases. Accurate simulation of power dissipation is desirable while circuits are analyzed with circuit simulators such as SPICE. An accurate method is presented for simulating the power dissipation with use of a dependent current source and a parallel RC circuit. The steady-state voltage across the capacitor reads the average power drawn from the supply voltage source. Simulation results are shown for CMOS circuits.

A CMOS Four-Quadrant Analog Multiplier

Abstract: A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.

Design procedures for differential cascode voltage switch circuits

Abstract: Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. Two procedures are presented for constructing DCVS trees to perform random logic functions. The first procedure uses a Karnaugh mapping technique and is a very powerful pictorial method for hand-processing designs involving up to six variables. The second procedure is a tabular method based on the Quine-McCluskey approach and is suitable for functions with more than six variables. Both of these procedures are considerably easier to implement than a recently proposed algebraic technique which relies upon decomposition and factorization of Boolean expressions. Several DCVS circuits that have been synthesized by the Karnaugh map (K-map) and tabular procedures are presented.

Corrections to an elliptic continuous-time CMOS filter with on-chip automatic tuning

Abstract: A voice-band continuous-time filter is described which was designed based on the technique of fully balanced networks and was fabrication in a 3.5-/spl mu/ CMOS technology. The filter implements a fifth-order elliptic low-pass transfer function with 0.05-dB passband ripple and 3.4 kHz cutoff frequency. A phase-locked loop control system fabricated on the same chip automatically references the frequency response of the filter to an external fixed clock frequency. The cutoff frequency was found to vary by less than 0.1% for an operating temperature range of 0-85/spl deg/C. The absolute value accuracy of the cutoff frequency was 0.5% (standard deviation). With /spl plusmn/5-V power supplies the measured dynamic range of the filter was approximately 100 dB.

CMOS RF circuits for data communications applications

Abstract: The author describes the recent development of two analog CMOS circuits operating at RF frequencies with applications to data communications. One is a four-quadrant analog multiplier which exhibits a 100-MHz bandwidth with a measured linearity error of 0.7% for X and Y inputs of 0.6 and 0.8 V, respectively. The other is a 90/spl deg/ phase shifter which maintains the grain and phase errors of less than 0.5 dB and 3/spl deg/, respectively, for a signal within 40-60-MHz frequency range.

A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS

Abstract: A design is presented for an 8-bit/spl times/8-bit parallel pipelined multiplier for high speed digital signal-processing applications. The multiplier is pipelined at the bit level. The first version of this multiplier has been fabricated in 2.5-/spl mu/m CMOS technology. It has been tested at multiplication rates up to 70 MHz with a power dissipation of less than 250 mW. Clock skew, a major problem encountered in high-speed pipelined architectures, is overcome by the use of a balanced clock distribution network all on metal, and by proper use of clock buffers. These issues and the timing simulation of the pipeline design are discussed in detail. Possible extensions and improvements for achieving higher performance levels are discussed. The conversion of the two-phase clocking scheme to an inherently single-phase clock approach is one possible improvement. A design using this approach has been simulated at 75 MHz and is currently being fabricated.

Reference refreshing cyclic analog-to-digital and digital-to-analog converters

Abstract: A method of cyclic analog-to-digital (A/D) and digital-to-analog (D/A) conversion using switched-capacitor techniques is described. By periodically modifying the reference voltage to compensate for the nonideal signal-transfer-loop gain, it is possible in principle to build A/D and D/A converters whose linearity is independent of component ratios and that occupy only a small die area. These converters require two moderate-gain MOS operational amplifiers, one comparator, and a few capacitors. A test chip for A/D conversion was built and evaluated. The test data show that the A/D performs as a monotonic 13-bit converter with maximum 1-LSB differential and 2-LSB integral nonlinearity.

Power distribution techniques for VLSI circuits

Abstract: The onchip power distribution problem for highly scaled technologies is investigated. Metal migration and line resistance problems as well as ways to optimize multilayer metal technology for low resistance, low current density, and maximum wirability are also investigated. Fundamental lower limits and the limiting factors of the power-line current density and the voltage drop are studied. Tradeoffs between interconnect wirability and power distribution space are examined. Power routing schemes, as well as the optical number of metal layers and the optimal thickness of each layer, are examined. The results indicate that orders of magnitude improvements in current density and resistive voltage drop can be achieved using very few layers of thick metal whose thicknesses increase rapidly in ascending layers. Also, using the upper layers for power distribution and lower layers for signal routing results in the most wire length available for signal routing.

Operation of bulk CMOS devices at very low temperatures

Abstract: Low-temperature (77K, 4.2K) operation is proposed for bulk CMOS devices to be used in superfast VLSI applications. Symmetrical variation of the parameters of both n-channel and p-channel MOSFETs with respect to the temperature and latch-up immunity makes CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, inverter chains and 16-kb static random-access memories (RAMs) with 2-/spl mu/m gate length were measured. Average propagation delay for an inverter chain has been reduced to 175 ps (77K) and 104 ps (4.2K) from 296 ps at 300K without sacrificing power dissipation. The power-delay product is less 1 fJ, which is the smallest for silicon devices reported to date. The chip select-access time of the RAM has been reduced to 14.3 ns (77K) from 24 ns (300K).

Elimination of process-dependent clock skew in CMOS VLSI

Abstract: Delays of two clock signals propagating along their respective CMOS logic circuit paths can be matched against all processing variations if the sum of the pull-up delays of PFETs along the first signal path is matched to that of the second path, and if the sum of the pull-down delays of NFETs along the first path is matched to that of the second path. This design technique allows generation of a skewless pair of upgoing and downgoing CMOS clocks, and the technique allows the design of CMOS VLSI free from process-induced race conditions. The technique is flexible for light or heavy clock load and for the choice of decoder logic. The technique has a wide application in MOS circuits other than clock decoders.

Realization of quaternary logic circuits by n-channel MOS devices

Abstract: A method to implement quaternary circuits using NMOS devices is proposed. The authors have designed a simplified elementary form of inverter and have implemented a series of fundamental logic and memory circuits. These circuits comprise MOS transistors with three values of enhancement-mode threshold voltage and one depletion-mode threshold voltage. The features of these circuits are a small number of MOS transistors, a simple structure, and an exact transfer characteristic. Several fundamental circuits such as inverter, NAND, NOR, and delta literal have been fabricated by conventional NMOS technology. Comparisons between the measured and calculated results indicate a good agreement, taking into account some back-bias effect. The performance of the inverter, including speed, noise margin, and pattern area, is also discussed.

A 12-bit sigma-delta analog-to-digital converter with a 15-MHz clock rate

Abstract: A sigma-delta analog-to-digital converter that achieves 12-bit integral and differential linearity and nearly 13-bit resolution without trimming is described. The baseband width is 120 kHz with a first filter pole at 60 kHz, the clock frequency is 15 MHz, and only one 5-V power supply is needed. The circuit was realized in a p-well CMOS technology with 3-/spl mu/m minimum feature size. Compared with previous sigma-delta modulators, the input signal frequency and clock rate limit have been increased by one order of magnitude. To achieve this increase, a novel integrator concept was developed using bidirectional current sources. The circuit is fully self-contained, requiring only a 15-MHz crystal and one blocking capacitor as external elements. This converter was developed as the analog front end of a digital echo cancellation circuit for an integrated services digital network.

Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI

Abstract: The authors describe the synchronous clock distribution problem in VLSI and techniques for its solution. In particular, the advantages and disadvantages of a hierarchical design technique for minimizing clock skew within a VLSI circuit are discussed. In addition, a model for clock distribution networks which considers the effects of distributed interconnect impedances on clock skew is described.

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

Abstract: The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.

A 4-Mbit DRAM with trench-transistor cell

Abstract: An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.

A Pipelined 330-MHz Multiplier

Abstract: An 8X8-bit multiplier test circuit developed in a 1-/spl mu/m NMOS technology is described. To achieve a high throughput rate, extensive pipelining is used in a semi-systolic fashion. It is shown that this saves area and allows for shorter cycle times compared to a pure systolic array. Problems with widely distributed lines (broadcasting) are avoided by a novel carry-save-adder cell. The data inputs and outputs are ECL compatible. The circuit contains 5480 MOSFET's in an active area of 0.6 mm/sup 2/. Effective channel lengths of 0.9 and 1.1 /spl mu/m are utilized for the enhancement and depletion transistors with a gate oxide thickness of 12.5 nm. The power dissipation is 1.5 W at a supply voltage of 3 V. The test chip operates up to a clock frequency of 330 MHz at room temperature and up to 600 MHz with liquid nitrogen cooling. This demonstrates the applicability of large-scale integrated MOS circuits in a frequency range of several hundred megahertz.

Design-performance trade-offs in CMOS-domino logic

Abstract: The authors present a study of the charge-sharing problem and its effect on the performance of CMOS-domino logic. Several solutions to the charge-sharing problem are examined, and the results are verified by simulation. Thus, the charge-sharing problem in CMOS-domino logic was identified and alternate approaches were evaluated.

Class E tuned power amplifier with nonsinusoidal output voltage

Abstract: An analysis is presented of the amplifier for a limiting case when the load network does not contain a series-resonant output circuit and the output voltage is non-sinusoidal. For optimum operation with any switch-duty ratio, the author has determined the current and voltage waveforms, the collector current and collector-emitter peak values, the output power, the power-output capability, and the load-network component values. The spectrum of the output voltage is given for a switch-duty ratio of 0.25, 0.5, and 0.75. Close-approximation equations are given for transistor power losses and collector efficiency. The experimental and theoretical results are in very good agreement. The measured collector efficiency is 95%. The circuit has practical applications, e.g., in high-efficiency switching-mode DC-to-DC converters used in DC power supplies for microcomputers or communication equipment.

Design and performance of a fully integrated bipolar 10.7-MHz analog bandpass filter

Abstract: Design and experimental evaluation of a sixth-order fully integrated continuous-time 10.7-MHz bandpass filter are presented. Circuit performance is stabilized through on-chip tuning by a dual-loop master-slave control scheme that locks center frequency and bandwidth to an external reference signal. Difficulties in design and performance are discussed and corrections suggested where appropriate.

A 1-Mbit DRAM with 33-MHz serial I/O ports

Abstract: High-speed operation, a 33-MHz serial cycle, and a 10-ns serial data access time have been realized by internal serial/parallel conversion circuits, a newly designed I/O controller circuit, new dynamic register circuits, a divided sensing method, and an optimized layout design. The chip is fabricated with a 1.2-/spl mu/m double-level polysilicon and double-level aluminium n-channel MOS process technology. An optimized interlevel insulator realizes equivalent first- and second-level aluminium pitches for a compact chip design. The chip size is 5.88/spl times/11.2 mm/SUP 2/. This memory has high-speed input and output capability as well as random accessibility. These features are suitable for TV and VCR frame-memory-system applications.

A wide-band low-noise monolithic transimpedance amplifier

Abstract: A transimpedance amplifier with nominal 200-MHz bandwidth, 6.6-k/spl Omega/ gain, and 33-nA RMS-equivalent input noise current is described. The circuit is realized in silicon-bipolar-monolithic technology and functions with source capacitances ranging from zero to several picofarads.

A substrate-plate trench-capacitor (SPT) memory cell for dynamic RAM's

Abstract: A (dynamic random-access memory) DRAM cell using a trench capacitor with a grounded substrate plate has been demonstrated, fabricated of functional fully decoded 64K arrays. The cell array is located inside the well and the trench capacitor extends from the planar surface through the well and epitaxial layer into the heavily doped substrate. The polysilicon inside the trench, connected to the source region of the transfer device, is used as the storage node and the bulk silicon surrounding the trench serves as the capacitor plate electrode. The cell features small area, high capacitance, small leakage current, low soft error rate, reduced surface topography, and a very stable capacitor-plate electrode. The arrays were fabricated in an advanced, 3.3-V, n-well epitaxial CMOS technology with a 15-nm gate insulator. The n- and p-channel transistors, exhibit transconductances of 120 and 650 mS/mm, respectively, at effective channel lengths of 6.0 /spl mu/m. Ring oscillators designed at this length have delays of 170 ps at 3.3 V.

Power Reduction Techniques in Megabit DRAM's

Abstract: Power dissipation in dynamic random-access memories (DRAM's) is described. Power reduction techniques are summarized and a comparison is made of NMOS and CMOS for individual circuits focusing on power dissipation for full- V/sub cc/ precharge and half- V/sub cc/ precharge, decoder, and clock generator. These results are then applied to actual 1-Mbit chips. The CMOS approach with a half-V/sub cc/ precharge is found to result in a power dissipation of just half that for NMOS, which is, verified through experiments on 1-Mbit CMOS and NMOS chips. Furthermore, from estimating power dissipation for DRAM chips larger than 1 Mbit, it is thought that the critical point for power-supply transition from the existing 5 V is around the 16-Mbit level.

An 8-bit 250 megasample per second analog-to-digital converter: operation without a sample and hold

Abstract: A monolithic, 8-bit, 250 megasample per second analog-to-digital converter (ADC) fabricated in an oxide-isolated bipolar process is described. The use of a flash ADC architecture at high speeds without a sample and hold leads to a number of error sources. The design of the converter is optimized to minimize the effects of these error sources. Experimental results are presented and compared with theory.

Intermodulation in high-frequency bipolar transistor integrated-circuit mixers

Abstract: Intermodulation in bipolar-transistor double-balanced mixers at high frequencies is analyzed theoretically and by computer simulation. The dependence of the distortion on a relatively few normalized parameters is illustrated. Computed results are compared with measurements on a monolithic quad mixer.

A CAD-oriented non-quasi-static approach for the transient analysis of MOS ICs

Abstract: The proposed approach, which considers the MOS transistor as a four-terminal device and takes into account short-channel effects, has been implemented in the circuit simulator SPICE. It is shown that the results predicted from this CAD-oriented approach are in good agreement with those achievable with a numerical procedure. It is also found that, using the new model in SPICE, the evaluation of transients in some high-precision circuits gives results significantly different from those expected from standard quasi-static formulations.

An 8-bit high-speed CMOS A/D converter

Abstract: An 8-bit high-speed A/D converter has been developed in a 1.5-/spl mu/m bulk CMOS double-polysilicon process technology. The design, process technology, and performance of the converter are described. In order to achieve high speed and low power, a fine-pattern process technology and a novel capacitor structure have been introduced and the transistor sizes of a chopper-type comparator have been optimized. High speed (30 MS/s) and low power consumption (60 mW) have been obtained. Computerized evaluations such as the histogram test and the fast Fourier transform test have been used to measure dynamic performance. The linearity error in dynamic operation is less than /spl plusmn/1 LSB. Signal-to-peak-noise ratio is 40 dB at a sampling rate of 14.32 MS/s and an input frequency of 1.42 MHz.