Showing papers in "IEEE Journal of Solid-state Circuits in 1987"
TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Abstract: The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.
1,456 citations
TL;DR: The Berkeley short-channel IGFET model (BSIM) as discussed by the authors is an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design is described.
Abstract: The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design are described. Both the strong-inversion and weak-inversion components of the drain current expression are included. In order to speed up the circuit-simulation execution time, the dependence of the drain current on the substrate bias has been modeled with a numerical approximation. This approximation also simplifies the transistor terminal-charge expressions. The charge model was derived from its drain-current counterpart to preserve consistency of device physics. Charge conservation is guaranteed in this model.
560 citations
TL;DR: A CMOS low-power low-noise monolithic instrumentation amplifier is described and it can produce variable gains of 14/20/26/40 dB, which are set by control software.
Abstract: A CMOS low-power low-noise monolithic instrumentation amplifier (IA) is described. The power drain is reduced by use of current feedback and by use of only single-stage operational transconductance amplifiers in the low-frequency loop. The bandwidth of the IA is designed for medical purposes (0.5-500 Hz) and it can produce variable gains of 14/20/26/40 dB, which are set by control software.
529 citations
TL;DR: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology.
Abstract: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.
432 citations
TL;DR: An extension of the op-amp concept featuring two differential inputs, in a closed-loop environment this circuit forces two floating voltages to the same value, and thus has many interesting applications in the analog circuit domain.
Abstract: An extension of the op-amp concept featuring two differential inputs is presented. In a closed-loop environment this circuit forces two floating voltages to the same value, and thus has many interesting applications in the analog circuit domain. A description of such a circuit, its nonidealities, and restrictions are given. A monolithic integration of this differential difference amplifier is implemented in a double-poly CMOS technology, its measured characteristics are described. Many applications of this circuit, including a voltage comparator with floating inputs, a voltage inverter without resistors, and an instrumentation amplifier with only two external gain determining resistors, are discussed.
409 citations
TL;DR: The examined class of circuits includes voltage multipliers, current multiplier circuits, linear V-I convertors, linear I-V convertor circuits, current squaring circuits, and current divider circuits.
Abstract: The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transistors is required in the presented circuits.
380 citations
TL;DR: The Interactive Design for Analog Circuits (IDAC) as discussed by the authors is a design system for transconductance amplifiers, operational amplifiers and low-noise BIMOS amplifiers.
Abstract: A design system has been developed which is able to design transconductance amplifiers, operational amplifiers, low-noise BIMOS amplifiers, voltage and current references, quartz oscillators, comparators, and oversampled A/D converters including their digital decimation filter starting from building-block and technology specifications. This design system, called Interactive Design for Analog Circuits (IDAC), is able to size a library of analog schematics (actually more than 40) as a function of technology (p-well and n-well CMOS) and desired building-block specifications. IDAC also generates a complete data sheet, an input file for SPICE2, and an input file for the analog layout program ILAC.
372 citations
TL;DR: It is shown that this easy-to-handle simplified model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.
Abstract: Charge injection in MOS analog switches, also called pass transistors or transmission gates, is approached by using the continuity equation. Experimental results show the negligible influence of substrate current which leads to a unidimensional model. An easy-to-handle simplified model is deduced and its predictions compared to the injection obtained by measurements. It is shown that this model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.
363 citations
TL;DR: A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described, which is versatile in application and diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.
Abstract: A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.
327 citations
TL;DR: In this article, a highly sensitive CMOS chopper amplifier for low-frequency applications is described, which is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique.
Abstract: A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W.
248 citations
TL;DR: The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted, which has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed.
Abstract: The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted. This class of circuits has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed. Several examples are demonstrated.
TL;DR: A two-rank GaAs sample-and-hold (S/H) chip and four 250-MHz silicon digitizers form a 1-GHz 6-b analog-to-digital converter (ADC) system that avoids dynamic errors inherent to interleaved ADCs.
Abstract: A two-rank GaAs sample-and-hold (S/H) chip and four 250-MHz silicon digitizers form a 1-GHz 6-b analog-to-digital converter (ADC) system. The two rank S/H architecture avoids dynamic errors inherent to interleaved ADCs; accuracy exceeds 5.2 effective bits, up to 1-GHz input frequency. Special attention is paid to avoiding GaAs slow transient errors.
TL;DR: Experimental results show that required timing relations can be obtained with less than 2-ns clock skew for frequencies from 1 to 18 MHz and an accurate phase relationship between the off-chip reference clock and the internal clock signals is obtained.
Abstract: The design of clock generation circuitry being used as a part of a high-performance microprocessor chip set is described. A self-calibrating tapped delay line is used to generate four nonoverlapping clock phases of a system clock. A charge-pump phase-locked loop (PLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between the off-chip reference clock and the internal clock signals. Experimental results show that required timing relations can be obtained with less than 2-ns clock skew for frequencies from 1 to 18 MHz.
TL;DR: On-chip test circuitry with a unity-gain operational amplifier, which reduces the disturbance imposed by measurement equipment to a minimum, is found to be an excellent monitor of the switch charge injection.
Abstract: The analysis has been extended to the general case including signal-source resistance and capacitance. Universal plots of percentage channel charge injected are presented. Normalized variables are used to facilitate usage of the plots. The effects of gate voltage falling rate, signal-source level, substrate doping, substrate bias, switch dimensions, as well as the source and holding capacitances are included in the plots. A small-geometry switch, slow switching rate, and small source resistance can reduce the charge injection effect. On-chip test circuitry with a unity-gain operational amplifier, which reduces the disturbance imposed by measurement equipment to a minimum, is found to be an excellent monitor of the switch charge injection. The theoretical results agree with the experimental data.
TL;DR: A flash-type analog-to-digital converter that operates without a sample-and-hold circuit and incorporates folding and interpolation techniques is presented, achieving an excellent performance while dissipating only 300 mW from a single 5-V power supply.
Abstract: A flash-type analog-to-digital converter that operates without a sample-and-hold circuit and incorporates folding and interpolation techniques is presented. It achieves an excellent performance while dissipating only 300 mW from a single 5-V power supply. The folding and interpolation system and the corresponding block diagram are explained. Implementation of folding and interpolation circuitry and the design of the reference resistor are discussed in detail. Several advantages of the system are investigated. The effective resolution of the converter is given as a function of analog input frequency. An 8-bit resolution bandwidth of 8 MHz is achieved. Up to an analog input frequency of 5 MHz, every distortion component stays below -60 dB. The maximum sample rate is 55 MHz. The circuit occupies 6 mm/SUP 2/ of silicon area, bonding pads included. It is realized in a 2.5-/spl mu/m bipolar process with an f/SUB T/ of 7.5 GHz.
TL;DR: A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques.
Abstract: Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.
TL;DR: A stereo D/A converter for digital audio applications is presented which obtains 16 bit resolution from a one bit converter, using a code conversion technique based upon oversampling and noise shaping.
Abstract: A complete monolithic stereo 16-bit D/A converter primarily intended for use in compact-disc players and digital audio tape recorders is described. The D/A converter achieves 16-bit resolution by using a code-conversion technique based upon oversampling and noise shaping. The band-limiting filters required for waveform smoothing and out-of-band noise reduction are included. Owing to the oversampling principle most applications will require only a few components for an analog postfilter. The converter has a linear characteristic and linear phase response. The chip is processed in a 2-/spl mu/m CMOS process and the die size is 44 mm/SUP 2/. Only a single 5-V supply is needed.
TL;DR: In this paper, a simple and robust instrumentation A/D converter, fabricated in a low-voltage 4/spl mu/m CMOS technology, is described, and the measured overall accuracy was 16 bits.
Abstract: A/D converters used in telemetry, instrumentation, and measurements require high accuracy, excellent linearity, and negligible DC offset, but need not be fast. A simple and robust instrumentation A/D converter, fabricated in a low-voltage 4-/spl mu/m CMOS technology, is described. The measured overall accuracy was 16 bits. Using a digital compensation for parasitic effects, both offset and nonlinearity were below 12 /spl mu/V. With analog compensation, the offset was 60 /spl mu/V and the nonlinearity below 15 /spl mu/V. These results indicate that even higher accuracy can be achieved using higher voltage technology.
TL;DR: A 16-bit/spl times/16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described, characterized by use of a binary tree of redundant binary adders.
Abstract: A 16-bit /spl times/ 16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described. This multiplier has been fabricated on an LSI chip using a standard n-E/D MOS process technology with a 2.7-/spl mu/m design rule. This multiplier is characterized by use of a binary tree of redundant binary adders. In the new algorithm, n-bit multiplication is performed in a time proportional to log/SUB 2/ n and the physical design of the multiplier is constructed of a regular cellular array. This new algorithm has been proposed by N. Takagi et al. (1982, 1983). The 16-bit/spl times/16-bit multiplier chip size is 5.8 /spl times/ 6.3 mm/SUP 2/ using the new layout for a binary adder tree. The chip contains about 10600 transistors, and the longest logic path includes 46 gates. The multiplication time was measured as 120 ns. It is estimated that a 32-bit /spl times/ 32-bit multiplication time is about 140 ns.
TL;DR: Experimental results are reported showing the performance of the circuit as a chemical sensor control system, providing the capability of performing differential measurements in order to null the effect of spurious background current.
Abstract: A simple CMOS integrated potentiostatic control circuit is described. The circuit maintains a constant bias potential between the reference and working electrodes. Chemical concentration signals are converted amperometrically to an output voltage with a slope of approximately 60 mV//spl mu/A. Redox currents from 0.1 to 3.5 /spl mu/A can be measured with a maximum nonlinearity of /spl plusmn/2% over this range. This design also provides the capability of performing differential measurements in order to null the effect of spurious background current. The total power consumption is less than 2 mW. Experimental results are reported showing the performance of the circuit as a chemical sensor control system.
TL;DR: A circuit configuration for a four-quadrant analog multiplier in MOS integrated circuit technology is described, based on the quarter-square algebraic identity and uses differential summer and differential squaring stages.
Abstract: A circuit configuration for a four-quadrant analog multiplier in MOS integrated circuit technology is described. It is based on the quarter-square algebraic identity and uses differential summer and differential squaring stages. The multiplier achieves a linearity of 0.44%, a -3-dB bandwidth of 5 MHz, a dynamic range of 87 dB, and a total harmonic distortion of 0.59%. The circuit was fabricated in a 5-/spl mu/m double-polysilicon p-well CMOS process. Typical power consumption is 10 mW. Chip size is 500 mil/SUP 2/.
TL;DR: In this article, a CMOS buffer amplifier which achieves significant improvements in linearity and drive capability over previously reported high-swing amplifiers is described, which is capable of rail-to-rail operation at both the input and output, exhibits a remarkably high linearity of 0.05% THD while driving 3 V/SUB p-p/ into 100 /spl Omega/ at 20 kHz.
Abstract: A CMOS buffer amplifier which achieves significant improvements in linearity and drive capability over previously reported high-swing amplifiers is described. The buffer operates from a 5-V supply, is capable of rail-to-rail operation at both the input and output, an exhibits a remarkably high linearity of 0.05% THD while driving 3 V/SUB p-p/ into 100 /spl Omega/ at 20 kHz.
TL;DR: In this article, a four-quadrant CMOS analog multiplier is presented, which is nominally biased with /spl plusmn/5-V supplies and exhibits less than 0.5% nonlinear error at 75% of full-scale swing.
Abstract: A four-quadrant CMOS analog multiplier is presented. The device is nominally biased with /spl plusmn/5-V supplies, has identical full-scale single-ended x and y inputs of /spl plusmn/4 V, and exhibits less than 0.5% nonlinear error at 75% of full-scale swing. Operation with supplies as low as /spl plusmn/2.5 V is also possible. A comparison of theoretical and experimental results obtained from fabrication of the multiplier in a 3-/spl mu/m p-well CMOS process is made.
TL;DR: A general-purpose gain/loss circuit is described, which provides up to 256 0.1-dB steps in gain or loss and has three digital interfaces: serial, parallel clocked input, and parallel fixed input.
Abstract: A general-purpose gain/loss circuit is described. Its function is controlled by an 8-b digital word. It provides up to 256 0.1-dB steps in gain or loss. The circuit has two modes of incremental gain/loss steps (two sets of gain/loss values for bits in the control word). A ninth bit selects between gain and loss. The IC has three digital interfaces: serial, parallel clocked input, and parallel fixed input. The chip is fabricated in a 3-/spl mu/m CMOS n-well process. It requires a /spl plusmn/5-V power supply, and for maximum gain of 25.5 dB, the 0.1-dB large-signal bandwidth is 260 kHz.
TL;DR: The authors provide an overview of MIPS-X, focusing on the techniques used to reduce the complexity of the processor and implement the on-chip instruction cache.
Abstract: MIPS-X is a 32-b RISC microprocessor implemented in a conservative 2-/spl mu/m, two-level-metal, n-well CMOS technology. High performance is achieved by using a nonoverlapping two-phase 20-MHz clock and executing one instruction every cycle. To reduce its memory bandwidth requirements, MIPS-X includes a 2-kbyte on-chip instruction cache. The authors provide an overview of MIPS-X, focusing on the techniques used to reduce the complexity of the processor and implement the on-chip instruction cache.
TL;DR: A 13-b self-calibrating algorithmic A/D converter with sample and hold and eight-channel multiplexer has been implemented in a standard 3-/spl mu/m CMOS technology to implement a complete data-acquisition peripheral.
Abstract: A 13-b self-calibrating algorithmic A/D converter with sample and hold and eight-channel multiplexer has been implemented in a standard 3-/spl mu/m CMOS technology. Digital circuitry including a sequencer, instruction RAM, and microprocessor interface have been incorporated to implement a complete data-acquisition peripheral. The conversion algorithm, calibration technique, and gain trimming circuitry are described. A bandgap voltage reference with buffered output and additional output voltage proportional to absolute temperature has also been implemented. Experimental data show that the integral and differential linearity meets 1/2 LSB (least significant bit) at the 13-b level; the dynamic performance is such that harmonic distortion of better than 84 dB below the fundamental is achieved.
AT&T1
TL;DR: The design and test results of a single-chip NMOS automatic gain control (AGC) amplifier, capable of operating at 3 GHz with unity gain delivering -8 dBm into a 50-/spl Omega/ load, is described.
Abstract: The design and test results of a single-chip NMOS automatic gain control (AGC) amplifier are described. The amplifier has a maximum flat gain of 50 dB, dynamic range of 70 dB, and a noise figure of 11 dB. The flat response from near DC to a 3-dB bandwidth of 1 GHz does not require tuning of any peaking circuits. The chip is also capable of operating at 3 GHz with unity gain delivering -8 dBm into a 50-/spl Omega/ load. The global feedback scheme designed for this chip stabilizes it against large shifts in threshold voltage and ambient temperature variation of 170/spl deg/C. This feedback scheme can provide stable DC feedback for a forward amplifier gain of at least 60 dB. Application of this application in the design of low-noise high-speed fibre-optic systems is envisaged.
TL;DR: In this paper, a monolithic realization of a switched-capacitor amplifier is reported, which has op-amp offset voltage cancellation without requiring the output to slew to ground each time the amplifier is reset.
Abstract: A monolithic realization of a switched-capacitor amplifier is reported. It has op-amp offset voltage cancellation without requiring the output to slew to ground each time the amplifier is reset. The amplifier is very insensitive to low op-amp gain. It also has clock-feedthrough cancellation. Finally, it can be used as a differential amplifier with both inputs being sampled at the same instance.
TL;DR: In this paper, an electrically erasable programmable read-only memory (EEPROM) is used in a novel way as a four-state memory by charging the floating gate to determined values.
Abstract: An electrically erasable programmable read-only memory (EEPROM) is used in a novel way as a four-state memory by charging the floating gate to determined values. The memory cell and the complete programming and readout circuit are described. Retention characteristics are investigated and found to confirm a thermionic emission model. Retention time is estimated to be more than 22 years at 125/spl deg/C. Secondary effects like charge trapping in the oxide are successfully suppressed by a controlled writing procedure. Using such a four-state EEPROM instead of a binary cell, a reduction in chip area of 40% can be expected for a 1-kb memory.
TL;DR: In this article, a high-performance analog cell library implemented in 3/spl mu/m CMOS is described, including an improved central biasing scheme, a circuit for high-swing cascode biasing, an impact ionization shielding technique, and a family of operational transconductance amplifiers including a precision low offsetvoltage amplifier utilizing lateral bipolar transistors.
Abstract: Several design aspects of a high-performance analog cell library implemented in 3-/spl mu/m CMOS are described, including an improved central biasing scheme, a circuit for high-swing cascode biasing, an impact ionization shielding technique, and a family of operational transconductance amplifiers including a precision low offset-voltage amplifier utilizing lateral bipolar transistors.