Showing papers in "IEEE Journal of Solid-state Circuits in 1990"
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Abstract: An alpha -power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square-law MOS model in the saturation region. Since the model is simple, it can be used to handle MOSFET circuits analytically and can predict the circuit behavior in the submicrometer region. Using the model, closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived. The delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is found that the CMOS inverter delay becomes less sensitive to the input waveform slope and that short-circuit dissipation increases as the carrier velocity saturation effect in short-channel MOSFETs gets more severe. >
1,596 citations
TL;DR: In this article, a technique that combines the high-frequency behavior of a single-stage op amp with the high DC gain of a multistage design is presented, which is based on the concept that a very high-DC gain can be achieved in combination with any unity-gain frequency achievable by a (folded-) cascode design.
Abstract: A technique that combines the high-frequency behavior of a single-stage op amp with the high DC gain of a multistage design is presented. This technique is based on the concept that a very high DC gain can be achieved in combination with any unity-gain frequency achievable by a (folded-) cascode design. Bode-plot measurements for an op amp realized in a 1.6- mu m process show a DC gain of 90 dB and a unity-gain frequency of 116 MHz (16-pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding to a closed-loop bandwidth of 18 MHz (35-pF load) and a settling accuracy better than 0.03%. This technique does not cause any loss in output voltage swing. At a supply voltage of 5.0 V an output swing of about 4.2 V is achieved without loss in DC gain. The above advantages are achieved with a 30% increase in chip area and a 15% increase in power consumption. >
711 citations
TL;DR: In this paper, a simple cascode with the gate voltage of the cascode transistor being controlled by a feedback amplifier called a regulated cascode is presented, where the minimum output voltage is lower by 30 to 60% while the output conductance and the feedback capacitance are lower by about 100 times.
Abstract: A simple cascode with the gate voltage of the cascode transistor being controlled by a feedback amplifier called a regulated cascode is presented. In comparison to the standard cascode circuit, the minimum output voltage is lower by about 30 to 60% while the output conductance and the feedback capacitance are lower by about 100 times. An analytical large-signal, small-signal, and noise analysis is carried out. Some applications like current mirrors and voltage amplifiers are discussed. Experimental results confirming the theory are presented. >
553 citations
TL;DR: In this article, a complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path, which consists of complementary inputs/outputs, an nMOS pass transistor logic network, and CMOS output inverters, and is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality.
Abstract: A 38-ns, 257-mW, 16*16-b CMOS multiplier with a supply voltage of 4 V is described A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 26 ns with 60 mW at 77 K >
485 citations
TL;DR: In this paper, passive inductors and LC filters fabricated in standard Si IC technology are demonstrated, and Q-factors from three to eight and inductors up to 10 nH in the gigahertz range have been realized.
Abstract: Passive inductors and LC filters fabricated in standard Si IC technology are demonstrated. Q-factors from three to eight and inductors up to 10 nH in the gigahertz range have been realized. Measurements on a five-pole maximally flat low-pass filter give midband insertion loss and -3 dB bandwidth close to the nominal design values of 2.25 dB and 880 MHz. >
433 citations
TL;DR: The jitter of such practical sampling systems as analog-to-digital converters, sample-and-hold circuits, and samplers is discussed and a model for estimating jitter is proposed, based on sampling sine-wave signal- to-noise ratio calculations.
Abstract: The jitter of such practical sampling systems as analog-to-digital converters, sample-and-hold circuits, and samplers is discussed. A model for estimating jitter is proposed. In this model, total jitter is composed of sampling circuit jitter, analog input signal jitter, and sampling clock jitter. Using this model, jitter is broken up into three components. To evaluate the model, a precise method for measuring jitter is devised. This method, based on sampling sine-wave signal-to-noise ratio calculations, enables separation of jitter and amplitude noise. The performance limit of converters as evaluated by the model is discussed. >
339 citations
TL;DR: It was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block.
Abstract: The relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block is examined. The investigation is done experimentally by implementing a set of industrial circuits as FPGAs using CAD (computer-aided design) tools for technology mapping, placement, and routing. A range of programming technologies (the method of FPGA customization) is explored using a simple model of the interconnection and logic block area. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block's functionality) is between three and four, and that a D flip-flop should be included in the logic block. The results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block. >
301 citations
TL;DR: A general-purpose fuzzy logic inference engine for real-time control applications, designed and fabricated in a 1.1- mu m, 3.3-V, double-level-metal CMOS technology, is discussed.
Abstract: A general-purpose fuzzy logic inference engine for real-time control applications, designed and fabricated in a 1.1- mu m, 3.3-V, double-level-metal CMOS technology, is discussed. Up to 102 rules are processed in parallel with a single 688 K transistor device. Features include a dynamically reconfigurable and cascadable architecture, TTL-compatible host interface, laser-programmable redundancy, a special mode for testability, RAM rule storage, and on-chip fuzzification and defuzzification. >
294 citations
TL;DR: In this paper, a 5-V, 7-order elliptic analog magnitude filter for antialiasing in digital video applications is described, based on a G/sub m/-C technique, exhibits a dynamic range of 61 dB and dissipates a power of 75 mW.
Abstract: An approach that has made possible the integration of video frequency continuous-time filters with wide dynamic range is discussed. The tuning scheme necessary to maintain the stable and accurate frequency response in the presence of temperature variations, process tolerance, and aging is described. Detailed design techniques specific to high-frequency operation are introduced to implement a 5-V, seventh-order elliptic analog magnitude filter for antialiasing in digital video applications. The filter, based on a G/sub m/-C technique, exhibits a dynamic range of 61 dB and dissipates a power of 75 mW. Ninety-two chips from various wafers and two different process runs were tested. Seventy-five percent of the fabricated chips were functional, and 63% of them met the commercial-grade specifications in spite of an error in the layout which forced the phase control circuitry to perform suboptimally. >
208 citations
TL;DR: In this paper, a linear large-signal MOS transconductor with the gain adjustable linearly by a voltage is described, and a perfect linear transfer characteristic is obtained by two cross-coupled differential transistor pairs operating in saturation pairwise at unequal bias, offering offset-free operation, with both differential or singleended input and differential output.
Abstract: A linear large-signal MOS transconductor with the gain adjustable linearly by a voltage is described. A perfect linear transfer characteristic is obtained by two cross-coupled differential transistor pairs operating in saturation pairwise at unequal bias, offering offset-free operation, with both differential or single-ended input and differential output. Single-ended output is achievable by use of a current mirror. The nonlinearity caused by mobility reduction, channel-length modulation, mismatch, etc. is discussed. A test circuit with transconductance of 6.25 mu mho has been built with 3- mu m MOS components, and a linearity error of less than +or-1% was measured for an input voltage range from -4 to 4 V. >
185 citations
TL;DR: In this paper, an MOS four-quadrant analog multiplier is described based on the square-law dependence of the MOS-transistor drain current on the gate-to-source voltage in the saturation region.
Abstract: An MOS four-quadrant analog multiplier is described. It is based on the square-law dependence of the MOS-transistor drain current on the gate-to-source voltage in the saturation region. One input is applied to the gate directly while the other input is applied to the source through a source-follower buffer stage. The circuit is realized with only 12 MOS transistors and two resistors. The circuit has been fabricated using a metal-gate NMOS process which has separate p-wells to eliminate the substrate bias effect. The multiplier achieves less than 0.45% nonlinearity when the input voltage range is 40% of the supply voltages, and it achieves a -3-dB bandwidth of 30 MHz. The total harmonic distortion is less than 0.6%. The power consumption and chip size are 8 mW and 1.2 mm/sup 2/, respectively. The second-order effects for this type of multiplier are considered in detail. >
IBM1
TL;DR: A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described.
Abstract: A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described. It can be packaged as a 2-Mb*8, 4-Mb*4, 8-Mb*2, or 16-Mb*1 DRAM, And is capable of operating in fast page mode, static column mode, or toggle mode. Speed and flexibility are achieved by a pipeline layout and on-chip SRAMs that buffer entire ECC words. The use of redundant word and bit lines in conjunction with the ECC produces a synergistic fault-tolerance effect. >
TL;DR: A current-mode technique for the design of algorithmic analog-to-digital converters (ADCs) allows the necessary voltage swing for a given dynamic range to be reduced while at the same time eliminating the need for large capacitors on which to store the signal.
Abstract: A current-mode technique for the design of algorithmic analog-to-digital converters (ADCs) is presented. The current-mode technique allows the necessary voltage swing for a given dynamic range to be reduced while at the same time eliminating the need for large capacitors on which to store the signal. Consequently, the resulting ADCs can be made very small and yet still capable of providing high sampling rates. The advantages and disadvantages of different current mirror structures for use in ADCs are discussed. Experimental results for ADCs fabricated using a 3- mu m CMOS process are reported, including an 8-b ADC which displayed a sampling rate of 500 kHz and a total circuit area of under 0.75 mm/sup 2/. >
TL;DR: In this article, a high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described.
Abstract: A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 95% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 p.p.m./ degrees C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequency. The total power dissipation is about 600 mW, and the active area is 30000 mil/sup 2/ in a 2- mu m single-poly double-metal n-well CMOS process. >
IBM1
TL;DR: Improved design techniques for logarithmic addition and higher order counters for multiplication complete this second-generation RISC floating-point unit design, and it allows for reduced overall system latency.
Abstract: A 440000-transistor second-generation RISC (reduced instruction set computer) floating-point chip is described. The pipeline latency is only two cycles, and a double-precision result is produced every cycle. System throughput and accuracy are increased by using a floating-point multiply-add-fused unit, which carries out a double-precision accumulate as a two-cycle pipelined execution with only one rounding error. While the cycle time (40 ns) is competitive with other CMOS RISC systems, the floating-point performance stretches to the range of bipolar RISC systems (7.4-13 MFLOPS LINPACK). Leading zero anticipation makes the two-cycle pipeline possible by nearly eliminating the additional postnormalization time, and it allows for reduced overall system latency. Partial decode shifters allow complete time sharing for the multiply and data alignment. Improved design techniques for logarithmic addition and higher order counters for multiplication complete this second-generation RISC floating-point unit design. >
TL;DR: In this paper, the effects of nonzero FET output conductance, limited frequency response and noise on the filter characteristics, and dynamic range are analyzed, particularly for filters with high Q components.
Abstract: A study of the limitations of active CMOS filters at high frequencies suggests automatic means to compensate imperfections in the filter response introduced by active devices. The effects of nonzero FET output conductance, limited frequency response and noise on the filter characteristics, and dynamic range are analyzed, particularly for filters with high Q components. These are used to demonstrate a 3- mu m CMOS realization of a fourth-order bandpass filter with a 250-kHz passband centered at 12.5 MHz. The filter demonstrates that the maximum frequency of filter operation is not as seriously limited by device f/sub T/ as was previously thought, but that automatic means may be used to tune out the imperfections introduced in the filter elements by the limited voltage gain and frequency response of transistors. >
TL;DR: An 8-b, 200-megasample/s flash converter with 400-MHz analog bandwidth and error correction circuitry is described, and measured frequency and error rate performance are examined.
Abstract: An 8-b, 200-megasample/s flash converter with 400-MHz analog bandwidth and error correction circuitry is described. A cascoded input stage and a dense bipolar process make the wide bandwidth possible. Errors arising from high input slew rate and comparator metastability are reduced by means of the circuitry and the latching stages respectively. The final defense against errors is the second rank error suppression. Measured frequency and error rate performance are examined. >
TL;DR: A VLSI-compatible approach for vector-matrix multipliers consisting of a two-dimensional array of analog multiplier circuits with the weight matrix values capacitively stored as analog voltages is described.
Abstract: A VLSI-compatible approach for vector-matrix multipliers consisting of a two-dimensional array of analog multiplier circuits with the weight matrix values capacitively stored as analog voltages is described. The performances of several MOSFET analog multiplier circuits, including the triode, differential pair, Gilbert, and modified Gilbert multiplier circuits, are evaluated. The weight retention characteristics of the capacitive storage approach are evaluated as a function of temperature with effective weight decay rates of 30 and 0.6 mV/s at room temperature measured for the single- and double-capacitor storage arrangements, respectively. The design approach for a 32*32 programmable vector-matrix multiplier circuit with an analog serial-to-parallel multiplexer for the input vector and an analog parallel-to-serial multiplexer for the output vector is described. An architecture for cascading the 32*32 vector-matrix multiplier circuits to implement multilevel artificial neural networks is described. >
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TL;DR: In this article, the value of the optimal taper depends on the C/sub x/C/sub y/ ratio: the best taper exceeds Jaeger's 2.72 slope, but only moderately.
Abstract: Jaeger's buffer comprises a string of tapered inverters. Each inverter is molded by a capacitor and a conductor. In this work, the capacitor is split into inherent and load components (C/sub x/ and C/sub y/), and it is shown that the value of the optimal taper depends on the C/sub x//C/sub y/ ratio: the best taper exceeds Jaeger's 2.72 slope, but only moderately. >
TL;DR: In this article, the authors used the AC small-signal analysis in the frequency domain instead of the usual time-domain approach to obtain the optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops.
Abstract: Optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops are obtained by using the AC small-signal analysis in the frequency domain instead of the usual time-domain approach. The Miller effect on the metastability is investigated for the configurations which have a better metastable resolving capability. The mean time between failure (MTBF) was measured, and the result verifies this new design approach. The power supply disturbance and temperature variation effects on the metastability were also measured, and the data show that a 0.75-V change of power supply voltage and 75 degrees C change of chip temperature cause a four orders of magnitude difference in the MTBF. The simulation results using the AC small-signal frequency-domain analysis agree well with the measurement data for the different power supply voltages and chip temperatures, confirming that an AC small-signal approach can be used more widely for the design of metastable hardened latch/flip-flops. The other parameters are discussed in terms of their effects on the latch/flip-flop's susceptibility to the metastable state. >
TL;DR: In this article, a three-stage CMOS power amplifier with a class AB rail-to-rail output stage is presented for ISDN applications with a gain bandwidth (GBW) of 5 MHz and with -80dB THD at 10 kHz for an output current of 20 mA in a load of 81 Omega.
Abstract: A CMOS power amplifier with a class AB rail-to-rail output stage is presented. By using a three-stage amplifier with double Miller compensation, the harmonic distortion of the output stage is suppressed by the internal feedback loops. This approach is thoroughly investigated, and it is shown that a three-stage amplifier has apparent advantages for DC gain, harmonic distortion, and power-supply rejection ratio (PSRR). A realized prototype for ISDN applications with a gain bandwidth (GBW) of 5 MHz and with -80-dB THD at 10 kHz for an output current of 20 mA in a load of 81 Omega is presented. >
TL;DR: A neural network implementation that uses MOSFET analog multipliers to construct weighted sums is described, which permits asynchronous analog operation of Hopfield-style networks with fully programmable digital weights.
Abstract: A neural network implementation that uses MOSFET analog multipliers to construct weighted sums is described. The scheme permits asynchronous analog operation of Hopfield-style networks with fully programmable digital weights. This approach avoids the use of components that waste chip area of require special processing. Two small chips have been fabricated and tested-one implementing a fully connected (recursive) network and the other containing isolated portions of a neuron. The fully connected network chip successfully solves simple graph partitioning problems, in confirmation of network simulations performed using an analytic model of the analog neuron. This result verifies the operation of the complete network, including common-mode biasing circuits and connection weight data paths. A direct scaling of this chip would allow the complete integration of 81-neuron fully connected networks with 6-b plus sign connection weights using 1.25- mu m design rules on a 1-cm die. >
TL;DR: In this paper, the design and implementation of switched-current (SI) ladder filters is described. But the SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) Integrator/Summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters.
Abstract: The design and implementation of switched-current (SI) ladder filters is described. The basic current-mode circuits, including the SI differential integrator/summer are developed. The SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) integrator/summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters. Signal flowgraph synthesis of SI ladder filters is presented. The nonideal characteristics of SI ladder filters that limit their accuracy are evaluated. Clock-feedthrough and device mismatch induced errors are more severe in the present SI circuit configurations than in SC circuits. A standard digital 2- mu m n-well CMOS process has been used to implement two high-order ladder filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to those obtained with the switched-capacitor technique. >
TL;DR: In this article, a method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described, and a CMOS operational-amplifier compiler (OAC) has been developed.
Abstract: A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density. >
TL;DR: In this paper, a high-speed 32*32b parallel multiplier with an improved parallel structure using 0.8-mu m CMOS triple-level-metal technology is discussed.
Abstract: A high-speed 32*32-b parallel multiplier with an improved parallel structure using 0.8- mu m CMOS triple-level-metal technology is discussed. A unit adder, a 4-2 compressor, enhances the parallelism of the multiplier array. A 25% reduction in the propagation delay time is achieved by using the compressor. The multiplier contains 27704 transistors with a 2.68-*2.71-mm/sup 2/ die area. The multiplication time is 15 ns at 5 V with a power dissipation of 277 mW at 10-MHz operation. The triple-level-metal interconnection technology reduces the multiplier layout area. Compared with double-level-metal technology, a 27% chip size reduction is achieved. >
TL;DR: Error correction techniques that overcome several error mechanism that can affect the accuracy of charge-redistribution analog-to-digital converters (ADCs) are described and a fully differential charge- redistribution ADC implemented with these techniques is described.
Abstract: Error correction techniques that overcome several error mechanism that can affect the accuracy of charge-redistribution analog-to-digital converters (ADCs) are described. A correction circuit and a self-calibration algorithm are used to improve the common-mode rejection of the differential ADC. A modified technique is used to self-calibrate the capacitor ratio errors and obtain higher linearity. The residual error of the ADC due to capacitor voltage dependence is minimized using a quadratic voltage coefficient (QVC) self-calibration scheme. A dual-comparator topology with digital error correction circuitry is used to avoid errors due to comparator threshold hysteresis. A fully differential charge-redistribution ADC implemented with these techniques was fabricated in a 5-V 1- mu m CMOS process using metal-to-polysilicide capacitors. The successive-approximation converter achieves 16-b accuracy with more than 90 dB of common-mode rejection while converting at a 200-kHz rate. >
TL;DR: In this article, a linearity study of the propagation delay of bipolar circuits carried out using a SPICE program is discussed, and therefore analytical propagation delay expressions for ECL and CML circuits are derived using a sensitivity analysis.
Abstract: A linearity study of the propagation delay of bipolar circuits carried out using a SPICE program is discussed. It is found that the behavior of the propagation delay is quite linear, and therefore analytical propagation delay expressions for ECL and CML circuits are derived using a sensitivity analysis. The validity of the expressions is checked by SPICE simulations and comparison to experimental data published in the literature, and agreement is within 5%. The expressions indicate that there is an optimum value of load resistance for logic circuits in order to achieve a minimum propagation delay. For present technology, logic circuits for silicon transistors can operate at the current density corresponding to maximum f/sub T/, and logic circuits for AlGaAs-GaAs heterojunction bipolar transistors (HBTs) should operate at a current density lower than that of maximum f/sub T/. Therefore, it is important to increase the collector current density of maximum f/sub T/ for silicon bipolar circuits, or to decrease the base resistance R/sub B/ and the forward transit time tau /sub F/ for HBT circuits, in order to increase the circuit speed. >
TL;DR: A single-phase clocking scheme is described that provides a structure that can contain all components of a digital VLSI system, including static, dynamic, and precharged logic as well as memories and PLAs.
Abstract: Two of the main consequences of advances in VLSI technologies are increased cost of design and wiring. In CMOS synchronous systems, this cost is partly due to tedious synchronization of different clock phases and routing of these clock signals. Here, a single-phase clocking scheme that makes the design very compact and simple is described. It is shown that this scheme is general, simple, and safe. It provides a structure that can contain all components of a digital VLSI system, including static, dynamic, and precharged logic as well as memories and PLAs. Clock and data signals are presented in a clean way that makes VLSI circuits and systems well suited for design compilation. >
TL;DR: A general-purpose median filter unit configuration in the form of two single-chip median filters, one extensible and one real time, is described, along with some possible applications.
Abstract: A general-purpose median filter unit configuration in the form of two single-chip median filters, one extensible and one real time, is described. The networks of the chips are pipelined and systolic at bit level and based on odd/even transposition sorting. The chips are implemented in 3- mu m standard CMOS using full-custom VLSI design techniques. The exact median of elements, in a window size w=9 with arbitrary word length L, can be found using only one extensible median filter chip. The filter can be extended to arbitrary window size and word lengths by using many chips. Simulation results show that the extensible median filter chip can be clocked up to 40 MHz and can generate 30/L megamedians per second. The real-time median filter chip can find the exact running medians of elements in a window of a fixed size w=9 with L=8. Simulations show that it can generate up to 50 megamedians per second with a 50-MHz clock. The algorithms, VLSI implementations, and chip test results are presented, along with some possible applications. >
TL;DR: A rail-to-rail amplifier that maintains a high common-mode rejection ratio (CMRR) over the whole common- mode range and has a low harmonic distortion despite the use of relatively small output devices is discussed.
Abstract: A rail-to-rail amplifier that maintains a high common-mode rejection ratio (CMRR) over the whole common-mode range and has a low harmonic distortion despite the use of relatively small output devices is discussed. The circuit, which measures only 0.3 mm/sup 2/ in a 3- mu m technology, has a quiescent current consumption of 600 mu A and a CMRR larger than 55 dB. It handles up to 4 nF, and can, with a 5-V supply, drive 3.8 V/sub pp/ into 100 Omega (0.1% total harmonic distortion at 10 kHz). >