Showing papers in "IEEE Journal of Solid-state Circuits in 1994"
TL;DR: In this article, power consumption of logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI has been estimated and an estimate tool is created.
Abstract: Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom design. Also comparisons between static and dynamic logic are given. Results show that the power consumption of all interconnections and off chip driving can be up to 20% and 65% of the total power consumption respectively. Compared to cell library design, gate array designed chips consume about 10% more power, and power reduction in full custom designed chips could be 15%. >
456 citations
TL;DR: In this article, two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level, one uses non-complementary signal inputs and the least number of transistors, while the other one improves the performance of the prior method but two more transistors are utilized.
Abstract: Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method uses non-complementary signal inputs and the least number of transistors. The other one improves the performance of the prior method but two more transistors are utilized. Both of them have been fully simulated by HSPICE on a SUN SPARC 2 workstation. >
355 citations
TL;DR: In this article, a simple approach in the design of composite field effect transistors with low output conductance is presented, where the transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connecting to the source terminal.
Abstract: This paper presents a simple approach in the design of composite field effect transistors with low output conductance. These transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connected to the source terminal. It is shown that this composite transistor has the same DC characteristics as a long-channel transistor of uniform width. A composite transistor has two main advantages over its "DC equivalent" transistor of uniform width: significant area savings and a higher cutoff frequency. The main application is low-voltage, high-frequency analog circuits. The proposed technique is particularly suited for analog design in gate arrays. >
227 citations
TL;DR: In this paper, a simple engineering approach for rapid simulation of cross-talk in mixed-mode IC's using SPICE is presented, which shows that while an SOI-based process provides high isolation from crosstalk at low operating frequencies, its benefit is lost at high frequencies.
Abstract: A simple engineering approach for rapid simulation of cross-talk in mixed-mode IC's using SPICE is presented. A side-by-side comparison of several cross-talk reduction schemes has shown that while an SOI-based process provides high isolation from cross-talk at low operating frequencies, its benefit is lost at high frequencies. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. Lumped parameter equivalent circuits have also been developed to represent different isolation schemes in SPICE. The isolation characteristics of test structures employing the above techniques are computed using SPICE and the results compared with two-dimensional device simulation. The results are also compared with experimental measurements on actual silicon to validate the models. >
211 citations
TL;DR: In this article, lowvoltage and low power (LV/LP) circuit design for both analog and digital LSI's is described for mixed analog/digital systems in portable equipment, including operational amplifiers, video-signal processing circuits, A/D and D/A converters, filters, and RF circuits.
Abstract: This paper describes low-voltage and low-power (LV/LP) circuit design for both analog LSI's and digital LSI's which are used in mixed analog/digital systems in portable equipment. We review some LV/LP circuits used in digital LSI's, such as general logic gate, DSP, and DRAM, and others used in analog LSI's, such as operational amplifiers, video-signal processing circuits, A/D and D/A converters, filters, and RF circuits, along with a wide range of items used in recently developed LSI's. Since analog circuits have fundamental difficulties in reducing the operating voltage and the power consumption, in spite of recent progress in LV/LP circuit techniques, these difficulties will be a major issue for decreasing the total power consumption of some mixed analog/digital systems used in portable equipment. >
191 citations
TL;DR: An exponential curvature compensation technique for bandgap references (BGR's) which exploits the temperature characteristics of the current gain /spl beta/ of a bipolar transistor is described in this article.
Abstract: An exponential curvature compensation technique for bandgap references (BGR's) which exploits the temperature characteristics of the current gain /spl beta/ of a bipolar transistor is described. This technique requires no additional circuits for the curvature compensation; only a size adjustment of a bias transistor in a conventional first-order compensated BGR is required. Positive and negative versions of the exponential curvature-compensated BGR have been fabricated using a 1.5 /spl mu/m BiCMOS process. Average temperature coefficients (TC's) of the negative BGR are measured as 2.4 and 6.7 ppm//spl deg/C, and those of the positive BGR are measured as 3.5 and 8.9 ppm//spl deg/C over the commercial (0/spl sim/70/spl deg/C) and military (-55/spl sim/125/spl deg/C) temperature ranges, respectively. These circuits dissipate 0.37 mW with a single 5 V supply, and occupy 270/spl times/150 /spl mu/m/sup 2/ and 290/spl times/150 /spl mu/m/sup 2/, respectively. >
153 citations
TL;DR: In this article, a new high-density DRAM cell concept is proposed and experimentally demonstrated, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle.
Abstract: A new high-density DRAM cell concept is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle. Since it does not need a large storage capacitance and one transistor is stacked on the top of the other transistor, the cell size is small and can be easily scaled down for future generations of memory devices. The unit cell size fabricated using a 4 M SRAM process without any process modification is 1.8 /spl mu/m/spl times/2.85 /spl mu/m. The proposed cell can be adopted to store multi-bit information. The fabricated prototype cell shows a resolution of about 3.5 bit. >
151 citations
TL;DR: This paper reviews several of the current-mode CMOS multiple-valued logic (MVL) circuits that have been studied over the past decade and their performance described.
Abstract: Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described. >
147 citations
TL;DR: Full digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters and can be applied to algorithmic converter configurations including pipelining, cyclic, or pipelined cyclic configurations.
Abstract: This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-/spl mu/m CMOS process. The ADC operates at 600 ks/s using 45 mW of power at /spl plusmn/2.5 V supplies. The active die area excluding the external logic circuit is 1 mm/sup 2/. Maximum DNL of /spl plusmn/0.6 LSB and INL of /spl plusmn/1 LSB at a 12-b resolution have been achieved. >
142 citations
TL;DR: In this article, the effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated, and a model that is capable of predicting the thermal noises of both long and short channel devices in both the triode and saturation regions is presented.
Abstract: The effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated. The experimental results show that the conventional MOSFET thermal noise models do not accurately predict the thermal noise of MOSFET's. A model that is capable of predicting the thermal noise of both long and short channel devices in both the triode and saturation regions is presented. This model, which can be easily implemented into existing circuit simulators such as SPICE, has been verified by a wide variety of measurements. >
141 citations
TL;DR: A list of generic layout rules and a layout scheme that predict matching accuracies better than 0.1% for the individual systematic error sources using capacitor sizes in the range of 20-40 /spl mu/m are developed.
Abstract: Precise capacitor ratios are employed in a variety of analog and mixed signal integrated circuits. The use of identical unit capacitors to form larger capacitances can easily produce 1% accuracy, but, in many cases, 0.1% accuracy can provide important performance advantages. Unfortunately, the ultimate matching precision of the ratio is limited by a number of systematic and random error sources. We have analyzed the source and significance of the systematic error sources on actual integrated circuit layouts and isolated five key contributors. Based on this analysis, we have developed a list of generic layout rules and a layout scheme that predict matching accuracies better than 0.1% for the individual systematic error sources using capacitor sizes in the range of 20-40 /spl mu/m. >
TL;DR: Possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits are identified.
Abstract: Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits. >
TL;DR: This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories and a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV.
Abstract: This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-/spl mu/m NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-/spl mu/s random access time with a 2.7-V power supply. The page-programming is completed after the 40-/spl mu/s program and 2.8-/spl mu/s verify read cycle is iterated 4 times. The block-erasing time is 10 ms. >
TL;DR: In this article, an improved model for the ramp response of a CMOS inverter has been derived where the influences of the short-circuit current and the input-to-output coupling capacitance are considered.
Abstract: An improved model for the ramp response of a CMOS inverter has been derived where the influences of the short-circuit current and the input-to-output coupling capacitance are considered. These effects modify the ideal linear relationship between the inverter propagation delay and the input ramp rise/fall time by adding a term proportional to the charge supplied by the short-circuiting transistor. This term is shown to contain first- and second-order contributions of the input ramp rise/fall time where the second-order contribution effectively models the propagation delay roll-off for slow input ramps. Both the first and the second-order effects are found to be affected by the P-to-N-channel gain ratio. The model shows excellent agreement with SPICE level 3 simulations; even when the short-circuiting transistor has a driving capability twice that of the charging/discharging transistor the error in the propagation delay is only about 2% for a slow input ramp (input-to-output slope-ratio at V/sub DD//2 equal to 1:2). >
TL;DR: The approach of an all-digital phase locked loop is used in this delay-locked loop circuit, which allows maximum utilization of the bus, as the minimal skew between the clocks of the two components significantly reduces idle periods, and also set-up and hold times.
Abstract: The approach of an all-digital phase locked loop is used in this delay-locked loop circuit. This design is designated to a system with two processing units, a master CPU and a slave system chip, that share the same bus. It allows maximum utilization of the bus, as the minimal skew between the clocks of the two components significantly reduces idle periods, and also set-up and hold times. Changes in the operating frequency are possible, without falling out of synchronization. Due to the special lead-lag phase detector, the jitter of the clock is zero, when the loop is locked, under any working conditions. >
TL;DR: An analog neural system made by combining LSI's with feedback connections is promising for implementing continuous-time models of recurrent networks with real-time learning.
Abstract: This paper proposes an all-analog neural network LSI architecture and a new learning procedure called contrastive backpropagation learning In analog neural LSI's with on-chip backpropagation learning, inevitable offset errors that arise in the learning circuits seriously degrade the learning performance Using the learning procedure proposed here, offset errors are canceled to a large extent and the effect of offset errors on the learning performance is minimized This paper also describes a prototype LSI with 9 neurons and 81 synapses based on the proposed architecture which is capable of continuous neuron-state and continuous-time operation because of its fully analog and fully parallel property Therefore, an analog neural system made by combining LSI's with feedback connections is promising for implementing continuous-time models of recurrent networks with real-time learning >
TL;DR: This paper presents a low-power, area-efficient, mask-programmable digital filter for decimation and interpolation in digital-audio applications and several architectural and implementation features reduce the complexity of the filter and allow its realization in a die area of only 3670 mils/sup 2.
Abstract: The area and power consumption of oversampled data converters are governed largely by the associated digital decimation and interpolation filters. This paper presents a low-power, area-efficient, mask-programmable digital filter for decimation and interpolation in digital-audio applications. Several architectural and implementation features reduce the complexity of the filter and allow its realization in a die area of only 3670 mils/sup 2/ (2.37 mm/sup 2/) in a 1-/spl mu/m CMOS technology. The use of simple multiplier-free arithmetic logic and a new memory addressing scheme for multi rate digital filters results in a power consumption of only 18.8 mW from a 5-V supply and 6.5 mW from a 3-V supply. The memory addressing scheme and the programmable functionality of the filter are general enough to implement a wide class of FIR and IIR single-rate and multi-rate digital filters. >
TL;DR: In this article, the authors measured a total of about 1400 PMOS and NMOS transistors produced in four different processes and reported the results in terms of mismatch dependance on current density, device dimensions, and substrate voltage, without using any specific model for the transistor.
Abstract: Measures the current matching properties of MOS transistors operated in the weak inversion region. The authors measured a total of about 1400 PMOS and NMOS transistors produced in four different processes and report the results in terms of mismatch dependance on current density, device dimensions, and substrate voltage, without using any specific model for the transistor. >
TL;DR: An electrothermal simulator (ETS) as discussed by the authors is a combination of SPICE with finite element code, in a relaxation procedure, which simulates the full electro-thermal behavior of integrated circuits.
Abstract: An accurate prediction of the electrothermal behavior of power integrated devices is required to design circuits in an efficient way. An electrothermal simulator (ETS) is a combination of SPICE with finite element code, in a relaxation procedure. It simulates the full electrothermal behavior of integrated circuits. Static and dynamic simulations of typical examples, reveal the value of ETS for high-power applications. Some specific design rules are derived. They are simple formulas, which estimate the temperature (gradients) on chip. They can be used before any CPU-time consuming simulation takes place which allows a more efficient design and prototype phase. >
TL;DR: In this paper, a four-quadrant CMOS analog multiplier is presented, which uses the square-law characteristic of an MOS transistor in saturation, and is suitable for use in the implementation of artificial neural networks.
Abstract: A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 /spl mu/m CMOS process. Experimental results obtained from it are presented. >
TL;DR: In this article, a CMOS buffer amplifier with symmetric operation at both the input and output is presented. But the output stage allows the use of gate channel capacitors of standard MOSFET's as the compensation capacitor saving die area from 80%/spl sim/93% in a standard single polysilicon digital process.
Abstract: This paper presents a CMOS buffer amplifier which operates on a single 5-V power supply. The uniquely symmetrical design adds the following advantages: rail-to-rail linear, symmetrical operation at both the input and output; the output stage allows the use of gate channel capacitors of standard MOSFET's as the compensation capacitor saving die area from 80%/spl sim/93% in a standard single polysilicon digital process; large gain-bandwidth product; high power supply rejection ratio; good common-mode rejection ratio; and easy compact layout suitable for design automation (layout as a parametric cell, allows easy adaption to changing processes). The buffer is capable of driving 300 /spl Omega//spl par/100 pF with a loaded gain-bandwidth product of more than 4 MHz and a fully loaded slew rate of greater than 4 V//spl mu/S. >
TL;DR: In this article, an automatic offset compensation scheme for CMOS operational amplifiers is presented, where offset is reduced by digitally adjusting the bias voltage of a programmable current mirror which is used as the load of the differential input stage.
Abstract: An automatic offset compensation scheme for CMOS operational amplifiers is presented. Offset is reduced by digitally adjusting the bias voltage of a programmable current mirror which is used as the load of the differential input stage. A 100% operating duty cycle is obtained by using a ping-pong structure. The offset compensation scheme is inherently time and temperature stable since the offset compensation is periodically performed with the ping-pong control. The proposed circuit has been fabricated using a 1.0 /spl mu/m n-well CMOS process. The measured offset voltages of the test circuits are less than 400 /spl mu/V in magnitude. >
TL;DR: The design of an 8-bit CMOS A/D converter is described which is intended for embedded operation in VLSI chips for video applications and a comparator circuit is shown which realizes a high bandwidth.
Abstract: The design of an 8-bit CMOS A/D converter is described which is intended for embedded operation in VLSI chips for video applications. The requirements on accuracy are analyzed and a comparator circuit is shown which realizes a high bandwidth. The full-flash architecture operates on wideband signals like CVBS in television systems. The A/D converter core measures 2.8 mm/sup 2/ in a 1 /spl mu/m CMOS process. The embedded operation of the A/D converter is illustrated on a video line-resizing chip. >
TL;DR: In this article, the authors present a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities, which consist of regular arrangements of elementary units, called smart pixels, made with vertical CMOS-BJT's connected in a Darlington structure.
Abstract: This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT's connected in a Darlington structure. Pixel smartness is achieved by exploiting the cellular neural network paradigm, incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-/spl mu/m technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm/sup 2/, with a power consumption down to 105 /spl mu/W/unit and image processing times below 2 /spl mu/s. >
TL;DR: In this article, a monolithic integrated driver circuit for laser modulation in a 10 Gb/s optical fiber link is presented, which can be operated up to 14 Gb with a maximum output voltage swing as high as 3.6 V at 50 /spl Omega/ load, corresponding to an internal current swing of 108 mA.
Abstract: A monolithic integrated driver circuit developed for laser modulation in a 10 Gb/s optical-fiber link is presented. The IC was fabricated in a self-aligned double-polysilicon Si-bipolar production technology with f/sub T//spl ap/25 GHz. The circuit can be operated up to 14 Gb/s with a maximum output voltage swing as high as 3.6 V at 50 /spl Omega/ load (corresponding to an internal current swing of 108 mA), which allows the circuit to drive external modulators. In addition, the circuit can be used for direct laser modulation at 10 Gb/s, since the output current swing can easily be controlled over a wide range (e.g., from 15 mA to 60 mA). Problems in the design of such driver circuits as well as their solutions are discussed in detail. >
TL;DR: A new wide-range CMOS four-quadrant multiplier using the bias feedback techniques is presented and it is shown that the linear range is over /spl plusmn/1 V and the linearity error is less than 1% over a 13 V input range.
Abstract: A new wide-range CMOS four-quadrant multiplier using the bias feedback techniques is presented. Simulation results show that for a power supply of /spl plusmn/5 V, the linear range is over 14 V and the linearity error is less than 1% over a 13 V input range. Experimental results show that the linear range is over /spl plusmn/1 V. The results will be useful in analog signal processing applications. >
TL;DR: The evolution of operational amplifier designs since vacuum tube days is traced to give a perspective of the large number of circuit variations used over time and the ability to use many of these circuit design options as the basis of new amplifiers.
Abstract: Strengths and weaknesses of modern wide-bandwidth bipolar transistor operational amplifiers are investigated and compared with respect to bandwidth, slew rate, noise, distortion, and power This paper traces the evolution of operational amplifier designs since vacuum tube days to give a perspective of the large number of circuit variations used over time Of particular value is the ability to use many of these circuit design options as the basis of new amplifiers In addition, an array of operational amplifier components fabricated on the AT&T CBIC V2 process is described This design incorporates many of the architectural techniques that have evolved over the years to produce four separate operational amplifier on a single base wafer The process design methodology requires identifying the common elements in each architecture and the minimum number of additional components required to implement four unique architectures on the array >
TL;DR: In this article, both uniform and non-uniform tapered buffers are considered and an analytical solution of the optimum tapering factor for a minimum power-delay product, which is about 1.5/spl sim/2 times larger than that for the minimum propagation delay, is presented.
Abstract: The tapered buffer is analyzed from the viewpoint of power dissipation. Both uniform and nonuniform tapered buffers are considered. It is found that there is an optimum value of tapering factor for a minimum power-delay product. In case of uniform tapering, we can obtain an analytical solution of the optimum tapering factor for a minimum power-delay product, which is about 1.5/spl sim/2 times larger than that for a minimum propagation delay. It is also found that there exists a nonuniform tapering factor which gives a global optimum condition for a minimum power-delay product, which, however, results in a larger short-circuit current. Compared with a uniform buffer, a nonuniform tapered buffer shows about 8% improvement in dynamic switching energy, and 3/spl sim/5% improvement in total switching energy. We confirm this by simulating tapered buffers with SPICE. >
TL;DR: A 16-Mb flash EEPROM has been developed based on the 0.6-/spl mu/m triple-well double-poly-Si single-metal CMOS technology to overcome the overerase problem that causes read operation failure and internal voltage generators independent of the external voltage supply and temperature have been developed.
Abstract: A 16-Mb flash EEPROM has been developed based on the 0.6-/spl mu/m triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 /spl mu/m/spl times/1.7 /spl mu/m, resulting in a die size of 7.7 mm/spl times/17.32 mm. >
NEC1
TL;DR: A 3.3-V 512-k/spl times/18-b/Spl times/2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture that minimizes an increase in die size.
Abstract: A 3.3-V 512-k/spl times/18-b/spl times/2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm/sup 2/, which is the same die size as the conventional DRAM, has been achieved with 0.50-/spl mu/m CMOS process technology. >