Showing papers in "IEEE Journal of Solid-state Circuits in 1996"
TL;DR: In this paper, the phase noise in two inductorless CMOS oscillators is analyzed and a new definition of phase noise is defined, and two prototypes fabricated in a 0.5/spl mu/m CMOS technology are used to investigate the accuracy of the theoretical predictions.
Abstract: This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-/spl mu/m CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB.
1,012Â citations
TL;DR: In this paper, an analytical model for the access and cycle times of on-chip direct-mapped and set-associative caches is presented, where the inputs to the model are the cache size, block size, and associativity, as well as array organization and process parameters.
Abstract: This paper describes an analytical model for the access and cycle times of on-chip direct-mapped and set-associative caches. The inputs to the model are the cache size, block size, and associativity, as well as array organization and process parameters. The model gives estimates that are within 6% of Hspice results for the circuits we have chosen. This model extends previous models and fixes many of their major shortcomings. New features include models for the tag array, comparator, and multiplexor drivers, nonstep stage input slopes, rectangular stacking of memory subarrays, a transistor-level decoder model, column-multiplexed bitlines controlled by an additional array organizational parameter, load-dependent size transistors for wordline drivers, and output of cycle times as well as access times. Software implementing the model is available via ftp.
829Â citations
TL;DR: It is found that careful design reduced the energy dissipation by almost 25% and methods of reducing energy consumption that do not lead to performance loss, and methods to reduce delay by exploiting instruction level parallelism are explored.
Abstract: In this paper we investigate possible ways to improve the energy efficiency of a general purpose microprocessor. We show that the energy of a processor depends on its performance, so we chose the energy-delay product to compare different processors. To improve the energy-delay product we explore methods of reducing energy consumption that do not lead to performance loss (i.e. wasted energy), and explore methods to reduce delay by exploiting instruction level parallelism. We found that careful design reduced the energy dissipation by almost 25%. Pipelining can give approximately a 2/spl times/ improvement in energy-delay product. Superscalar issue, however, does not improve the energy-delay product any further since the overhead required offsets the gains in performance. Further improvements will be hard to come by since a large fraction of the energy (50-80%) is dissipated in the clock network and the on-chip memories. Thus, the efficiency of processors will depend more on the technology being used and the algorithm chosen by the programmer than the micro-architecture.
635Â citations
TL;DR: In this paper, a new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used.
Abstract: A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).
604Â citations
TL;DR: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit and shows four to six times power reduction with a practical loading and operation frequency range.
Abstract: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-/spl mu/m CMOS technology with a reduced threshold voltage of 0.2 V.
503Â citations
TL;DR: An integrated low-noise amplifier and down-conversion mixer operating at 1 GHz has been fabricated for the first time in 1 /spl mu/m CMOS as discussed by the authors, where the overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, and the IIP3 is +8 dBm.
Abstract: An integrated low-noise amplifier and downconversion mixer operating at 1 GHz has been fabricated for the first time in 1 /spl mu/m CMOS. The overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, the IIP3 is +8 dBm, and the circuit takes 9 mA from a 3 V supply. Circuit design methods which exploit the features of CMOS well suited to these functions are in large part responsible for this performance. The front-end is also characterized in several other ways relevant to direct-conversion receivers.
360Â citations
TL;DR: In this article, a high-speed complementary bipolar process was used to construct a rectangular spiral inductor with Q's over 12 for use in wireless applications, and an accurate broadband model for the inductors has been developed, and a test filter and mixer have been built to verify the performance of inductors and the accuracy of the model.
Abstract: Rectangular spiral inductors with Q's over 12 have been built in a high-speed complementary bipolar process and characterized for use in wireless applications. An accurate broadband model for the inductors has been developed, and a test filter and mixer have been built to verify the performance of the inductors and the accuracy of the model.
315Â citations
TL;DR: In this article, the fundamental mechanical and electronic noise floors for representative capacitive position-sensing interface circuits are discussed, and analog and digital closed-loop accelerometers are compared, with the latter using highfrequency voltage pulses to apply force quanta to the microstructure and achieve a very linear response.
Abstract: Surface micromachining has enabled the cofabrication of thin-film micromechanical structures and CMOS or bipolar/MOS integrated circuits. Using linear, single-axis accelerometers as a motivating example, this paper discusses the fundamental mechanical as well as the electronic noise floors for representative capacitive position-sensing interface circuits. Operation in vacuum lowers the Brownian noise of a polysilicon accelerometer to below 1 /spl mu/g//spl radic/(Hz). For improved sensor performance, the position of the microstructure should be controlled using electrostatic force-feedback. Both analog and digital closed-loop accelerometers are described and contrasted, with the latter using high-frequency voltage pulses to apply force quanta to the microstructure and achieve a very linear response.
302Â citations
TL;DR: In this article, a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance is presented, which uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm.
Abstract: This paper describes a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance. The technique uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm. It is demonstrated that this technique is suitable for optimization of layout for minimization of substrate coupling. Analysis of substrate coupling in different types of substrates and the utility of guard rings in different types of substrates is also discussed. Experimental verification of the models is presented.
299Â citations
TL;DR: A CMOS smart temperature sensor with digital output that consumes only 7 /spl mu/W and is equipped with a facility that switches off the supply power after each sample is presented.
Abstract: A CMOS smart temperature sensor with digital output is presented It consumes only 7 /spl mu/W To achieve this extremely low-power consumption, the system is equipped with a facility that switches off the supply power after each sample The circuit uses substrate bipolars as a temperature sensor Conversion to the digital domain is done by a sigma-delta converter which makes the circuit highly insensitive to digital interference The complete system is realized in a standard CMOS process and measures only 15 mm/sup 2/ In the temperature range from -40 to +120/spl deg/C, the inaccuracy is /spl plusmn/1/spl deg/C after calibration at two temperatures The circuit operates at supply voltages down to 22 V
299Â citations
TL;DR: In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high speed potential of advanced Si-bipolar technologies, starting from the most promising circuit concepts and an adequate resistance level, the dimensions of individual transistors in the IC's must be optimized very carefully using advanced transistor models.
Abstract: In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the IC's must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links.
TL;DR: In this article, a dual-modulus divide-by-128/129 prescaler was developed in a 0.7-/spl mu/m CMOS technology, which enables the limitation of the high-speed section of the precaler to only one divideby-two flipflop.
Abstract: A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-/spl mu/m CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz.
TL;DR: The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three, demonstrating that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost.
Abstract: The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with conventional cell based design. An extremely simple cell library with only seven cells combined with a synthesis tool called "circuit inventor" is compared with the conventional CMOS library that has over 60 cells combined with the state-of-the-art logic synthesis. The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three. This demonstrates that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost. Key issues which have to be cleared before pass transistor logic is used as the generic logic scheme replacing CMOS are also discussed.
TL;DR: In this article, the authors presented circuit techniques for CMOS low-power high-performance multiplier design using 0.8-/spl mu/m CMOS (in BiCMOS) technology.
Abstract: In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-/spl mu/m CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16/spl times/16)-b multiplier using the Booth algorithm, a (6/spl times/6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6/spl times/6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS.
TL;DR: This approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality and efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility.
Abstract: We present efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion. Our algorithms are able to minimize a cost function subject to given timing constraints; we focus on minimization of dynamic power dissipation, but the algorithm is also easily adaptable to, for example, area minimization. In addition, the algorithm efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility. An extension of our basic algorithm accommodates a generalized delay model which takes into account the effect of signal slew on buffer delay which can contribute substantially to overall delay. To the best of our knowledge, our approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality. The effectiveness of these methods is demonstrated experimentally.
TL;DR: The VBIC95 bipolar junction transistor (BJT) model was developed as an industry standard replacement for the SPICE Gummel-Poon (SGP) model, to improve deficiencies of the SGP model that have become apparent over time as mentioned in this paper.
Abstract: This paper details the VBIC95 bipolar junction transistor (BJT) model. The model was developed as an industry standard replacement for the SPICE Gummel-Poon (SGP) model, to improve deficiencies of the SGP model that have become apparent over time because of the advances in BJT process technology. VBIC95 is still based on the Gummel-Poon formulation, and thus can degenerate to be similar to the familiar SGP model. However, it includes improved modeling of the Early effect, quasi-saturation, substrate and oxide parasitics, avalanche multiplication, and temperature behavior that can be invoked selectively based on model parameter values.
TL;DR: In this paper, a 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation by using a high swing residue amplifier and by optimizing the per stage resolution.
Abstract: A 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 /spl mu/m CMOS process displayed 80.1 dB peak signal-to-noise plus distortion ratio (SNDR) and 82.9 dB dynamic range. Integral nonlinearity (INL) is 0.8 least significant bits (LSB), and differential nonlinearity (DNL) is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply.
TL;DR: A 128-Mb multilevel NAND flash memory storing 2 b per cell, made practical by significantly reducing program disturbance by using a local self-boosting scheme, for mass storage, low cost, and high serial access throughput.
Abstract: For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-/spl mu/m CMOS technology, resulting in a 117 mm/sup 2/ die size and a 1.1 /spl mu/m/sup 2/ effective cell size.
TL;DR: In this paper, a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits is introduced, based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well.
Abstract: This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and /spl eta/, which reflects the drain induced barrier lowering, are also addressed.
TL;DR: An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology, resulting in a 75 MHz maximum full-scale input signal frequency.
Abstract: An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm/sup 2/ in 0.5-/spl mu/m standard digital CMOS technology.
TL;DR: In this article, the authors describe the principle and design of a differential CMOS low-distortion variable-gain amplifier for high-frequency (video) applications, which has a gain accuracy of 0.05 dB over the -2 to +12 dB gain range for single-sided input signals.
Abstract: The overall system performance of mixed-signal CMOS IC's is largely determined by the dynamic performance of the analog front-ends. System features are, in contrast, mainly set by the digital architecture. In order to optimize the dynamic range of the system and to minimize the sensitivity to substrate noise, the analog-to-digital converter (ADC) has to be preceded by a variable-gain amplifier (VGA) and a differential circuit topology for the complete front-end to be adopted. Since most of present-day applications are based on single-sided signal source definitions, the differential-input VGA must be able to perform a single-to-differential signal conversion. This paper describes the principle and design of a differential CMOS low-distortion variable-gain amplifier for high-frequency (video) applications. Experimental results of the circuit show total harmonic distortion figures better than -60 dB and a gain accuracy of 0.05 dB over the -2 to +12 dB gain range for single-sided input signals.
TL;DR: In this article, the Yuan-Svensson D-flip-flop (D-FF) was analyzed and a general purpose, general purpose and faster D-FF was presented, running at frequencies from tens of hertz to a couple of gigahertz.
Abstract: In digital circuits, a transistor connected to a particular circuit node does not always load that node by a gate capacitance proportional to C/sub ox/WL if the transistors connected to its source are turned off. Such an observation, illustrated in this paper by a detailed analysis of the Yuan-Svensson D-flip-flop (D-FF) can be used to advantage both in sizing the transistors and in developing better configurations. A glitch-free, general purpose, and faster D-FF is presented here which has complementary outputs and runs at frequencies from tens of hertz to a couple of gigahertz for a 1-/spl mu/m CMOS technology. Measured maximum clock frequency of a divide-by-16 circuit is 2.65 GHz at 5 V supply, whereas that of a dual-modulus frequency prescaler, dividing by 64/65, goes up to 1.6 GHz at 5 V.
TL;DR: An algorithmic approach to the design of low-power frequency-selective digital filters based on the concepts of adaptive filtering and approximate processing to reduce the total switched capacitance by dynamically varying the filter order based on signal statistics.
Abstract: We present an algorithmic approach to the design of low-power frequency-selective digital filters based on the concepts of adaptive filtering and approximate processing. The proposed approach uses a feedback mechanism in conjunction with well-known implementation structures for finite impulse response (FIR) and infinite impulse response (IIR) digital filters. Our algorithm is designed to reduce the total switched capacitance by dynamically varying the filter order based on signal statistics. A factor of 10 reduction in power consumption over fixed-order filters is demonstrated for the filtering of speech signals.
TL;DR: In this paper, a low-profile micromachined CMOS probe for multisite stimulation and recording in the central nervous system is described, which uses flexible silicon interconnects to allow the signal processing portion of the probe to fold at right angles to the penetrating probe shanks.
Abstract: Describes a low-profile micromachined CMOS probe for multisite stimulation and recording in the central nervous system. The probe uses flexible silicon interconnects to allow the signal processing portion of the probe to fold at right angles to the penetrating probe shanks, limiting the implanted profile above the cortex to less than 1 mm. The probe is designed to stimulate a 4 mm/sup 3/ volume of neural tissue with a spatial resolution of 400 /spl mu/m using 1000 /spl mu/m/sup 2/ electrode sites. Eight of the 64 sites on the probe can be driven simultaneously over a current range from -127 /spl mu/A to +127 /spl mu/A with 1 /spl mu/A resolution. An on-chip preamplifier allows the neural activity on any selected site to be recorded with an overall gain of 30 and bandwidth from 50 Hz to 9 kHz. The probe operates with a stimulus current linearity of 0.98 up to clock frequencies as high as 5 MHz and dissipates less than 15 /spl mu/A in standby from /spl plusmn/5 V supplies.
NEC1
TL;DR: An adaptive pipeline (APL) technique is described, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations, and it is shown that MOS current-mode logic circuits are suitable for a low-noise variable delay circuit.
Abstract: This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.
CERN1
TL;DR: In this article, the authors describe the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions.
Abstract: This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 /spl mu/m CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives.
TL;DR: In this paper, a second-order active bandpass filter using integrated inductors was implemented in Si bipolar technology, which uses special techniques to make the quality factor and the center frequency tunable.
Abstract: A second-order active bandpass filter using integrated inductors was implemented in Si bipolar technology. The filter uses special techniques to make the quality factor and the center frequency tunable. For a nominal center frequency of 1.8 GHz and a quality factor of 35, the filter has 1 dB compression dynamic range of 40 dB, and draws 8.7 mA from a 2.8 V supply.
TL;DR: In this paper, a 1.2 GHz dual-modulus prescaler IC fabricated with 0.8 /spl mu/m CMOS technology is presented, which includes a synchronous counter and an asynchronous counter.
Abstract: A 1.2 GHz dual-modulus prescaler IC fabricated with 0.8 /spl mu/m CMOS technology is presented in this paper. The dual-modulus prescaler includes a synchronous counter (divide-by-4/5) and an asynchronous counter (divide-by-32). A new dynamic D-flip-flop (DFF) is developed for the high-speed synchronous counter. The maximum operating frequency of 1.22 GHz with power consumption of 25.5 mW has been measured at 5 V supply voltage.
TL;DR: In this paper, the first stage of frequency down conversion is implemented with a subsampling switched-capacitor sample-and-hold circuit clocked at 78 MHz, followed by discrete-time analog filters.
Abstract: Discrete-time analog filters, rather than off-chip components, have been used to perform frequency selection and down conversion in the integrated front-end for a 900-MHz RF receiver. The first stage of frequency down conversion is implemented with a subsampling switched-capacitor sample-and-hold circuit clocked at 78 MHz. Subsequent stages of discrete-time filtering are realized using switched-capacitor biquadratic filters. An experimental prototype of the front-end had been integrated in a 0.6-/spl mu/m BiCMOS technology. The circuit provides a system gain of 36 dB and 32 dB suppression of interfering channels over a 40 MHz bandwidth. Referred to the system input, the third-order intercept-point is -16 dBm, and the spot input-referred noise is -82 dBm over a 30 kHz bandwidth. The experimental circuit dissipates 90 mW from a 3.3-V supply and occupies an active area of 1.9/spl times/1.9 mm/sup 2/.
TL;DR: A low-power microprocessor clock generator based upon a phase-locked loop (PLL) that is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-/spl mu/m triple-metal CMOS process without the need for external components is described.
Abstract: This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-/spl mu/m triple-metal CMOS process without the need for external components. It operates from a supply voltage down to 1 V at a VCO frequency of 320 MHz. The PLL power consumption is lower than 1.2 mW at 1.35 V for the same frequency. The maximum measured cycle-to-cycle jitter is /spl plusmn/150 ps with a square wave superposed to the supply voltage with a peak-to-peak amplitude of 200 mV and rise/fall time of about 30 ps. The input frequency is 3.68 MHz and the PLL internal frequency ranges from 176 MHz up to 574 MHz, which correspond to a multiplication factor of about 100.