Showing papers in "IEEE Journal of Solid-state Circuits in 1999"
TL;DR: In this paper, the authors present simple and accurate expressions for the DC inductance of square, hexagonal, octagonal, and circular spiral inductors, and evaluate the accuracy of their expressions, as well as several previously published inductance expressions, in two ways: by comparison with three-dimensional field solver predictions and by contrast with their own measurements, and also previously published measurements.
Abstract: We present several new simple and accurate expressions for the DC inductance of square, hexagonal, octagonal, and circular spiral inductors. We evaluate the accuracy of our expressions, as well as several previously published inductance expressions, in two ways: by comparison with three-dimensional field solver predictions and by comparison with our own measurements, and also previously published measurements. Our simple expression matches the field solver inductance values typically within around 3%, about an order of magnitude better than the previously published expressions, which have typical errors ground 20% (or more). Comparison with measured values gives similar results: our expressions (and, indeed, the field solver results) match within around 5%, compared to errors of around 20% for the previously published expressions. (We believe most of the additional errors in the comparison to published measured values is due to the variety of experimental conditions under which the inductance was measured.) Our simple expressions are accurate enough for design and optimization of inductors or of circuits incorporating inductors. Indeed, since inductor tolerance is typically on the order of several percent, "more accurate" expressions are not really needed in practice.
1,498Â citations
TL;DR: A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented in this paper, where the impulse sensitivity functions are used to derive expressions for the jitter.
Abstract: A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed.
1,059Â citations
TL;DR: In this article, an analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators is presented, and the effect of tail current and tank power dissipation on the voltage amplitude is shown.
Abstract: An analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators is presented. The effect of tail current and tank power dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. The predictions are in good agreement with measurements over a large range of tail currents and supply voltages. A 1.8 GHz LC oscillator with a phase noise of -121 dBc/Hz at 600 kHz is demonstrated, dissipating 6 mW of power using on-chip spiral inductors.
972Â citations
TL;DR: In this paper, a 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6/spl mu/m CMOS technology.
Abstract: A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.
966Â citations
TL;DR: In this paper, the authors proposed a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, and measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.
Abstract: This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the sum of the built-in voltage of the diode V/sub f/ and the thermal voltage V/sub T/ of kT/q multiplied by a constant. Therefore, V/sub ref/ is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V/sub ref/ has been converted from the sum of two currents; one is proportional to V/sub f/ and the other is proportional to V/sub T/. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-/spl mu/m flash memory process. Measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.
820Â citations
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Abstract: In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.
660Â citations
TL;DR: In this paper, the authors describe a three-axis accelerometer implemented in a surface-micromachining technology with integrated CMOS, which measures changes in a capacitive half-bridge to detect deflections of a proof mass, which result from acceleration input.
Abstract: This paper describes a three-axis accelerometer implemented in a surface-micromachining technology with integrated CMOS. The accelerometer measures changes in a capacitive half-bridge to detect deflections of a proof mass, which result from acceleration input. The half-bridge is connected to a fully differential position-sense interface, the output of which is used for one-bit force feedback. By enclosing the proof mass in a one-bit feedback loop, simultaneous force balancing and analog-to-digital conversion are achieved. On-chip digital offset-trim electronics enable compensation of random offset in the electronic interface. Analytical performance calculations are shown to accurately model device behaviour. The fabricated single-chip accelerometer measures 4/spl times/4 mm/sup 2/, draws 27 mA from a 5-V supply, and has a dynamic range of 84, 81, and 70 dB along the x-, y-, and z-axes, respectively.
492Â citations
TL;DR: In this article, a monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability.
Abstract: A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is discussed that utilizes a unique, gain-controllable transresistance sustaining amplifier. We show that in the absence of an automatic level control loop, the closed-loop, steady-state oscillation amplitude of this oscillator depends strongly upon the dc-bias voltage applied to the capacitively driven and sensed /spl mu/resonator. Although the high-Q of the micromechanical resonator does contribute to improved oscillator stability, its limited power-handling ability outweighs the Q benefits and prevents this oscillator from achieving the high short-term stability normally expected of high-Q oscillators.
431Â citations
TL;DR: In this article, a first-order differential equation is derived for the noise dynamics of injection-locked oscillators, and a single-ended ILFD is designed in a 0.5-/spl mu/m CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mW of power.
Abstract: Injection-locked oscillators (ILOs) are investigated in a new theoretical approach. A first-order differential equation is derived for the noise dynamics of ILOs. A single-ended injection-locked frequency divider (SILFD) is designed in a 0.5-/spl mu/m CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mW of power. A differential injection-locked frequency divider (DILFD) is designed in a 0.5-/spl mu/m CMOS technology operating at 3 GHz and consuming 0.45 mW, with a 190 MHz locking range. A locking range of 370 MHz is achieved for the DILFD when the power consumption is increased to 1.2 mW.
429Â citations
TL;DR: This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.
Abstract: This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.
319Â citations
TL;DR: In this article, a 1-W, class-E power amplifier is implemented in a 0.35-/spl mu/m CMOS technology and suitable for operations up to 2 GHz.
Abstract: This paper presents a 1-W, class-E power amplifier that is implemented in a 0.35-/spl mu/m CMOS technology and suitable for operations up to 2 GHz. The concept of mode locking is used in the design, in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. A compact off-chip microstrip balun is also proposed for output differential-to-single-ended conversion. At 2-V supply and at 1.98 GHz, the power amplifier achieves 48% power-added efficiency (41% combined with the balun).
TL;DR: In this paper, a noise analysis of current-commutating CMOS mixers, such as the widely used CMOS Gilbert cell, is presented, where the contribution of all internal and external noise sources to the output noise is calculated.
Abstract: A noise analysis of current-commutating CMOS mixers, such as the widely used CMOS Gilbert cell, is presented. The contribution of all internal and external noise sources to the output noise is calculated. As a result, the noise figure can be rapidly estimated by computing only a few parameters or by reading them from provided normalized graphs. Simple explicit formulas for the noise introduced by a switching pair are derived, and the upper frequency limit of validity of the analysis is examined. Although capacitive effects are neglected, the results are applicable up to the gigahertz frequency range for modern submicrometer CMOS technologies. The deviation of the device characteristics from the ideal square law is taken into account, and the analysis is verified with measurements.
TL;DR: In this article, a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6/spl mu/m CMOS technology is described.
Abstract: This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-/spl mu/m CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset.
TL;DR: In this article, a digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process.
Abstract: A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.
TL;DR: This paper is an introduction to RF simulation methods and how they are applied to make common RF measurements.
Abstract: Radio-frequency (RF) circuits exhibit several distinguishing characteristics that make them difficult to simulate using traditional SPICE transient analysis. The various extensions to the harmonic balance and shooting method simulation algorithms are able to exploit these characteristics to provide rapid and accurate simulation for these circuits. This paper is an introduction to RF simulation methods and how they are applied to make common RF measurements. It describes the unique characteristics of RF circuits, the methods developed to simulate these circuits, and the application of these methods.
TL;DR: A set of characterization vehicles that can be employed to quantify the analog behaviour of active and passive devices in CMOS processes, in particular, properties that are not modeled accurately by SPICE parameters are described.
Abstract: The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today's "digital" technologies often proves inadequate for analog and RF design, mandating many additional measurements and iterations to arrive at an acceptable solution. This paper describes a set of characterization vehicles that can be employed to quantify the analog behaviour of active and passive devices in CMOS processes, in particular, properties that are not modeled accurately by SPICE parameters. Test structures and circuits are introduced for measuring speed, noise, linearity, loss, matching, and dc characteristics.
TL;DR: A general-purpose phase-locked loop (PLL) with programmable bit rates is presented demonstrating that large frequency tuning range, large power supply range, and low jitter can be achieved simultaneously.
Abstract: A general-purpose phase-locked loop (PLL) with programmable bit rates is presented demonstrating that large frequency tuning range, large power supply range, and low jitter can be achieved simultaneously. The clock recovery architecture uses phase selection for automatic initial frequency capture. The large period jitter of conventional phase selection is eliminated through feedback phase selection. Digital control sequencing of the feedback enables accurate phase interpolation without the traditional need of analog circuitry. Circuit techniques enabling low Vdd operation of a PLL with differential delay stages are presented. Measurements show a PLL frequency range of 1-200 MHz at Vdd=1.2 V linearly increasing to 2-1600 MHz at Vdd=2.5 V, achieved in a standard process technology without low threshold voltage devices. Correct operation has been verified down to Vdd=0.9 V, but the lower limit of differential operation with improved supply-noise rejection is estimated to be 1.1 V.
TL;DR: In this article, a digitally controlled power converter that dynamically tracks circuit performance with a ring oscillator and regulates the supply voltage to the minimum required to operate at a desired frequency is presented.
Abstract: A voltage scaling technique for energy-efficient operation requires an adaptive power-supply regulator to significantly reduce dynamic power consumption in synchronous digital circuits. A digitally controlled power converter that dynamically tracks circuit performance with a ring oscillator and regulates the supply voltage to the minimum required to operate at a desired frequency is presented. This paper investigates the issues involved in designing a fully digital power converter and describes a design fabricated in a MOSIS 0.8-/spl mu/m process. A variable-frequency digital controller design takes advantage of the power savings available through adaptive supply-voltage scaling and demonstrates converter efficiency greater than 90% over a dynamic range of regulated voltage levels.
TL;DR: This paper describes two CMOS bandgap-reference circuits featuring Dynamic-Threshold MOS transistors, aimed at application in low-voltage low-power ICs that tolerate medium accuracy and high accuracy operation without trimming.
Abstract: This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 /spl mu/W; the die area is 0.063 mm/sup 2/ in a standard digital 0.35-/spl mu/m CMOS process. The second bandgap reference circuit aims at high accuracy operation (/spl sigma/=0.3%) without trimming. It consumes approximately 5 /spl mu/W from a 1.8-V supply voltage and occupies 0.06 mm/sup 2/ in a standard 0.35-/spl mu/m CMOS process.
TL;DR: A qualitative understanding of the microwave characteristics of MOS transistors is provided in this article, which is directed toward helping analog IC circuit designers create better front-end radio-frequency CMOS circuits.
Abstract: This paper discusses design issues and the microwave properties of CMOS devices. A qualitative understanding of the microwave characteristics of MOS transistors is provided. The paper is directed toward helping analog IC circuit designers create better front end radio-frequency CMOS circuits. The network properties of CMOS devices, the frequency response, and the microwave noise properties are reviewed, and a summary of the microwave scaling rules is presented.
TL;DR: A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented, ideally suited to pixel-level implementation in a CMOS image sensor.
Abstract: A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320/spl times/256 sensor using the MCBS ADC is described. The chip measures 4.14/spl times/5.16 mm/sup 2/. It achieves 10/spl times/10 /spl mu/m/sup 2/ pixel size at 28% fill factor in 0.35 /spl mu/m CMOS technology. Each 2/spl times/2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively.
TL;DR: A new family of edge-triggered flip-flops has been developed that has the capability of easily incorporating logic functions with a small delay penalty, and greatly reduces the pipeline overhead.
Abstract: In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well.
TL;DR: In this article, a serial link transmitter fabricated in a large-scale integrated 0.4/spl mu/m CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects.
Abstract: A serial link transmitter fabricated in a large-scale integrated 0.4-/spl mu/m CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height >350 mV and a width >100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5/spl times/2.0 mm/sup 2/ of die area.
TL;DR: The architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC) is described and it is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath.
Abstract: This paper describes the architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC). It is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 1.0-/spl mu/m CMOS, and tested. The IC produces 16-b sine and cosine outputs with a spurious-free dynamic range of more than 100 dBc. A 36-b frequency control word gives a tuning resolution of 0.0015 Hz at a 100-MHz sampling rate.
TL;DR: In this article, the expected difficulties and some concepts for 0.1 and sub-0.1/spl mu/m LSIs are explained based on the research of the downsizing MOSFET into such a dimension.
Abstract: MOS large-scale-integration circuits (LSIs), having advanced remarkably during the past 25 years, are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems at the beginning of next century when the minimum feature size of LSIs is going to shift to 0.1 and sub-0.1 /spl mu/m. In this paper, the anticipated difficulties and some concepts for 0.1- and sub-0.1 /spl mu/m LSIs are explained based on the research of the downsizing MOSFET into such a dimension, and a further concept for deep sub-0.1-/spl mu/m LSIs is described.
CERN1
TL;DR: An architecture for a time interpolation circuit with an rms error of /spl sim/25 ps has been developed in a 0.7-/spl mu/m CMOS technology based on a delay locked loop driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit.
Abstract: An architecture for a time interpolation circuit with an rms error of /spl sim/25 ps has been developed in a 0.7-/spl mu/m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology.
TL;DR: Two different silicon implementations of the bitstream approach to generating analog signals with very low complexity and hardware requirements are presented, and their performance is analyzed through experimental results.
Abstract: A new method for generating analog signals with very low complexity and hardware requirements has recently been introduced. It consists of periodically reproducing short optimized bitstreams recorded from the output of a sigma-delta modulator. In this paper, various types of signals generated using the bitstream approach are discussed. Two different silicon implementations are presented, and their performance is analyzed through experimental results. Various ways in which the generators can be used are also demonstrated. Emphasis is placed on the simplicity of the design process and its compact implementation, which are crucial considerations when implementing a built-in self-test strategy.
TL;DR: In this article, the design challenges of a VCO with automatic amplitude control, which operates in the 300 MHz to 1.2 GHz frequency range using different external resonators, are presented.
Abstract: Voltage controlled oscillators (VCOs) used in portable wireless communications applications, such as cellular telephony, are required to achieve low phase-noise levels while consuming minimal power. This paper presents the design challenges of a VCO with automatic amplitude control, which operates in the 300 MHz to 1.2 GHz frequency range using different external resonators. The VCO phase noise level is -106 dBc/Hz at 100-KHz offset from an 800-MHz carrier, and it consumes 1.6 mA from a 2.7-V power supply. An extensive phase-noise analysis is employed for this VCO design in order to identify the most important noise sources in the circuit and to find the optimum tradeoff between noise performance and power consumption.
TL;DR: The design of a high-resolution high-speed delta-sigma analog-to-digital converter that operates from a single 3.3V supply is presented, which achieves a SNR of 87 dB, a SNDR of 82 dB and an input dynamic range of 15 bits after comb-filtering.
Abstract: The design of a high-resolution, high-speed, delta-sigma analog to-digital converter that operates from a single 3.3-V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switched-capacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 2-1-1 cascade topology with optimized coefficients. For an oversampling-ratio of only 24, the converter achieves a signal-to-noise ratio of 87 dB, a signal-to-(noise+distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-/spl mu/m CMOS technology, in a 5-mm/sup 2/ die area, and consumes 200 mW from a 3.3-V power supply.
TL;DR: In this article, the authors reported the highest frequency bipolar voltage-controlled oscillator (VCO) monolithic microwave integrated circuit (MMIC) so far reported, which is based on a push-push oscillator topology.
Abstract: This paper reports on what is believed to be the highest frequency bipolar voltage-controlled oscillator (VCO) monolithic microwave integrated circuit (MMIC) so far reported. The W-band VCO is based on a push-push oscillator topology, which employs InP HBT technology with peak f/sub T/'s and f/sub max/'s of 75 and 200 GHz, respectively. The W-band VCO produces a maximum oscillating frequency of 108 GHz and delivers an output power of +0.92 dBm into 50 /spl Omega/. The VCO also obtains a tuning bandwidth of 2.73 GHz or 2.6% using a monolithic varactor. A phase noise of -88 dBc/Hz and -109 dBc/Hz is achieved at 1- and 10-MHz offsets, respectively, and is believed to be the lowest phase noise reported for a monolithic W-band VCO. The push-push VCO design approach demonstrated in this work enables higher VCO frequency operation, lower noise performance, and smaller size, which is attractive for millimeter-wave frequency source applications.