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Showing papers in "IEEE Journal of Solid-state Circuits in 2003"


Journal ArticleDOI
TL;DR: In this article, a low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface is presented.
Abstract: There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

1,572 citations


Journal ArticleDOI
TL;DR: A novel fully integrated passive transponder IC with 4.5- or 9.25-m reading distance at 500-mW ERP or 4-W EIRP base-station transmit power, operating in the 868/915-MHz ISM band with an antenna gain less than -0.5 dB.
Abstract: This paper presents a novel fully integrated passive transponder IC with 4.5- or 9.25-m reading distance at 500-mW ERP or 4-W EIRP base-station transmit power, respectively, operating in the 868/915-MHz ISM band with an antenna gain less than -0.5 dB. Apart from the printed antenna, there are no external components. The IC is implemented in a 0.5-/spl mu/m digital two-poly two-metal digital CMOS technology with EEPROM and Schottky diodes. The IC's power supply is taken from the energy of the received RF electromagnetic field with help of a Schottky diode voltage multiplier. The IC includes dc power supply generation, phase shift keying backscatter modulator, pulse width modulation demodulator, EEPROM, and logic circuitry including some finite state machines handling the protocol used for wireless write and read access to the IC's EEPROM and for the anticollision procedure. The IC outperforms other reported radio-frequency identification ICs by a factor of three in terms of required receive power level for a given base-station transmit power and tag antenna gain.

875 citations


Journal ArticleDOI
TL;DR: In this paper, a 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented.
Abstract: A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.

450 citations


Journal ArticleDOI
TL;DR: In this article, an Arbitrated address-event imager was designed and fabricated in a 0.6-/spl mu/m CMOS process, which is composed of 80 /spl times/ 60 pixels of 32 /spltimes/ 30 /spl m/m. Tests conducted on the imager showed a large output dynamic range of 180 dB (under bright local illumination) for an individual pixel.
Abstract: An arbitrated address-event imager has been designed and fabricated in a 0.6-/spl mu/m CMOS process. The imager is composed of 80 /spl times/ 60 pixels of 32 /spl times/ 30 /spl mu/m. The value of the light intensity collected by each photosensitive element is inversely proportional to the pixel's interspike time interval. The readout of each spike is initiated by the individual pixel; therefore, the available output bandwidth is allocated according to pixel output demand. This encoding of light intensities favors brighter pixels, equalizes the number of integrated photons across light intensity, and minimizes power consumption. Tests conducted on the imager showed a large output dynamic range of 180 dB (under bright local illumination) for an individual pixel. The array, on the other hand, produced a dynamic range of 120 dB (under uniform bright illumination and when no lower bound was placed on the update rate per pixel). The dynamic range is 48.9 dB value at 30-pixel updates/s. Power consumption is 3.4 mW in uniform indoor light and a mean event rate of 200 kHz, which updates each pixel 41.6 times per second. The imager is capable of updating each pixel 8.3K times per second (under bright local illumination).

362 citations


Journal ArticleDOI
TL;DR: In this article, an integrated single-inductor dual-output boost converter is presented, which adopts time-multiplexing control in providing two independent supply voltages (3.0 and 3.6 V) using only one 1/spl mu/H off-chip inductor and a single control loop.
Abstract: An integrated single-inductor dual-output boost converter is presented. This converter adopts time-multiplexing control in providing two independent supply voltages (3.0 and 3.6 V) using only one 1-/spl mu/H off-chip inductor and a single control loop. This converter is analyzed and compared with existing counterparts in the aspects of integration, architecture, control scheme, and system stability. Implementation of the power stage, the controller, and the peripheral functional blocks is discussed. The design was fabricated with a standard 0.5-/spl mu/m CMOS n-well process. At an oscillator frequency of 1 MHz, the power conversion efficiency reaches 88.4% at a total output power of 350 mW. This topology can be extended to have multiple outputs and can be applied to buck, flyback, and other kinds of converters.

345 citations


Journal ArticleDOI
TL;DR: In this article, a wideband physical and scalable 2-spl Pi/ equivalent circuit model for on-chip spiral inductors is developed based on physical derivation and circuit theory, closed-form formulas are generated to calculate the RLC circuit elements directly from the inductor layout.
Abstract: A wide-band physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Based on physical derivation and circuit theory, closed-form formulas are generated to calculate the RLC circuit elements directly from the inductor layout. The 2-/spl Pi/ model accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. Using frequency-independent RLC elements, this new model is fully compatible with both ac and transient analysis. Verification with measurement data from a SiGe process demonstrates accurate performance prediction and excellent scalability for a wide range of inductor configurations.

341 citations


Journal ArticleDOI
TL;DR: In this article, a new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5 GHz CMOS voltage-controlled oscillator. But the technique is limited to a single oscillator and it is not suitable for a large number of oscillators.
Abstract: A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply.

312 citations


Journal ArticleDOI
TL;DR: The design and implementation of an ADC to meet the unique requirements of sensor networks is described and the ADC reported here consumes 31 pJ/8-bit sample at 1-V supply and 100 kS/s, with a standby power consumption of 70 pW, one of the lowest ever reported.
Abstract: A low-energy successive approximation analog-to-digital converter (ADC) targeted for use in distributed sensor networks is presented The individual nodes combine sensing, computation, communications, and power into a tiny volume Energy is extremely limited, forcing the nodes to operate with very low duty cycles This paper describes the design and implementation of an ADC to meet the unique requirements of sensor networks The ADC reported here consumes 31 pJ/8-bit sample at 1-V supply and 100 kS/s, with a standby power consumption of 70 pW This energy consumption is one of the lowest ever reported

305 citations


Journal ArticleDOI
TL;DR: In this article, a physically based mismatch model was used to obtain dramatic improvements in prediction of MOSFET mismatch for analog design, and the model was applied to current mirrors to show some nonobvious effects over bias, geometry, and multiple unit devices.
Abstract: Despite the significance of matched devices in analog circuit design, mismatch modeling for design application has been lacking. This paper addresses misconceptions about MOSFET mismatch for analog design. V/sub t/ mismatch does not follow a simplistic 1/(/spl radic/area) law, especially for wide/short and narrow/long devices, which are common geometries in analog circuits. Further, V/sub t/ and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in prediction of mismatch. This model is applied to MOSFET current mirrors to show some nonobvious effects over bias, geometry, and multiple-unit devices.

295 citations


Journal ArticleDOI
TL;DR: In this paper, a low-voltage low-power CMOS voltage reference independent of temperature is presented based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a sub-threshold MCFET, which exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm/spl deg/C.
Abstract: In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.

294 citations


Journal ArticleDOI
R. Pelliconi1, David Iezzi1, A. Baroni1, Marco Pasotti1, Pierluigi Rolandi1 
TL;DR: In this article, a power-efficient charge pump is proposed, which uses low-voltage transistors and a simple two-phase clocking scheme to obtain high current, high efficiency, and small area.
Abstract: A power-efficient charge pump is proposed. The use of low-voltage transistors and of a simple two-phase clocking scheme permits the use of higher operating frequencies compared to conventional solutions, thus obtaining high current, high efficiency, and small area. Measurements show good results for frequencies around 100 MHz. Two test patterns have been fabricated, one with three stages and one with five stages, in a 1.8-V 0.18-/spl mu/m triple-well standard CMOS digital process (six metals). High-voltage capacitors have been implemented using metal to metal parasitic capacitance.

Journal ArticleDOI
TL;DR: An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second- Order Intermodulation if the IF is not carefully chosen.
Abstract: An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters is proposed in this paper. The achievable second-order input intercept point (IIP2) has a fundamental limit due to nonlinearity and mismatches in the switching stage and improves with technology scaling. Second-order intermodulation products generated by the input transconductor or due to self-mixing usually contribute to determine the IIP2 even though they can, at least in principle, be eliminated. The parasitic capacitance loading the switching-stage common source plays a key role in the intermodulation mechanisms. Moreover, the paper shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second-order intermodulation if the IF is not carefully chosen. The test vehicle to validate the proposed analysis is a highly linear 0.18-/spl mu/m direct-conversion CMOS mixer, embedded in a fully integrated receiver, realized for Universal Mobile Telecommunications System applications.

Journal ArticleDOI
TL;DR: In this article, the treatment of injection-locked frequency dividers (ILFDs) and regenerative systems is described, and the utility of the model is demonstrated in the calculation of both the steady-state and dynamic properties of ILFD systems, and subsequent computation of the corresponding phase noise spectrum.
Abstract: Injection-locked frequency dividers (ILFDs) are versatile analog circuit blocks used, for example, within phase-locked loops (PLLs). An important attribute is substantially lower power consumption relative to their digital counterparts. The model described in this paper unifies the treatment of injection-locked and regenerative systems. It also provides useful design insights by clarifying the nature and role of the nonlinearity present in many mixer-based frequency conversion circuits. The utility of the model is demonstrated in the calculation of both the steady-state and dynamic properties of ILFD systems, and the subsequent computation of the corresponding phase noise spectrum. Illustrative circuit examples show close correspondence between theory and simulation. Finally, measurement results from a 5.4-GHz divide-by-2 ILFD fabricated in 0.24-/spl mu/m CMOS show close correspondence between experiment and theory.

Journal ArticleDOI
TL;DR: The proposed match-line (ML) sense scheme reduces power consumption by minimizing switching activity of search-lines and limiting voltage swing of MLs and operates at a minimum supply voltage of 1.2 V.
Abstract: A 256/spl times/144-bit TCAM is designed in 0.18-/spl mu/m CMOS. The proposed TCAM cell uses 4T static storage for increased density. The proposed match-line (ML) sense scheme reduces power consumption by minimizing switching activity of search-lines and limiting voltage swing of MLs. The scheme achieves a match-time of 3 ns and operates at a minimum supply voltage of 1.2 V.

Journal ArticleDOI
TL;DR: In this article, a two-stage self-biased cascode power amplifier in 0.18/spl mu/m CMOS process for Class-1 Bluetooth application is presented, which provides 23dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz.
Abstract: A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.

Journal ArticleDOI
TL;DR: In this article, a multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced, which uses the positive phase shift of left-halfplane (LHP) zeros caused by the feedforward path to cancel the negative phase shifting of poles to achieve a good phase margin.
Abstract: A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.

Journal ArticleDOI
Byung-Moo Min1, P. Kim1, F.W. Bowman, D.M. Boisvert, A.J. Aude 
TL;DR: The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique and helps to reduce power consumption in a 10-bit pipeline.
Abstract: A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18-/spl mu/m dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm/sup 2/.

Journal ArticleDOI
TL;DR: In this paper, a low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field effect transistor (FET).
Abstract: A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.

Journal ArticleDOI
TL;DR: This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-/spl mu/m CMOS standard cell technology.
Abstract: This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-/spl mu/m CMOS standard cell technology. This integrated circuit implements the Rijndael encryption algorithm, at any combination of block lengths (128, 192, or 25 bits) and key lengths (128, 192, or 256 bits). We present the chip architecture and discuss the design optimizations. We also present measurement results that were obtained from a set of 14 test samples of this chip.

Journal ArticleDOI
TL;DR: In this article, a simple analysis relates the small-signal specification of a varactor's capacitance to an oscillator's tuning curve and explains how the varactor converts AM noise on the oscillation into FM, which is phase noise.
Abstract: A simple analysis relates the small-signal specification of a varactor's capacitance to an oscillator's tuning curve. The notion of an effective capacitance across the amplitude of oscillation is introduced. The analysis also explains how the varactor converts AM noise on the oscillation into FM, which is phase noise. The analysis is experimentally validated.

Journal ArticleDOI
TL;DR: In this paper, an active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented, where a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier.
Abstract: An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.

Journal ArticleDOI
TL;DR: In this paper, a successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages, which is realized in a 0.18-/spl mu/m standard CMOS technology.
Abstract: A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-/spl mu/m standard CMOS technology. Neither low-V/sub T/ devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V/sub DD/ and ground V/sub SS/. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 /spl mu/W, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.

Journal ArticleDOI
TL;DR: In this paper, a general design methodology of low-voltage wideband voltage-controlled oscillator (VCO) suitable for wireless LAN (WLAN) application is described, and the applications of high-quality passives for the resonator are introduced: a single-loop horseshoe inductor with Q > 20 between 2 and 5 GHz for good phase noise performance; and accumulation MOS (AMOS) varactors with C/sub max/C/sub min/ ratio of 6 to provide wide-band tuning capability at lowvoltage supply.
Abstract: In this paper, a general design methodology of low-voltage wide-band voltage-controlled oscillator (VCO) suitable for wireless LAN (WLAN) application is described. The applications of high-quality passives for the resonator are introduced: 1) a single-loop horseshoe inductor with Q > 20 between 2 and 5 GHz for good phase noise performance; and 2) accumulation MOS (AMOS) varactors with C/sub max//C/sub min/ ratio of 6 to provide wide-band tuning capability at low-voltage supply. The adverse effect of AMOS varactors due to high sensitivity is examined. Amendment using bandswitching topology is suggested, and a phase noise improvement of 7 dB is measured to prove the concept. The measured VCO operates on a 1-V supply with a wide tuning range of 58.7% between 3.0 and 5.6 GHz when tuned between /spl plusmn/0.7 V. The phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz, with the nominal power dissipation between 2 and 3 mW across the whole tuning range. The best phase noise at 1-MHz offset is -124 dBc/Hz at the frequency of 3 GHz, a supply voltage of 1.4 V, and power dissipation of 8.4 mW. When the supply is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz. Using this design methodology, the feasibility of generating two local oscillator frequencies (2.4-GHz ISM and 5-GHz U-NII) for WLAN transceiver using a single VCO with only one monolithic inductor is demonstrated. The VCO is fabricated in a 0.13-/spl mu/m partially depleted silicon-on-insulator CMOS process.

Journal ArticleDOI
TL;DR: In this paper, a high-order curvature-compensated CMOS bandgap reference, which utilizes a temperaturedependent resistor ratio generated by a high resistive poly resistor and a diffusion resistor, is presented.
Abstract: A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.

Journal ArticleDOI
TL;DR: A match-line (ML) sensing scheme that allocates less power to match decisions involving a larger number of mismatched bits, which results in a significant CAM power reduction.
Abstract: In the conventional content-addressable memory (CAM), equal power is consumed to determine if a stored word is matched to a search word or mismatched, independent of the number of mismatched bits. This paper presents a match-line (ML) sensing scheme that allocates less power to match decisions involving a larger number of mismatched bits. Since the majority of CAM words are mismatched, this scheme results in a significant CAM power reduction. The proposed ML sensing scheme is implemented in a 256 /spl times/ 144-bit ternary CAM for a 0.13-/spl mu/m 1.2-V CMOS logic process. For a 2-ns search time on a 144-bit word, the proposed scheme saves 60% of the power consumed by the conventional sensing scheme.

Journal ArticleDOI
TL;DR: In this article, a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes was proposed, which involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents.
Abstract: In this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also uses a special on-chip sawtooth oscillator to monitor and measure currents down to a few femtoamperes. This way, subpicoampere currents are characterized without driving them off chip and requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is implemented that uses a 100-fF capacitor and a 3.5-fA bias current to achieve a cutoff frequency of 0.5 Hz. A technique for characterizing noise at these currents is also described and verified. Finally, transistor mismatch measurements are provided and discussed. Experimental measurements are shown throughout the paper, obtained from prototypes fabricated in the AMS 0.35-/spl mu/m three-metal two-poly standard CMOS process.

Journal ArticleDOI
TL;DR: In this paper, a low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated.
Abstract: A low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, the magnetic tunnel junction (MTJ) elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high-permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming. The 25-mm/sup 2/ 1-Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The 1-Mb MRAM circuit is fabricated in a 0.6-/spl mu/m CMOS process utilizing five layers of metal and two layers of poly.

Journal ArticleDOI
TL;DR: In this article, a low-power low-phase-noise 1.9 GHz RF oscillator is presented, which employs a single thin-film bulk acoustic wave resonator and was implemented in a standard 0.18/spl mu/m CMOS process.
Abstract: A low-power low-phase-noise 1.9-GHz RF oscillator is presented. The oscillator employs a single thin-film bulk acoustic wave resonator and was implemented in a standard 0.18-/spl mu/m CMOS process. This paper addresses design issues involved in codesigning micromachined resonators with CMOS circuitry to realize ultralow-power RF transceiver components. The oscillator achieves a phase-noise performance of -100 dBc/Hz at 10-kHz offset, -120 dBc/Hz at 100-kHz offset, and -140 dBc/Hz at 1-MHz offset. The startup time of the oscillator is less than 1 /spl mu/s. The oscillator core consumes 300 /spl mu/A from a 1-V supply.

Journal ArticleDOI
TL;DR: In this article, a voltage reference based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region has been proposed for CMOS low-dropout linear regulators and implemented in a standard 0.6-/spl mu/m CMOS technology.
Abstract: A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).

Journal ArticleDOI
TL;DR: In this paper, a 10-Gb/s phase-locked clock and data recovery circuit incorporating a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming is presented.
Abstract: A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-/spl mu/m CMOS technology in an area of 1.75/spl times/1.55 mm/sup 2/, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10/sup -9/ with a pseudorandom bit sequence of 2/sup 23/-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.