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Showing papers in "IEEE Journal of Solid-state Circuits in 2004"


Journal ArticleDOI
TL;DR: In this paper, an identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction, and the behavior of phase-locked oscillators under injection pulling is also formulated.
Abstract: Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators under injection pulling is also formulated.

1,159 citations


Journal ArticleDOI
TL;DR: In this article, a feed-forward noise-canceling technique is proposed to cancel the noise and distortion contributions of the matching device, which allows for designing wide-band impedance-matching amplifiers with noise figure (NF) well below 3 dB.
Abstract: Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-/spl mu/m standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3/spl times/0.25 mm/sup 2/.

749 citations


Journal ArticleDOI
TL;DR: An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter using a 0.18-/spl mu/m CMOS process achieves a power gain of 9.3 dB with an input match of -10 dB over the band.
Abstract: An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter is presented. Fabricated in a 0.18-/spl mu/m CMOS process, the IC prototype achieves a power gain of 9.3 dB with an input match of -10 dB over the band, a minimum noise figure of 4 dB, and an IIP3 of -6.7 dBm while consuming 9 mW.

714 citations


Journal ArticleDOI
TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
Abstract: We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

566 citations


Journal ArticleDOI
TL;DR: A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this article, where the measured absolute error between the sensed signal and the inductor current is less than 4%.
Abstract: A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.

513 citations


Journal ArticleDOI
TL;DR: In this paper, the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage was investigated for a latch-type voltage sense amplifier with a high-impedance differential input stage.
Abstract: A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.

450 citations


Journal ArticleDOI
TL;DR: In this article, a SiGe amplifier with on-chip matching network spanning 3-10 GHz was presented, achieving 21dB peak gain, 2.5dB noise figure, and -1dBm input IP3 at 5 GHz, with a 10-mA bias current.
Abstract: Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

335 citations


Journal ArticleDOI
Tae Wook Kim1, Bonkee Kim, Kwyro Lee1
TL;DR: In this article, a high-level linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported.
Abstract: Highly linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported. In MGTR circuitry, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/'' of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output for the amplifier and by the tuned load for the mixer. Experimental results designed using the above techniques show IIP/sub 3/ improvements at given power consumption by as much as 10 dB for CMOS low-noise amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and noise figure.

313 citations


Journal ArticleDOI
TL;DR: Series-resonant vibrating micromechanical resonator oscillators are demonstrated using a custom-designed single-stage zero-phase-shift sustaining amplifier together with planar-processed micromecanical resonators variants with quality factors Q in the thousands that differ mainly in their power-handling capacities.
Abstract: Series-resonant vibrating micromechanical resonator oscillators are demonstrated using a custom-designed single-stage zero-phase-shift sustaining amplifier together with planar-processed micromechanical resonator variants with quality factors Q in the thousands that differ mainly in their power-handling capacities. The resonator variants include two 40-/spl mu/m-long 10-MHz clamped-clamped-beam (CC-beam) resonators, one of them much wider than the other so as to allow larger power-handling capacity, and a 64-/spl mu/m-diameter 60-MHz disk resonator that maximizes both Q and power handling among the resonators tested. Tradeoffs between Q and power handling are seen to be most important in setting the close-to-carrier and far-from-carrier phase noise behavior of each oscillator, although such parameters as resonant frequency and motional resistance are also important. With a 10/spl times/ higher power handling capability than the wide-width CC-beam resonator, a comparable series motional resistance, and a 45/spl times/ higher Q of 48 000, the 60-MHz wine glass resonator reference oscillator exhibits a measured phase noise of -110 dBc/Hz at 1-kHz offset, and -132 dBc/Hz at far-from-carrier offsets. Dividing down to 10 MHz for fair comparison with a common conventional standard, this oscillator achieves a phase noise of -125 dBc/Hz at 1-kHz offset, and -147 dBc/Hz at far-from-carrier offsets.

309 citations


Journal ArticleDOI
TL;DR: In this article, a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining is described, which employs capacitance matching with optimal transistor sizing to minimize sensor noise floor.
Abstract: This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential difference amplifier (DDA). Low-duty-cycle periodic reset is used to establish robust dc bias at the sensing electrodes with low noise. This work shows that continuous-time voltage sensing can achieve lower noise than switched-capacitor charge integration for sensing ultra-small capacitance changes. A prototype accelerometer integrated with this circuit achieves 50-/spl mu/g//spl radic/Hz acceleration noise floor and 0.02-aF//spl radic/Hz capacitance noise floor while chopped at 1 MHz.

307 citations


Journal ArticleDOI
TL;DR: In this paper, the authors present design considerations along with measurement results pertinent to hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) drive circuits for active matrix organic light emitting diode (AMOLED) displays.
Abstract: This paper presents design considerations along with measurement results pertinent to hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) drive circuits for active matrix organic light emitting diode (AMOLED) displays. We describe both pixel architectures and TFT circuit topologies that are amenable for vertically integrated, high aperture ratio pixels. Here, the OLED layer is integrated directly above the TFT circuit layer, to provide an active pixel area that is at least 90% of the total pixel area with an aperture ratio that remains virtually independent of scaling. Both voltage-programmed and current-programmed drive circuits are considered. The latter provides compensation for shifts in device characteristics due to metastable shifts in the threshold voltage of the TFT. Various drive circuits on glass and plastic were fabricated and tested. Integration of on-panel gate drivers is also discussed where we present the architecture of an a-Si:H based gate de-multiplexer that is threshold voltage shift invariant. In addition, a programmable current mirror with good linearity and stability is presented. Programmable current sources are an essential requirement in the design of source driver output stages.

Journal ArticleDOI
TL;DR: An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators, which features wide locking ranges, a very low input capacitance, and highest frequency capability.
Abstract: An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The direct injection-locking scheme features wide locking ranges, a very low input capacitance, and highest frequency capability. The direct locking and the tradeoff between power consumption and tank quality factor is verified through three test circuits in 0.13-/spl mu/m standard CMOS, aiming at input frequency ranges of 50, 40, and 15 GHz. The 40- and 50-GHz dividers consume 3 mW with locking ranges of 80 MHz and 1.5 GHz. The 15-GHz divider consumes 23 mW and features a locking range of 2.8 GHz.

Journal ArticleDOI
TL;DR: In this paper, the design and implementation of fully integrated rectifiers in BiCMOS and standard CMOS technologies for rectifying an externally generated RF carrier signal in inductively powered wireless devices, such as biomedical implants, radio-frequency identification (RFID) tags, and smartcards to generate an on-chip dc supply.
Abstract: This paper describes the design and implementation of fully integrated rectifiers in BiCMOS and standard CMOS technologies for rectifying an externally generated RF carrier signal in inductively powered wireless devices, such as biomedical implants, radio-frequency identification (RFID) tags, and smartcards to generate an on-chip dc supply. Various full-wave rectifier topologies and low-power circuit design techniques are employed to decrease substrate leakage current and parasitic components, reduce the possibility of latch-up, and improve power transmission efficiency and high-frequency performance of the rectifier block. These circuits are used in wireless neural stimulating microsystems, fabricated in two processes: the University of Michigan's 3-/spl mu/m 1M/2P N-epi BiCMOS, and the AMI 1.5-/spl mu/m 2M/2P N-well standard CMOS. The rectifier areas are 0.12-0.48 mm/sup 2/ in the above processes and they are capable of delivering >25mW from a receiver coil to the implant circuitry. The performance of these integrated rectifiers has been tested and compared, using carrier signals in 0.1-10-MHz range.

Journal ArticleDOI
TL;DR: In this paper, the first 24 GHz CMOS front-end in a 0.18/spl mu/m process was reported, which consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz.
Abstract: This paper reports the first 24-GHz CMOS front-end in a 0.18-/spl mu/m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S/sub 11/ of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy.

Journal ArticleDOI
TL;DR: In this article, a transimpedance amplifier was realized in a 0.6/spl mu/m digital CMOS technology for Gigabit Ethernet applications, which exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as Si Bipolar or GaAs MESFET.
Abstract: A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.

Journal ArticleDOI
TL;DR: A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described.
Abstract: A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.

Journal ArticleDOI
TL;DR: In this paper, a third-order continuous-time /spl Sigma/spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 mm/sup 2/.
Abstract: This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.

Journal ArticleDOI
TL;DR: In this paper, a phase noise cancellation technique and a charge pump linearization technique are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL).
Abstract: A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.

Journal ArticleDOI
TL;DR: In this article, a regenerative divide topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances, achieving a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.
Abstract: An analysis of regenerative dividers predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.

Journal ArticleDOI
TL;DR: In this paper, a large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation.
Abstract: A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

Journal ArticleDOI
TL;DR: In this paper, a dual-mode digitally controlled buck converter IC for cellular phone applications is described, which employs internal power management to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology.
Abstract: This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm/sup 2/ in 0.25-/spl mu/m CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 /spl mu/A.

Journal ArticleDOI
TL;DR: In this article, the authors proposed a frequency divider that combines the conventional and the extended true-single-phase-clock logics for multigigahertz phase-locked loops.
Abstract: The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-/spl mu/m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.

Journal ArticleDOI
TL;DR: In this paper, a retrospective and a perspective of RF CMOS is presented, including its origins, the commercial impact, and how it will evolve in the future, as well as a discussion of the current state of the art.
Abstract: All-CMOS radio transceivers and systems-on-a-chip are rapidly making inroads into a wireless market that for years was dominated by bipolar and BiCMOS solutions. It is not a matter of replacing bipolar transistors in known circuit topologies with FETs; the wave of RF CMOS brings with it new architectures and unprecedented levels of integration. What are its origins? What is the commercial impact? How will RF CMOS evolve in the future? This paper offers a retrospective and a perspective.

Journal ArticleDOI
TL;DR: In this paper, a design principle for very low-voltage analog signal processing in CMOS technologies is presented, based on the use of quasi-floating gate (QFG) MOS transistors.
Abstract: A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very low-voltage applications.

Journal ArticleDOI
TL;DR: In this paper, the authors present an analysis of phase noise in multiphase LC oscillators, and measurement results for several CMOS quadrature-voltage-controlled-oscillators (QVCOs) working in the 2 GHz frequency range.
Abstract: This paper presents an analysis of phase noise in multiphase LC oscillators, and measurement results for several CMOS quadrature-voltage-controlled-oscillators (QVCOs) working in the 2-GHz frequency range. The phase noise data for a so-called BS-QVCO (-140 dBc/Hz or less at 3 MHz frequency offset from the carrier, for a power consumption of 20.8 mW and a figure-of-merit of 184 dBc/Hz) show that phase noise performances are close to the previously derived limits. A systematic cause of departure from ideal quadrature between QVCO signals is also analyzed and measured experimentally, and a compact LC-tank layout that removes this source of phase error is proposed. A TS-QVCO designed with this technique shows a phase-noise figure-of-merit improvement of 4 dB, compared to a previous implementation. The measured equivalent phase error for all QVCOs is between 0.6/spl deg/ and 1/spl deg/.

Journal ArticleDOI
TL;DR: In this paper, a low-pass filter component values are used to improve the bandwidth of a CMOS transimpedance amplifier, which achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance.
Abstract: A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known low-pass filter component values, is introduced. To demonstrate the feasibility of the method, a CMOS transimpedance amplifier (TIA) is implemented in a 0.18-/spl mu/m BiCMOS technology. It achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance. This corresponds to a bandwidth enhancement ratio of 2.4 over the amplifier without the additional passive networks. The transresistance gain is 54 dB/spl Omega/, while drawing 55 mA from a 2.5-V supply. The input sensitivity of the TIA is -18 dBm for a bit error rate of 10/sup -12/.

Journal ArticleDOI
TL;DR: In this paper, the design of three and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz was presented.
Abstract: This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.

Journal ArticleDOI
TL;DR: In this paper, a single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented, which is intended to minimize the power consumption in a lowvoltage environment.
Abstract: A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.

Journal Article
TL;DR: In this paper, the same pseudorandom data pattern is loaded onto both chips so that the receiving chip can check the accuracy of every bit communicated, and the test chip includes a Vernier measurement circuit that provides inter-chip position measurements with a resolution of 1.4 µm.
Abstract: This paper reports results from wireless chip-to-chip communication experiments. Sixteen bit words pass from one chip to another in parallel without detectable error at 1.35 billion data items per second for a total data rate of 21.6 Gigabits per second. The experiment transmits pseudo random patterns between chips built in a 350-nm CMOS technology. Chips touch face-to-face to communicate. The same pseudorandom data pattern is loaded onto both chips so that the receiving chip can check the accuracy of every bit communicated. Each communication channel consumes a static power of 3.6 mW, and a dynamic power of 3.9 pJ per bit communicated. The channels lie on 50-/spl mu/m centers. Because the capacitive communication works through covering oxide, ESD protection is unnecessary. Vernier position measuring circuits built into the chips indicate the relative position of transmitting and receiving arrays to assist mechanical alignment. The test chip includes a Vernier measurement circuit that provides inter-chip position measurements with a resolution of 1.4 /spl mu/m.

Journal ArticleDOI
TL;DR: This paper presents methods for efficient energy-performance optimization at the circuit and micro-architectural levels and demonstrates that the scope of energy-efficient optimization can be extended by the choice of circuit topology or the level of parallelism.
Abstract: This paper presents methods for efficient energy-performance optimization at the circuit and micro-architectural levels. The optimal balance between energy and performance is achieved when the sensitivity of energy to a change in performance is equal for all the design variables. The sensitivity-based optimizations minimize energy subject to a delay constraint. Energy savings of about 65% can be achieved without delay penalty with equalization of sensitivities to sizing, supply, and threshold voltage in a 64-bit adder, compared to the reference design sized for minimum delay. Circuit optimization is effective only in the region of about /spl plusmn/30% around the reference delay; outside of this region the optimization becomes too costly either in terms of energy or delay. Using optimal energy-delay tradeoffs from the circuit level and introducing more degrees of freedom, the optimization is hierarchically extended to higher abstraction layers. We focus on the micro-architectural optimization and demonstrate that the scope of energy-efficient optimization can be extended by the choice of circuit topology or the level of parallelism. In a 64-bit ALU example, parallelism of five provides a three-fold performance increase, while requiring the same energy as the reference design. Parallel or time-multiplexed solutions significantly affect the area of their respective designs, so the overall design cost is minimized when optimal energy-area tradeoff is achieved.