Showing papers in "IEEE Journal of Solid-state Circuits in 2012"

Platform Architecture for Solar, Thermal, and Vibration Energy Combining With MPPT and Single Inductor

Abstract: A platform architecture combining energy from solar, thermal, and vibration sources is presented. A dual-path architecture for energy harvesting is employed that has a peak efficiency improvement of 11%-13% over the traditional two-stage approach. The system implemented consists of a reconfigurable multi-input, multi-output switch matrix that combines energy from three distinct energy-harvesting sources-photovoltaic, thermoelectric, and piezoelectric. The system can handle input voltages from 20 mV to 5 V and is capable of extracting maximum power from individual harvesters all at the same time utilizing a single inductor. A proposed time-based power monitor is used for achieving maximum power point tracking for the photovoltaic harvester. This has a peak tracking efficiency of 96%. The peak efficiencies achieved with inductor sharing are 83%, 58%, and 79% for photovoltaic boost, thermoelectric boost, and piezoelectric buck-boost converters, respectively. The switch matrix and the control circuits are implemented on a 0.35-μm CMOS process.

A 3- $\mu\hbox{W}$ CMOS Glucose Sensor for Wireless Contact-Lens Tear Glucose Monitoring

Abstract: This paper presents a noninvasive wireless sensor platform for continuous health monitoring. The sensor system integrates a loop antenna, wireless sensor interface chip, and glucose sensor on a polymer substrate. The IC consists of power management, readout circuitry, wireless communication interface, LED driver, and energy storage capacitors in a 0.36-mm2 CMOS chip with no external components. The sensitivity of our glucose sensor is 0.18 μA·mm-2·mM-1. The system is wirelessly powered and achieves a measured glucose range of 0.05-1 mM with a sensitivity of 400 Hz/mM while consuming 3 μW from a regulated 1.2-V supply.

Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors

Abstract: This work introduces the use of compressed sensing (CS) algorithms for data compression in wireless sensors to address the energy and telemetry bandwidth constraints common to wireless sensor nodes. Circuit models of both analog and digital implementations of the CS system are presented that enable analysis of the power/performance costs associated with the design space for any potential CS application, including analog-to-information converters (AIC). Results of the analysis show that a digital implementation is significantly more energy-efficient for the wireless sensor space where signals require high gain and medium to high resolutions. The resulting circuit architecture is implemented in a 90 nm CMOS process. Measured power results correlate well with the circuit models, and the test system demonstrates continuous, on-the-fly data processing, resulting in more than an order of magnitude compression for electroencephalography (EEG) signals while consuming only 1.9 μW at 0.6 V for sub-20 kS/s sampling rates. The design and measurement of the proposed architecture is presented in the context of medical sensors, however the tools and insights are generally applicable to any sparse data acquisition.

A 1 k-Pixel Video Camera for 0.7–1.1 Terahertz Imaging Applications in 65-nm CMOS

Abstract: A 1 k-pixel camera chip for active terahertz video recording at room-temperature has been fully integrated in a 65-nm CMOS bulk process technology. The 32 × 32 pixel array consists of 1024 differential on-chip ring antennas coupled to NMOS direct detectors operated well-beyond their cutoff frequency based on the principle of distributed resistive self-mixing. It includes row and column select and integrate-and-dump circuitry capable of capturing terahertz videos up to 500 fps. The camera chip has been packaged together with a 41.7-dBi silicon lens (measured at 856 GHz) in a 5 × 5 × 3 cm3 camera module. It is designed for continuous-wave illumination (no lock-in technique required). In this video-mode the camera operates up to 500 fps. At 856 GHz it achieves a responsivity Rv of about 115 kV/W (incl. a 5-dB VGA gain) and a total noise equivalent power (NEPtotal) of about 12 nW integrated over its 500-kHz video bandwidth. At a 5-kHz chopping frequency (non-video mode) a single pixel can provide a maximum responsivity Rv of 140 kV/W (incl. a 5-dB VGA gain) and a minimum noise equivalent power ( NEP) of 100 pW/√Hz at 856 GHz. The wide-band antenna and pixel design achieves a 3-dB bandwidth of at least 790-960 GHz.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

Abstract: A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V

Abstract: Sensing systems such as biomedical implants, infrastructure monitoring systems, and military surveillance units are constrained to consume only picowatts to nanowatts in standby and active mode, respectively. This tight power budget places ultra-low power demands on all building blocks in the systems. This work proposes a voltage reference for use in such ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies. Prototype chips in 0.13 μm show a temperature coefficient of 16.9 ppm/°C (best) and line sensitivity of 0.033%/V, while consuming 2.22 pW in 1350 μm2. The lowest functional Vdd 0.5 V. The proposed design improves energy efficiency by 2 to 3 orders of magnitude while exhibiting better line sensitivity and temperature coefficient in less area, compared to other nanowatt voltage references. For process spread analysis, 49 dies are measured across two runs, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature. Digital trimming is demonstrated, and assisted one temperature point digital trimming, guided by initial samples with two temperature point trimming, enables TC <; 50 ppm/°C and ±0.35% output precision across all 25 dies. Ease of technology portability is demonstrated with silicon measurement results in 65 nm, 0.13 μm, and 0.18 μm CMOS technologies.

A 0.28 THz Power-Generation and Beam-Steering Array in CMOS Based on Distributed Active Radiators

Abstract: In this paper, we present a scalable transmitter architecture for power generation and beam-steering at THz frequencies using a centralized frequency reference, sub-harmonic signal distribution, and local phase control. The power generation and radiator core is based on a novel method called distributed active radiation, which enables high conversion efficiency from DC to radiated terahertz power above fmax of a technology. The design evolution of the distributed active radiator (DAR) follows from an inverse design approach, where metal surface currents at different harmonics are formulated in the silicon chip for the desired electromagnetic field profiles. Circuits and passives are then designed conjointly to synthesize and control the surface currents. The DAR consists of a self-oscillating active electromagnetic structure, comprising of two loops which sustain out-of-phase currents at the fundamental frequency and in-phase currents at the second harmonic. The fundamental signal, thus gets, spatially filtered, while the second harmonic is radiated selectively, thereby consolidating signal generation, frequency multiplication, radiation of desired harmonic and filtration of undesired harmonics simultaneously in a small silicon footprint. A two-dimensional 4×4 radiating array implemented in 45 nm SOI CMOS (without high-resistivity substrate) radiates with an EIRP of +9.4 dBm at 0.28 THz and beam-steers in 2D over 80° in both azimuth and elevation. The chip occupies 2.7 mm × 2.7 mm and dissipates 820 mW of DC power. To the best of the authors' knowledge, this is the first reported integrated beam-scanning array at THz frequencies in silicon.

A 0.013 ${\hbox {mm}}^{2}$ , 5 $\mu\hbox{W}$ , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

Abstract: We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 mm2 while consuming 5 μW and achieving 4.9 μVrms of input-referred noise in a 10 kHz bandwidth.

A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS

Abstract: On-chip DC-DC converters have the potential to offer fine-grain power management in modern chip-multiprocessors. This paper presents a fully integrated 3-level DC-DC converter, a hybrid of buck and switched-capacitor converters, implemented in 130 nm CMOS technology. The 3-level converter enables smaller inductors (1 nH) than a buck, while generating a wide range of output voltages compared to a 1/2 mode switched-capacitor converter. The test-chip prototype delivers up to 0.85 A load current while generating output voltages from 0.4 to 1.4 V from a 2.4 V input supply. It achieves 77% peak efficiency at power density of 0.1 W/mm2 and 63% efficiency at maximum power density of 0.3 W/mm2. The converter scales output voltage from 0.4 V to 1.4 V (or vice-versa) within 20 ns at a constant 450 mA load current. A shunt regulator reduces peak-to-peak voltage noise from 0.27 V to 0.19 V under pseudo-randomly fluctuating load currents. Using simulations across a wide range of design parameters, the paper compares conversion efficiencies of the 3-level, buck and switched-capacitor converters.

A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- $\mu$ m CMOS for Medical Implant Devices

Abstract: This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-μm CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.

HermesE: A 96-Channel Full Data Rate Direct Neural Interface in 0.13 $\mu$ m CMOS

Abstract: A power and area efficient sensor interface consumes 6.4 mW from 1.2 V while occupying 5 mm × 5 mm in 0.13 μm CMOS. The interface offers simultaneous access to 96 channels of broadband neural data acquired from cortical microelectrodes as part of a head-mounted wireless recording system, enabling basic neuroscience as well as neuroprosthetics research. Signals are conditioned with a front-end achieving 2.2 μVrms input-referred noise in a 10 kHz bandwidth before conversion at 31.25 kSa/s by 10-bit SAR ADCs with 60.3 dB SNDR and 42 fJ/conv-step. Switched-capacitor filtering provides a well-controlled frequency response and utilizes windowed integrator sampling to mitigate noise aliasing, enhancing noise/power efficiency.

A Combined Series-Parallel Hybrid Envelope Amplifier for Envelope Tracking Mobile Terminal RF Power Amplifier Applications

Abstract: An improved envelope amplifier architecture for envelope tracking RF power amplifiers is presented, consisting of two switching amplifiers and one linear amplifier. The first switching amplifier and the linear amplifier provide wideband and high-efficiency operation, while the second switching amplifier provides a reduced bandwidth variable supply to the linear amplifier to further reduce power loss. The first switching amplifier and the linear amplifier are fabricated together in a 150 nm CMOS process, while the second switching amplifier is external. Measurements show a maximum average efficiency of 82% for a 10 MHz LTE signal with a 6 dB PAPR at 29.7 dBm output power and an SFDR of 63 dBc for a single tone of 5 MHz driving an 8 Ω load.

An 8-Bit, 40-Instructions-Per-Second Organic Microprocessor on Plastic Foil

Abstract: Forty years after the first silicon microprocessors, we demonstrate an 8-bit microprocessor made from plastic electronic technology directly on flexible plastic foil. The operation speed is today limited to 40 instructions per second. The power consumption is as low as 100 μW. The ALU-foil operates at a supply voltage of 10 V and back-gate voltage of 50 V. The microprocessor can execute user-defined programs: we demonstrate the execution of the multiplication of two 4-bit numbers and the calculation of the moving average of a string of incoming 6-bit numbers. To execute such dedicated tasks on the microprocessor, we create small plastic circuits that generate the sequences of appropriate instructions. The near transparency, mechanical flexibility, and low power consumption of the processor are attractive features for integration on everyday objects, where it could be programmed as, amongst other items, a calculator, timer, or game controller.

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Abstract: This paper describes an all-digital PVT-variation tolerant true-random number generator (TRNG), fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die entropy generation in high-performance microprocessors. The TRNG harvests differential thermal-noise at the diffusion nodes of a pre-charged cross-coupled inverter pair to resolve out of metastability, generating one random bit/cycle. A self-calibrating 2-step tuning mechanism using coarse-grained configurable inverters and fine-grained programmable clock delay generators, along with an entropy-tracking feedback loop provide tolerance to 20% PVT variation-induced device mismatches, enabling lowest-reported energy-consumption of 2.9 pJ/bit with a dense layout occupying 4004 μm2, while achieving: (i) 2.4 Gbps random bit throughput, 7 mW total power consumption with 0.7 mW leakage power component, measured at 1.1 V, 50°C, (ii) random bitstreams that passes all NIST RNG tests with raw entropy/bit measured up to 0.9999999993, (iii) good distribution of 1's with 4-bit entropy of 3.97996 and high-entropy pattern probability of 0.066 (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 14 Mbps, 5.6 μW, measured at 280 mV, 50°C, (v) 12 fine-grained high-entropy settings for the TRNG to dither in during steady-state operation, (vi) <;3% error while using an analytical ergodic Markov chain model for predicting pattern probabilities and (vii) 200x higher throughput and 9x higher energy-efficiency than previously reported implementations. Design modifications for robust operation in 22 nm high-volume manufacturing in the presence of 3σ process variations demonstrate scalability of the all-digital design to future technologies.

A Time-Resolved, Low-Noise Single-Photon Image Sensor Fabricated in Deep-Submicron CMOS Technology

Abstract: We report on the design and characterization of a novel time-resolved image sensor fabricated in a 130 nm CMOS process. Each pixel within the 3232 pixel array contains a low-noise single-photon detector and a high-precision time-to-digital converter (TDC). The 10-bit TDC exhibits a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential non-linearity (DNL) and integral non-linearity (INL) were measured at ±0.4 and ±1.2 LSBs, respectively. The pixel array was fabricated with a pitch of 50 μm in both directions and with a total TDC area of less than 2000 μm2. The target application for this sensor is time-resolved imaging, in particular fluorescence lifetime imaging microscopy and 3D imaging. The characterization shows the suitability of the proposed sensor technology for these applications.

A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching

Abstract: In this paper we will present a low-phase-noise wide-tuning-range oscillator suitable for scaled CMOS processes. It switches between the two resonant modes of a high-order LC resonator that consists of two identical LC tanks coupled by capacitor and transformer. The mode switching method does not add lossy switches to the resonator and thus doubles frequency tuning range without degrading phase noise performance. Moreover, the coupled resonator leads to 3 dB lower phase noise than a single LC tank, which provides a way of achieving low phase noise in scaled CMOS process. Finally, the novel way of using inductive and capacitive coupling jointly decouples frequency separation and tank impedances of the two resonant modes, and makes it possible to achieve balanced performance. The proposed structure is verified by a prototype in a low power 65 nm CMOS process, which covers all cellular bands with a continuous tuning range of 2.5-5.6 GHz and meets all stringent phase noise specifications of cellular standards. It uses a 0.6 V power supply and achieves excellent phase noise figure-of-merit (FoM) of 192.5 dB at 3.7 GHz and >; 188 dB across the entire tuning range. This demonstrates the possibility of achieving low phase noise and wide tuning range at the same time in scaled CMOS processes.

A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process

Abstract: A fully-integrated, silicon photonic transceiver is demonstrated in a silicon-on-insulator process using photonic microring resonator modulators for low power consumption. The trade-offs between bandwidth and extinction ratio are discussed and motivate the use of transmit pre-emphasis for ring modulators to increase the interconnect data rate. The transmitter and receiver is demonstrated to data rates of 25 Gb/s with a BER of 10 ^-12. The total power consumption of the transceiver is 256 mW and demonstrates a link efficiency of 10.2 pJ/bit excluding laser power. At 25 Gb/s, the driver operates at 7.2 pJ/bit.

A Novel Wide-Temperature-Range, 3.9 ppm/ $^{\circ}$ C CMOS Bandgap Reference Circuit

Abstract: This paper presents an innovative CMOS Bandgap Reference Generator topology that leads to an improved curvature compensation method over a very wide temperature range. The proposed design was implemented in a standard 0.35 μm CMOS process. The compensation is performed by using only poly-silicon resistors. This is achieved by using a second Op-amp that generates a CTAT current, which is subsequently used to enhance the curvature compensation method. The performance of the circuit was verified experimentally. Measured results have shown temperature coefficients as low as 3.9 ppm/°C over a temperature range of 165°C ( -15°C to 150°C ) and temperature coefficients as low as 13.7 ppm/°C over an extended temperature range of 200°C (-50°C to 150°C ). In addition the circuit demonstrated very good line regulation performance for a broad range of supply voltages. The measured line regulation at room temperature is 0.039% V.

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Abstract: This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with VDD down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 μW power. Data is held down to 0.275 V with 2.29 μW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for VDD around/above 1.0 V.

Merged Two-Stage Power Converter With Soft Charging Switched-Capacitor Stage in 180 nm CMOS

Abstract: In this paper, we introduce a merged two-stage dc-dc power converter for low-voltage power delivery. By separating the transformation and regulation function of a dc-dc power converter into two stages, both large voltage transformation and high switching frequency can be achieved. We show how the switched-capacitor stage can operate under soft charging conditions by suitable control and integration (merging) of the two stages. This mode of operation enables improved efficiency and/or power density in the switched-capacitor stage. A 5-to-1 V, 0.8 W integrated dc-dc converter has been developed in 180 nm CMOS. The converter achieves a peak efficiency of 81%, with a regulation stage switching frequency of 10 MHz.

Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications

Abstract: Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or low-voltage power-on operation with the capability of power-off nonvolatile data storage. However, the two-macro approach suffers from slow store/restore speeds due to word-by-word serial transfer of data between the volatile and nonvolatile memories. Slow store/restore speeds require long power-on/off time and leave the device vulnerable to sudden power failure . This study proposes a resistive memory (memristor) based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/restore energy consumption, and a compact cell area. This resistive nonvolatile 8T2R (Rnv8T) cell includes two fast-write memristor (RRAM) devices vertical-stacked over the 8T, and a novel 2T memristor-switch, which provides both memristor control and SRAM write-assist functions. The write assist feature enables the Rnv8T cell to use read favored transistor sizing to prevent read/write failure at lower VDDs. We also fabricated the first macro-level memristor-based (or RRAM-based) nonvolatile SRAM. This 16 Kb Rnv8T macro achieved the lowest store energy and R/W VDDmin (0.45 V) of any nonvolatile SRAM or two-macro solution.

A Fully Autonomous Integrated Interface Circuit for Piezoelectric Harvesters

Abstract: This paper presents a fully autonomous, adaptive pulsed synchronous charge extractor (PSCE) circuit optimized for piezoelectric harvesters (PEHs) which have a wide output voltage range 1.3-20 V. The PSCE chip fabricated in a 0.35 μm CMOS process is supplied exclusively by the buffer capacitor where the harvested energy is stored in. Due to the low power consumption, the chip can handle a minimum PEH output power of 5.7 μW. The system performs a startup from an uncharged buffer capacitor and operates in the adaptive mode at storage buffer voltages from 1.4 V to 5 V. By reducing the series resistance losses, the implementation of an improved switching technique increases the extracted power by up to 20% compared to the formerly presented Synchronous Electric Charge Extraction (SECE) technique and enables the chip efficiency to reach values of up to 85%. Compared to a low-voltage-drop passive full-wave rectifier, the PSCE chip increases the extracted power to 123% when the PEH is driven at resonance and to 206% at off-resonance.

Widely Tunable 4th Order Switched G $_m$ -C Band-Pass Filter Based on N-Path Filters

Abstract: A widely tunable 4th order BPF based on the subtraction of two 2nd order 4-path passive-mixer filters with slightly different center frequencies is proposed. The center frequency of each 4-path filter is slightly shifted relative to its clock frequency (one upward and the other one downward) by agm-C technique. Capacitive splitting of the input signal is used to reduce the mutual loading of the two 4-path BPFs and increase their quality factors. The filter is tunable from 0.4 GHz to 1.2 GHz with approximately constant bandwidth of 21 MHz. The in-band 1-dB compression point of the filter is -4.4 dBm while the in-band IIP3 of the filter is +9 dBm and the out-of-band IIP3 is + 29 dBm (Δf=+50 MHz). The ultimate rejection of the filter is >; 55 dB and the NF of the filter is 10 dB. The static and dynamic current consumption of the filter are 2.8 mA from 2.5 V and 12 mA from 1.2 V, respectively (at 1 GHz). The LO leakage power to the input port is <; - 60 dBm. The filter has been fabricated in CMOS LP 65 nm technology and the active area is 0.127 mm2.

A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications

Abstract: This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.

An Energy-Efficient 15-Bit Capacitive-Sensor Interface Based on Period Modulation

Abstract: This paper presents an energy-efficient capacitive-sensor interface with a period-modulated output signal. This interface converts the sensor capacitance to a time interval, which can be easily digitized by a simple digital counter. It is based on a relaxation oscillator consisting of an integrator and a comparator. To enable the use of a current-efficient telescopic OTA in the integrator, negative feedback loops are applied to limit the integrator's output swing. To obtain an accurate ratiometric output signal, auto-calibration is applied. This eliminates errors due to comparator delay, thus enabling the use of a low-power comparator. Based on an analysis of the stability of the negative feedback loops, it is shown how the current consumption of the interface can be traded for its ability to handle parasitic capacitors. A prototype fabricated in 0.35 μm standard CMOS technology can handle parasitic capacitors up to five times larger than the sensor capacitance. Experimental results show that it achieves 15-bit resolution and 12-bit linearity within a measurement time of 7.6 ms for sensor capacitances up to 6.8 pF, while consuming only 64 μA from a 3.3 V power supply. Compared to prior work with similar performance, this represents a significant improvement in energy efficiency.

Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and ${\rm V}_{\rm TH}$ -Tuned Oscillator With Fixed Charge Programming

Abstract: This paper presents a 95 mV startup-voltage step-up DC-DC converter for energy harvesting applications. The capacitor pass-on scheme enables operation of the system from an input voltage of 95 mV without using additional off-chip components. To compensate for the die-to-die process variation, post-fabrication threshold voltage (VTH) trimming is applied to reduce the minimum operating voltage (VDDMIN) of the oscillator. Experimental results demonstrate the 34% VDDMIN reduction of the oscillator by post-fabrication VTH trimming. The proposed step-up converter achieves the lowest startup voltage in standard CMOS without using a mechanical switch or large transformer.

A 2.4-GHz, 27-dBm Asymmetric Multilevel Outphasing Power Amplifier in 65-nm CMOS

Abstract: We present a 2.4-GHz asymmetric multilevel outphasing (AMO) power amplifier (PA) with class-E branch amplifiers and discrete supply modulators integrated in a 65-nm CMOS process. AMO PAs achieve improved modulation bandwidth and efficiency over envelope tracking (ET) PAs by replacing the continuous supply modulator with a discrete supply modulator implemented with a fast digital switching network. Outphasing modulation is used to provide the required fine output envelope control. The AMO PA delivers 27.7-dBm peak output power with 45% system efficiency at 2.4 GHz. For a 20-MHz WLAN OFDM signal with 7.5-dB PAPR, the AMO PA achieves a drain efficiency of 31.9% and a system efficiency of 27.6% with an EVM of 2.7% rms.

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example

Abstract: This paper presents a design methodology for power and area minimization of flexible FFT processors. The methodology is based on the power-area tradeoff space obtained by adjusting algorithm, architecture, and circuit variables. Radix factorization is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism and delay line circuits. The flexibility is provided by reconfigurable processing units that support radix-2/4/8/16 factorizations. As a proof of concept, a 128- to 2048-point FFT processor for 3GPP-LTE standard has been implemented in a 65-nm CMOS process. The processor designed for minimum power-area product is integrated in 1.25 × 1.1 mm2 and dissipates 4.05 mW at 0.45 V for the 20 MHz LTE bandwidth. The energy dissipation ranging from 2.5 to 103.7 nJ/FFT for 128 to 2048 points makes it the lowest energy flexible FFT.

A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS

Abstract: This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only 160 μm × 70 μm.

Transformer-Based Uneven Doherty Power Amplifier in 90 nm CMOS for WLAN Applications

Abstract: This paper presents a fully integrated transformer-based Doherty power amplifier in a standard 90 nm CMOS process. A novel asymmetrical series combining transformer is used to achieve uneven Doherty operation. The transformer-based uneven Doherty architecture is analyzed to further improve the back-off efficiency without linearity degradation. The fabricated two-stage uneven Doherty PA achieves a maximum output power of 26.3 dBm at 2.4 GHz with a peak power added efficiency (PAE) of 33% at 2 V supply voltage. The PAE at 6 dB back-off is still as high as 25.1%. The PA is tested with 54 Mbps WLAN 802.11g signal and it meets the stringent EVM and spectral mask requirements at 19.3 dBm average output power with a PAE of 22.9% with no need of predistortion. An open loop digital predistortion is applied to further improve the linearity. The PA satisfies WLAN requirements at 20.2 dBm average output power with a PAE of 24.7% with predistortion.