Showing papers in "IEEE Journal of Solid-state Circuits in 2014"

A 240 × 180 130 dB 3 µs Latency Global Shutter Spatiotemporal Vision Sensor

Abstract: Event-based dynamic vision sensors (DVSs) asynchronously report log intensity changes. Their high dynamic range, sub-ms latency and sparse output make them useful in applications such as robotics and real-time tracking. However they discard absolute intensity information which is useful for object recognition and classification. This paper presents a dynamic and active pixel vision sensor (DAVIS) which addresses this deficiency by outputting asynchronous DVS events and synchronous global shutter frames concurrently. The active pixel sensor (APS) circuits and the DVS circuits within a pixel share a single photodiode. Measurements from a 240×180 sensor array of 18.5 μm 2 pixels fabricated in a 0.18 μm 6M1P CMOS image sensor (CIS) technology show a dynamic range of 130 dB with 11% contrast detection threshold, minimum 3 μs latency, and 3.5% contrast matching for the DVS pathway; and a 51 dB dynamic range with 0.5% FPN for the APS readout.

Co-Design of a CMOS Rectifier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters

Abstract: In this paper, a design method for the co-design and integration of a CMOS rectifier and small loop antenna is described. In order to improve the sensitivity, the antenna-rectifier interface is analyzed as it plays a crucial role in the co-design optimization. Subsequently, a 5-stage cross-connected differential rectifier with a 7-bit binary-weighted capacitor bank is designed and fabricated in standard 90 nm CMOS technology. The rectifier is brought at resonance with a high-Q loop antenna by means of a control loop that compensates for any variation at the antenna-rectifier interface and passively boosts the antenna voltage to enhance the sensitivity. A complementary MOS diode is proposed to improve the harvester's ability to store and hold energy over a long period of time during which there is insufficient power for rectification. The chip is ESD protected and integrated on a compact loop antenna. Measurements in an anechoic chamber at 868 MHz demonstrate a -27 dBm sensitivity for 1 V output across a capacitive load and 27 meter range for a 1.78 W RF source in an office corridor. The end-to-end power conversion efficiency equals 40% at -17 dBm.

A CMOS 210-GHz Fundamental Transceiver With OOK Modulation

Abstract: This paper presents a 210-GHz transceiver with OOK modulation in a 32-nm SOI CMOS process (fT/fmax= 250/320 GHz). The transmitter (TX) employs a 2 × 2 spatial combining array consisting of a double-stacked cross-coupled voltage controlled oscillator (VCO) at 210 GHz with an on-off-keying (OOK) modulator, a power amplifier (PA) driver, a novel balun-based differential power distribution network, four PAs, and an on-chip 2 × 2 dipole antenna array. The noncoherent receiver (RX) utilizes a direct detection architecture consisting of an on-chip antenna, a low-noise amplifier (LNA), and a power detector. The VCO generates measured -13.5-dBm output power, and the PA shows a measured 15-dB gain and 4.6-dBm Psat. The LNA exhibits a measured in-band gain of 18 dB and minimum in-band noise figure (NF) of 11 dB. The TX achieves an EIRP of 5.13 dBm at 10 dB back-off from saturated power. It achieves an estimated EIRP of 15.2 dBm when the PAs are fully driven. This is the first demonstration of a fundamental frequency CMOS transceiver at the 200-GHz frequency range.

A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro

Abstract: To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 × 2.10 mm2) with sub-cellular spatial resolution (pitch of 17.5 μm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 μVrms in the action-potential band (300 Hz-10 kHz) and 5.4 μVrms in the local-field-potential band (1 Hz-300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures.

A Fully Digital 8 $\,\times\,$ 16 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output

Abstract: An 8 × 16 pixel array based on CMOS small-area silicon photomultipliers (mini-SiPMs) detectors for PET applications is reported. Each pixel is 570 × 610 μm2 in size and contains four digital mini-SiPMs, for a total of 720 SPADs, resulting in a full chip fill-factor of 35.7%. For each gamma detection, the pixel provides the total detected energy and a timestamp, obtained through two 7-b counters and two 12-b 64-ps TDCs. An adder tree overlaid on top of the pixel array sums the sensor total counts at up to 100 Msamples/s, which are then used for detecting the asynchronous gamma events on-chip, while also being output in real-time. Characterization of gamma detection performance with an 3 × 3 × 5 mm3 LYSO scintillator at 20°C is reported, showing a 511-keV gamma energy resolution of 10.9% and a coincidence timing resolution of 399 ps.

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

Abstract: A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.

A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes

Abstract: We propose a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. A conventional approach to generate these currents is to drop a temperature sensitive voltage across a resistor. Since a large resistance is required to achieve nWs of power consumption with typical voltage levels (100 s of mV to 1 V), we introduce a new sensing element that outputs only 75 mV to save both power and area. The sensor is implemented in 0.18 μm CMOS and occupies 0.09 mm 2 while consuming 71 nW. After 2-point calibration, an inaccuracy of + 1.5°C/-1.4°C is achieved across 0 °C to 100 °C. With a conversion time of 30 ms, 0.3 °C (rms) resolution is achieved. The sensor does not require any external references and consumes 2.2 nJ per conversion. The sensor is integrated into a wireless sensor node to demonstrate its operation at a system level.

External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range

Abstract: This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable for system-on-chip (SoC) applications while maintaining the capability to reduce high-frequency supply noise. The paths of the power supply noise to the LDO output are analyzed, and a power supply noise cancellation circuit is developed. The PSR performance is improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. The effectiveness of the PSR enhancement technique is experimentally verified with an LDO that was fabricated in a 0.18 μm CMOS technology with a power supply of 1.8 V. The active core chip area is 0.14 mm2, and the entire proposed LDO consumes 80 μA of quiescent current during operation mode and 55 μA of quiescent current in standby mode. It has a drop-out voltage of 200 mV when delivering 50 mA to the load. The measured PSR is better than -56 dB up to 4 MHz when delivering a current of 50 mA. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively.

A Micro Inertial Energy Harvesting Platform With Self-Supplied Power Management Circuit for Autonomous Wireless Sensor Nodes

Abstract: A 025 cm 3 autonomous energy harvesting micro-platform is realized to efficiently scavenge, rectify and store ambient vibration energy with batteryless cold start-up and zero sleep-mode power consumption The fabricated compact system integrates a high-performance vacuum-packaged piezoelectric MEMS energy harvester with a power management IC and surface-mount components including an ultra-capacitor The power management circuit incorporates a rectification stage with ~30 mV voltage drop, a bias-Ωip stage with a novel control system for increased harvesting efficiency, a trickle charger for permanent storage of harvested energy, and a low power supply-independent bias circuitry The overall system weighs less than 06 grams, does not require a precharged battery, and has power consumption of 05 μW in active-mode and 10 pW in sleep-mode operation While excited with 1 g vibration, the platform is tested to charge an initially depleted 70 mF ultra-capacitor to 185 V in 50 minutes (at 155 Hz vibration), and a 20 mF ultra-capacitor to 135 V in 75 min (at 419 Hz) The end-to-end rectification efficiency from the harvester to the ultra-capacitor is measured as 58-86% The system can harvest from a minimum vibration level of 01 g

Compressed Sensing Analog Front-End for Bio-Sensor Applications

Abstract: In a conventional bio-sensor, key signal features are acquired using Nyquist-rate analog-to-digital conversion without exploiting the typical bio-signal characteristic of sparsity in some domain (e.g., time, frequency, etc.). Compressed sensing (CS) is a signal processing paradigm that exploits this sparsity for commensurate power savings by enabling alias-free sub-Nyquist acquisition. In a severely energy constrained sensor, CS also eliminates the need for digital signal processing (DSP). A fully-integrated low-power CS analog front-end (CS-AFE) is described for an electrocardiogram (ECG) sensor. Switched-capacitor circuits are used to achieve high accuracy and low power. Implemented in 0.13 μm CMOS in 2×3 mm2, the prototype comprises a 384-bit Fibonacci-Galois hybrid linear feedback shift register and 64 digitally-selectable CS channels with a 6-bit C-2C MDAC/integrator and a 10-bit C-2C SAR ADC in each. Clocked at 2 kHz, the total power dissipation is 28 nW and 1.8 μW for one and 64 active channels, respectively. CS-AFE enables compressive sampling of bio-signals that are sparse in an arbitrary domain.

A 0.18- $\mu$ m CMOS SoC for a 100-m-Range 10-Frame/s 200 $\,\times\,$ 96-Pixel Time-of-Flight Depth Sensor

Abstract: With the emerging need for high-resolution light detection and ranging (LIDAR) technologies in advanced driver assistance systems (ADAS), we introduce a system-on-a-chip (SoC) that performs time-correlated single-photon counting and complete digital signal processing for a time-of-flight (TOF) sensor. At the core of the 0.18-μm CMOS SoC, we utilize linear arrays of 16 TOF and 32 intensity-only macro-pixels based on single-photon avalanche diodes in an original look-ahead concept, thus acquiring active TOF and passive intensity images simultaneously. The SoC also comprises an array of circuits capable of generating precise triggers upon spatiotemporal correlation events, an array of 64 12-b time-to-digital converters, and 768 kb of SRAM memory. The SoC provides the system-level electronics with a serial and low-bit-rate digital interface for: 1) multi-echo distance; 2) distance reliability; 3) intensity; and 4) passive-only intensity, thus mitigating system-level complexity and cost. A proof-of-concept prototype that achieves depth imaging up to 100 m with a resolution of 202 × 96 pixels at 10 frames/s has been implemented. Quantitative evaluation of the TOF sensor under strong solar background illuminance, i.e., 70 klux, revealed a repeatability error of 14.2 cm throughout the distance range of 100 m, thus leading to a relative precision of 0.14%. Under the same conditions, the relative nonlinearity error was 0.11%. In order to show the suitability of our approach for ADAS-related applications, experimental results in which the depth sensor was operated in typical traffic situations have also been reported.

An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor Voltage Doubler

Abstract: This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm 2 solar cell in low light condition of 260 lux, converting 7 nW input power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 5 range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.

A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

Abstract: In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For pipelined operation, a novel time-register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse-train time-amplifier, a 9-bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/stage TDCs and a 3 b delay-line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/s while consuming 15.4 mW. Compared to other high-resolution state-of-the-art TDCs, the proposed pipelined TDC achieves the best figure-of-merit (FoM) without any calibration.

1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing

Abstract: This work demonstrates the first fabricated 1 Mb nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90 nm CMOS technology and mushroom phase-change memory (PCM) technology. The primary challenge for enabling reliable array operation with such aggressive cell is presented, namely, severely degraded sensing margin due to significantly lower ON/OFF ratio of resistive memories (~102 for PCM) than that of traditional MOSFETs (>105 ). To address this challenge, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding and 2) a clocked self-referenced sensing scheme (CSRSS). In addition, the two-bit encoding can also improve algorithmic mapping by effectively compressing TCAM entries. The 1 Mb chip demonstrates reliable low voltage search operation (VDDmin ~750 mV) and a match delay of 1.9 ns under nominal operating conditions.

A 100 fps, Time-Correlated Single-Photon-Counting-Based Fluorescence-Lifetime Imager in 130 nm CMOS

Abstract: A fully-integrated single-photon avalanche diode (SPAD) and time-to-digital converter (TDC) array for high-speed fluorescence lifetime imaging microscopy (FLIM) in standard 130 nm CMOS is presented. This imager is comprised of an array of 64-by-64 SPADs each with an independent TDC for performing time-correlated single-photon counting (TCSPC) at each pixel. The TDCs use a delay-locked-loop-based architecture and achieve a 62.5 ps resolution with up to a 64 ns range. A data-compression datapath is designed to transfer TDC data to off-chip buffers, which can support a data rate of up to 42 Gbps. These features, combined with a system implementation that leverages a x4 PCIe-cabled interface, allow for demonstrated FLIM imaging rates at up to 100 frames per second.

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

Abstract: This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- VT co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (μs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.

A 130.7- $\hbox{mm}^{2}$ 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

Abstract: A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit area overhead. Die efficiency is further improved by sharing wordlines and bitlines between adjacent blocks. As the number of sense amplifiers under the memory array is limited, a pipelined array control scheme is adopted to compensate the performance impact while utilizing the fast switching time of ReRAM cells. With the chip current consumption being dominated by the array leakage and sensitive to array bias and operating conditions, a charge pump stage control scheme is introduced to dynamically adapt to the operating conditions for optimal power consumption. Smart Read during sensing and leakage current compensation scheme during programming are applied to the large-block architecture and achieve a chip density that is several orders of magnitude higher than prior ReRAM developments.

A Low-Noise Design Technique for High-Speed CMOS Optical Receivers

Abstract: A careful comparison between alternative topologies to realize low-noise wideband TIAs is carried out in this work. In order to break the tradeoff between noise and bandwidth, the proposed front-end uses two stages, i.e. a low-noise narrowband transimpedance interface followed by an equalizer aimed at restoring the required bandwidth. The technique is especially effective for white noise components. The core first-stage amplifier exploits current reuse for minimum power consumption and is optimized for colored noise reduction. A net 4 $\times$ noise power reduction is achieved if compared with a design approach based on a traditional shunt-feedback TIA with the same bandwidth. A complete receiver, interfacing a commercial photodiode, and including the proposed two-stage front-end (TSFE), a limiting amplifier and a wideband output buffer has been realized in 65 nm CMOS. Optical communications tailored to 100GBASE-LR4 standard, which is specified for mid-to-long range transmissions at a channel rate of 25 Gb/s, are targeted. Realized prototypes show a sensitivity of $-$ 11.9 dBm at a BER of $10^{-12}$ with a PRBS31 input pattern and a transimpedance gain of 83 $\hbox{dB}\Omega$ , while tolerating an overall input capacitance of 160 fF. To the best of the authors' knowledge, this is the best sensitivity performance achieved by 25-Gb/s optical receivers in CMOS, comparable to state-of-the-art BiCMOS realizations.

A 90-nm CMOS 5-Mbps Crystal-Less RF-Powered Transceiver for Wireless Sensor Network Nodes

Abstract: This paper presents a 90-nm CMOS batteryless transceiver for RF-powered wireless sensor networks. The circuit is made up of a RF energy harvesting module that is implemented through a multi-stage rectifier, a power management unit, and a PLL-based RF front-end that enables TX carrier synthesis by exploiting the RF input signal as a reference frequency. This avoids the use of a local crystal oscillator, thus implementing a highly integrated low-cost wireless transceiver. An active narrowband transmission scheme is adopted with the aim of overcoming the reader self-jamming that limits the operating range of backscattering-based RF-powered devices. The circuit supports a 915-MHz FSK downlink and a 2.45-GHz OOK uplink, while achieving a data rate up to 5 Mbps. It operates with an RF input power as low as -17.1 dBm.

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

Abstract: Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multibit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although its spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in-band phase noise of -103 dBc/Hz and power consumption of 4.2 mW.

A 1024 $\,\times\,$ 8, 700-ps Time-Gated SPAD Line Sensor for Planetary Surface Exploration With Laser Raman Spectroscopy and LIBS

Abstract: A 1024 × 8 time-gated, single-photon avalanche diode line sensor is presented for time-resolved laser Raman spectroscopy and laser-induced breakdown spectroscopy. Two different chip geometries were implemented and characterized. A type-I sensor has a maximum photon detection efficiency of 0.3% and median dark count rate of 80 Hz at 3 V of excess bias. A type-II sensor offers a maximum photon detection efficiency of 19.3% and a median dark count rate of 5.7 kHz at 3 V of excess bias. Both chips have 250-ps temporal resolution and fast gating capability, with a minimum gate width of 1.8 ns for type I and 0.7 ns for type II. Raman spectra were successfully observed from natural minerals, such as calcite and willemite. With the use of subnanosecond gating, background fluorescence was significantly reduced.

Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback

Abstract: Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appealing aspects of both single-bit and multibit designs, without the disadvantage of either approaches. In this work, we give a method for stabilizing a CTDSM that uses an FIR feedback DAC. Further, we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorporated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, while consuming only 280 μW from a 1.8 V supply.

A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks

Abstract: This paper describes an 8-channel gel-free EEG/electrode-tissue impedance (ETI) acquisition system, consisting of nine active electrodes (AEs) and one back-end (BE) analog signal processor. The AEs amplify the weak EEG signals, while their low output impedance suppresses cable-motion artifacts and 50/60 Hz mains interference. A common-mode feed-forward (CMFF) scheme boosts the CMRR of the AE pairs by 25 dB. The BE post-processes and digitizes the analog outputs of the AEs, it also can configure them via a single-wire pulse width modulation (PWM) protocol. Together, the AEs and BE are capable of recording 8-channel EEG and ETI signals. With EEG recording enabled, ETIs of up to 60 kΩ can be measured, which increases to 550 kΩ when EEG recording is disabled. Each EEG channel has a 1.2 GΩ input impedance (at 20 Hz), 1.75 μVrms (0.5-100 Hz) input-referred noise, 84 dB CMRR and ±250 mV electrode offset rejection capability. The EEG acquisition system was implemented in a standard 0.18 μm CMOS process, and dissipates less than 700 μW from a 1.8 V supply.

A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology

Abstract: A fully integrated 60 GHz frequency synthesizer with an in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) is proposed. Through a particular symmetrical coupling network formed by diode-connected transistors, the in-phase coupling is realized in the IPIC-QVCO, which reduces both phase noise and phase error. A compact inductor-less divider chain is designed to reduce power consumption. A self-correcting low spur charge pump is employed to reduce reference spur. A standalone 60 GHz IPIC-QVCO and a fully integrated PLL are implemented in standard 65 nm low power CMOS technology. The measurement results show that the QVCO covers a frequency range from 57.88 to 68.33 GHz while consuming 11.4 mW power from a 1.2 V supply. The phase noise of the QVCO is -92 ~ -95 dBc/Hz at 1 MHz offset. The FOM and FOM T of the QVCO are -178.1 ~ -179.7 and -182.5 ~ -184.1 dBc/Hz respectively. The tuning range of the frequency synthesizer is from 57.9 to 68.3 GHz, and the power consumption is 24.6 mW. The phase noise of the frequency synthesizer is -89.8 ~ -91.5 dBc/Hz at 1 MHz offset across the frequency band.

A Self-Powered CMOS Reconfigurable Multi-Sensor SoC for Biomedical Applications

Abstract: A highly adaptive multi-sensor SoC comprising four integrated on-chip sensors and a smart wireless acquisition system is realized in standard CMOS process for the first time. To intelligently process different types (C, R, I, and V) of sensor signals, a linear (R-square is 0.999) and reconfigurable sensor readout is proposed based on switched-capacitor circuit technology. In addition, a dual-input energy harvesting interface with conversion efficiency of 73% is also integrated to pick up light energy and RF power, which potentiates long-term use without battery replacement. The entire SoC occupies die area of 11.25 mm 2 and consumes only 942.9 μW. Experimental results show that four physiological parameters (temperature, glucose and protein concentration, and pH value) can be simultaneously monitored using this chip. This system can be seen as a universal sensor platform. Different types of sensors can be easily integrated into it for convenient use, which dramatically reduces time consuming of building a new sensor system.

An Autonomous Piezoelectric Energy Harvesting IC Based on a Synchronous Multi-Shot Technique

Abstract: This paper presents a fully autonomous integrated circuit (IC) dedicated to piezoelectric harvesters. The novel Multi-Shot Synchronous Electric Charge Extraction (MS-SECE) performed by the IC optimizes the energy transfer from a highly charged piezoelectric harvester to a low voltage storage element. The system deals with piezoelectric powers in the 10 µW to 1 mW range and handles very high piezoelectric voltage values ( $>$ 100 V) thanks to the off-chip components around the IC. The IC has been fabricated in AMS 0.35 µm 3.3 V technology and its low power consumption (1 µW @ 5 Hz) is particularly suitable for low frequency harvesters. MS-SECE increases the extracted power compared to the Maximum Power Point Tracking (MPPT) technique but it also improves the efficiency by up to 25% compared to standard SECE. Furthermore, MS-SECE allows the use of small off-chip components: an efficiency of 61% has been reached with a 125 mm 3 coupled-inductor. Finally, the proposed power management circuit self-starts, works without any battery and its overall volume is expected to be less than 1 cm 3 .

0.56 V, –20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip With Harvesting-Efficiency Tracking Loop

Abstract: A battery-less, multi-node wireless body area network (WBAN) system-on-a-chip (SoC) is demonstrated. An efficiency tracking loop is proposed that adjusts the rectifier's threshold voltage to maximize the wireless harvesting operation, resulting in a minimum RF sensitivity better than –20 dBm at 904.5 MHz. Each SoC node is injection-locked and time-synchronized with the broadcasted RF basestation power (up to a sensitivity of –33 dBm) using an injection-locked frequency divider (ILFD). Hence, every sensor node is phase-locked with the basestation and all nodes can wirelessly transmit TDMA sensor data concurrently. Designed in a 65 nm-CMOS process, the fabricated sensor SoC contains the energy harvesting rectifier and bandgap, duty-cycled ADC, digital logic, as well as the multi-node wireless clock synchronization and MICS-band transmitter. For a broadcasted basestation power of 20 dBm (30 dBm), experimental measurements verify correct powering, sensor reading, and wireless data transfer for a distance of 3 m (9 m). The entire biomedical system application is verified by reception of room and abdominal temperature monitoring.

Design of Transformer-Based Boost Converter for High Internal Resistance Energy Harvesting Sources With 21 mV Self-Startup Voltage and 74% Power Efficiency

Abstract: Thin-film thermoelectric generators (TEG) or graphene-based microbial fuel cells (MFC) are emerging energy harvesting sources with promising power density and sustainability. Nevertheless, conventional transformer-based boost converters commonly used to achieve autonomous low voltage startup encounter low efficiency and potential startup problems with these novel power sources due to their high internal resistance. In this paper, an improved design of transformer-based boost converter addressing these issues is demonstrated with prototype chip fabricated using a standard 0.13 μm CMOS process. The self-start oscillation does not rely on the conventional LC resonant principle, but instead is dependent on the MOS transistor's active-over-leakage current ratio and the mutual coupling between the two identical transformer coils. Circuit design techniques to regulate output voltage and to track system's maximum power point (MPP) of this boost converter are presented. Measurement results confirmed that the proposed circuit works with either low threshold voltage or native MOS transistors. It needs minimum self-startup voltage of 21 mV (at 5.8 μW input power) and minimum startup power of 1.3 μW (at 35 mV input voltage) respectively. The maximum output power is 2 mW and peak power conversion efficiency is 74% at a regulated output voltage of 1 V.

A 0.53 THz Reconfigurable Source Module With Up to 1 mW Radiated Power for Diffuse Illumination in Terahertz Imaging Applications

Abstract: This paper presents a high-power 0.53 THz source module with programmable diversity to adjust the brightness and the direction of light to obtain the desired diffuse lighting conditions in THz imaging applications. The source module consists of a single SiGe BiCMOS chip which operates an array of 16 source-pixel incoherently. Each source pixel consists of a primary on-chip ring-antenna and two triple-push oscillators locked 180° out-of-phase. The module provides a total radiated power of up to 1 mW (0 dBm) with 62.5 μW (-12 dBm) per source pixel on average and an EIRP per pixel of 25 dBm. The circuit layout is scalable in size and output power. The chip consumes up to 2.5 W from a 2.4 V supply and 3.2 mW from a digital 1.2 V supply respectively. The module includes a secondary silicon lens, is programmable through a CPLD, and supplied from a USB port. The THz radiation can be recorded with a CMOS 1 k-pixel THz video camera and represent an all silicon solution for real-time active THz imaging.

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS

Abstract: Photonic interconnects are a promising technology to meet the bandwidth demands of next-generation high-performance computing systems. This paper presents silicon photonic transceiver circuits for a microring resonator-based optical interconnect architecture in a 1 V standard 65 nm CMOS technology. The transmitter circuits incorporate high-swing ( $2{\rm V}_{{\rm pp}}$ and $4{\rm V}_{{\rm pp}})$ drivers with nonlinear pre-emphasis and automatic bias-based tuning for resonance wavelength stabilization. An optical forwarded-clock adaptive inverter-based transimpedance amplifier (TIA) receiver trades off power for varying link budgets by employing an on-die eye monitor and scaling the TIA supply for the required sensitivity. At 5 Gb/s operation, the $4{\rm V}_{{\rm pp}}$ transmitter achieves 12.7 dB extinction ratio with 4.04 mW power consumption, excluding laser power, when driving wire-bonded modulators designed in a 130 nm SOI process, while a 0.28 nm tuning range is obtained at 6.8 $\mu$ W/GHz efficiency with the bias-based tuning scheme implemented with the $2{\rm V}_{{\rm pp}}$ transmitter. When tested with a wire-bonded 150 fF p-i-n photodetector, the receiver achieves ${-}$ 9 dBm sensitivity at a ${\rm BER}=10^{-9}$ and consumes 2.2 mW at 8 Gb/s. Testing with an on-die test structure emulating a low-capacitance waveguide photodetector yields 17 $\mu$ A $_{{\rm pp}}$ sensitivity at 10 Gb/s and more than 40% power reduction with higher input current levels.