Showing papers in "IEEE Journal of Solid-state Circuits in 2015"

A Minimally Invasive 64-Channel Wireless μECoG Implant

Abstract: Emerging applications in brain–machine interface systems require high-resolution, chronic multisite cortical recordings, which cannot be obtained with existing technologies due to high power consumption, high invasiveness, or inability to transmit data wirelessly. In this paper, we describe a microsystem based on electrocorticography (ECoG) that overcomes these difficulties, enabling chronic recording and wireless transmission of neural signals from the surface of the cerebral cortex. The device is comprised of a highly flexible, high-density, polymer-based 64-channel electrode array and a flexible antenna, bonded to 2.4 mm × 2.4 mm CMOS integrated circuit (IC) that performs 64-channel acquisition, wireless power and data transmission. The IC digitizes the signal from each electrode at 1 kS/s with 1.2 μV input referred noise, and transmits the serialized data using a 1 Mb/s backscattering modulator. A dual-mode power-receiving rectifier reduces data-dependent supply ripple, enabling the integration of small decoupling capacitors on chip and eliminating the need for external components. Design techniques in the wireless and baseband circuits result in over 16× reduction in die area with a simultaneous 3× improvement in power efficiency over the state of the art. The IC consumes 225 μW and can be powered by an external reader transmitting 12 mW at 300 MHz, which is over 3× lower than IEEE and FCC regulations.

A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices

Abstract: A 13.56 MHz wireless power transfer system with a 1X/2X reconfigurable resonant regulating (R $^3$ ) rectifier and wireless power control for biomedical implants is presented. Output voltage regulation is achieved through two mechanisms: 1) a local PWM loop at the secondary side controls the duty cycle of mode-switching of the rectifier between the 1X and 2X modes; and 2) a global control loop obtains the mode-switching information from the secondary side and send it back to the primary side through the wireless channel and adjusts the transmitter power of the primary coil to adapt to load and coupling variations. Two novel backscattering uplink techniques are proposed for fast and energy-efficient data feedback. The first is for general data transmission using Manchester code; and the second is for fast duty cycle feedback to cater for fast load-transient responses. Stability analysis of the entire system with the two control loops is also presented. The primary transmitter and the secondary R $^3$ rectifier are fabricated in 0.35 µm CMOS process with the digital control circuits implemented using FPGA. The measured maximum received power and receiver efficiency are 102 mW and 92.6%, respectively. For load transients, the overshoot and the undershoot are approximately 110 mV and the settling times are less than 130 µs.

A mm-Sized Implantable Medical Device (IMD) With Ultrasonic Power Transfer and a Hybrid Bi-Directional Data Link

Abstract: A first proof-of-concept mm-sized implantable device using ultrasonic power transfer and a hybrid bi-directional data communication link is presented. Ultrasonic power transfer enables miniaturization of the implant and operation deep inside the body, while still achieving safe and high power levels (100 $\mu$ W to a few mWs) required for most implant applications. The current implant prototype measures 4 mm $\times $ 7.8 mm and is comprised of a piezoelectric receiver, an IC designed in 65 nm CMOS process and an off-chip antenna. The IC can support a maximum DC load of 100 $\mu$ W for an incident acoustic intensity that is $\sim $ 5% of the FDA diagnostic limit. This demonstrates the feasibility of providing further higher available DC power, potentially opening up new implant applications. The proposed hybrid bi-directional data link consists of ultrasonic downlink and RF uplink. Falling edge of the ultrasound input is detected as downlink data. The implant transmits an ultra-wideband (UWB) pulse sequence as uplink data, demonstrating capability of implementing an energy-efficient M-ary PPM transmitter in the future.

A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC

Abstract: We introduce a 512 × 424 time-of-flight (TOF) depth image sensor designed in a TSMC 0.13 μm LP 1P5M CMOS process, suitable for use in Microsoft Kinect for XBOX ONE. The 10 μm × 10 μm pixel incorporates a TOF detector that operates using the quantum efficiency modulation (QEM) technique at high modulation frequencies of up to 130 MHz, achieves a modulation contrast of 67% at 50 MHz and a responsivity of 0.14 A/W at 860 nm. The TOF sensor includes a 2 GS/s 10 bit signal path, which is used for the high ADC bandwidth requirements of the system that requires many ADC conversions per frame. The chip also comprises a clock generation circuit featuring a programmable phase and frequency clock generator with 312.5-ps phase step resolution derived from a 1.6 GHz oscillator. An integrated shutter engine and a programmable digital micro-sequencer allows an extremely flexible multi-gain/multi-shutter and multi-frequency/multi-phase operation. All chip data is transferred using two 4-lane MIPI D-PHY interfaces with a total of 8 Gb/s input/output bandwidth. The reported experimental results demonstrate a wide depth range of operation (0.8–4.2 m), small accuracy error ( $ 1%), very low depth uncertainty ( $ 0.5% of actual distance), and very high dynamic range ( $>$ 64 dB).

A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP

Abstract: This paper presents a MUlti-SEnsor biomedical IC (MUSEIC). It features a high-performance, low-power analog front-end (AFE) and fully integrated DSP. The AFE has three biopotential readouts, one bio-impedance readout, and support for general-purpose analog sensors The biopotential readout channels can handle large differential electrode offsets ( ${\pm} $ 400 mV), achieve high input impedance ( ${>}$ 500 M $\Omega$ ), low noise ( ${ 620 nVrms in 150 Hz), and large CMRR ( ${>}$ 110 dB) without relying on trimming while consuming only 31 $\mu$ W/channel. In addition, fully integrated real-time motion artifact reduction, based on simultaneous electrode-tissue impedance measurement, with feedback to the analog domain is supported. The bio-impedance readout with pseudo-sine current generator achieves a resolution of 9.8 m $\Omega$ / $\surd$ Hz while consuming just 58 $\mu$ W/channel. The DSP has a general purpose ARM Cortex M0 processor and an HW accelerator optimized for energy-efficient execution of various biomedical signal processing algorithms achieving 10 $\times$ or more energy savings in vector multiply-accumulate executions.

Integrated Wideband Self-Interference Cancellation in the RF Domain for FDD and Full-Duplex Wireless

Abstract: A fully integrated technique for wideband cancellation of transmitter (TX) self-interference (SI) in the RF domain is proposed for multiband frequency-division duplexing (FDD) and full-duplex (FD) wireless applications. Integrated wideband SI cancellation (SIC) in the RF domain is accomplished through: 1) a bank of tunable, reconfigurable second-order high-Q RF bandpass filters in the canceller that emulate the antenna interface’s isolation (essentially frequency-domain equalization in the RF domain) and 2) a linear $N$ -path $G_m$ - $C$ filter implementation with embedded variable attenuation and phase shifting. A 0.8–1.4 GHz receiver (RX) with the proposed wideband SIC circuits is implemented in a 65 nm CMOS process. In measurement, $>20\;\text{MHz}\;20\;\text{dB}$ cancellation bandwidth (BW) is achieved across frequency-selective antenna interfaces: 1) a custom-designed LTE-like 0.780/0.895 GHz duplexer with TX/RX isolation peak magnitude of 30 dB, peak group delay of 11 ns, and 7 dB magnitude variation across the TX band for FDD and 2) a 1.4 GHz antenna pair for FD wireless with TX/RX isolation peak magnitude of 32 dB, peak group delay of 9 ns, and 3 dB magnitude variation over 1.36–1.38 GHz. For FDD, SIC enhances the effective out-of-band (OOB) IIP3 and IIP2 to $+\text{25}\text{-}27\;\text{dBm}$ and $+90\;\text{dBm}$ , respectively (enhancements of 8–10 and 29 dB, respectively). For FD, SIC eliminates RX gain compression for as high as $-8\;\text{dBm}$ of peak in-band (IB) SI, and enhances effective IB IIP3 and IIP2 by 22 and 58 dB.

An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring

Abstract: A syringe-implantable electrocardiography (ECG) monitoring system is proposed. The noise optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current consumption while a minimum energy computation approach in the digital back-end reduces digital energy consumption by 40%. The proposed SoC is fabricated in 65 nm CMOS and consumes 64 nW while successfully detecting atrial fibrillation arrhythmia and storing the irregular waveform in memory in experiments using an ECG simulator, a live sheep, and an isolated sheep heart.

A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS

Abstract: In this paper, a 240 GHz 16 Gbps QPSK transmitter is demonstrated in 65 nm bulk CMOS process The transmitter chain employs an 80 GHz local oscillator and a modulator to generate the data that is amplified by a class-E switching power amplifier The amplified signal then drives the 240 GHz tripler to generate the required modulated data By using on-chip slotted loop antennas, the transmitter achieves an EIRP of 1 dBm A maximum data rate of 16 Gbps is achieved with a transmitter efficiency of 14 pJ/bit

A 16-Channel Patient-Specific Seizure Onset and Termination Detection SoC With Impedance-Adaptive Transcranial Electrical Stimulator

Abstract: A 16-channel noninvasive closed-loop beginning- and end-of-seizure detection SoC is presented. The dual-channel charge recycled (DCCR) analog front end (AFE) achieves chopping and time-multiplexing an amplifier between two channels simultaneously which exploits fast-settling DC servo-loop with current consumption and NEF of $0.9\;\upmu\text{A}$ /channel and 3.29/channel, respectively. The dual-detector architecture ( $\text{D}^2 \text{A}$ ) classification processor utilizes two linear support-vector machine (LSVM) classifiers based on digital hysteresis to enhance both the sensitivity and the specificity simultaneously. The pulsating voltage transcranial electrical stimulator (PVTES) automatically configures the number of pulses to control the amount of charge delivered based on skin-electrode impedance variation in efforts to suppress the seizure activity, while burning only $2.45\;\upmu\text{W}$ . The $25\;\text{mm}^2$ SoC implemented in $0.18\;\upmu\text{m}$ CMOS consumes $2.73\;\upmu\text{J}$ /classification for 16 channels with an average sensitivity, specificity, and latency of 95.7%, 98%, and 1 s, respectively.

A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC

Abstract: This paper presents a 13 bit 50 MS/s fully differential ring amplifier based SAR-assisted pipeline ADC, implemented in 65 nm CMOS. We introduce a new fully differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of high gain, fast slew based charging and an almost rail-to-rail output swing. We implement a switched-capacitor (SC) inter-stage residue amplifier that uses this new fully differential ring amplifier to give accurate amplification without calibration. In addition, a new floated detect-and-skip (FDAS) capacitive DAC (CDAC) switching method reduces the switching energy and improves linearity of first-stage CDAC. With these techniques, the prototype ADC achieves measured SNDR, SNR, and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, with a Nyquist frequency input. The prototype achieves 13 bit linearity without calibration and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion $\cdot$ step and 174.9 dB, respectively.

A 10 mV-Input Boost Converter With Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting With 220 mV Cold-Start and $-$ 14.5 dBm, 915 MHz RF Kick-Start

Abstract: A boost converter for thermoelectric energy harvesting in 130 nm CMOS achieves energy harvesting from a 10 mV input, which allows wearable body sensors to continue operation with low thermal gradients. The design uses a peak inductor current control scheme and duty cycled, offset compensated comparators to maintain high efficiency across a broad range of input and output voltages. The measured efficiency ranges from 53% at ${\rm V}_{\rm I}=20\ {\hbox{mV}}$ to a peak efficiency of 83% at ${\rm V}_{\rm I}=300\ {\hbox{mV}}$ . A cold-start circuit starts the operation of the boost converter from 220 mV, and an RF kick-start circuits starts it from $-$ 14.5 dBm at 915 MHz RF power.

A 240 GHz Fully Integrated Wideband QPSK Receiver in 65 nm CMOS

Abstract: Operation at millimeter-wave/sub-terahertz frequencies allows one to realize very high data-rate transceivers for wireless chip-to-chip communication In this paper, a 240 GHz 16 Gbps QPSK receiver is demonstrated in 65 nm CMOS technology The receiver employs a direct-conversion mixer-first architecture with an integrated slotted loop antenna A 240 GHz LO chain drives the passive mixers to down-convert the modulated data to baseband The baseband signal is then amplified using high gain, wide bandwidth amplifiers The receiver has a noise figure of 15 dB with a conversion gain of 25 dB calculated from measurement data The receiver achieves a data rate of 10 Gbps (with ${\rm BER} ) and a maximum data rate of 16 Gbps (with BER of $10^{-4}$ ) with a receiver efficiency of 16 pJ/bit

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

Abstract: This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.

A SiGe Terahertz Heterodyne Imaging Transmitter With 3.3 mW Radiated Power and Fully-Integrated Phase-Locked Loop

Abstract: A high-power 320 GHz transmitter using 130 nm SiGe BiCMOS technology ( $f_{T}/f_{\max} =$ 220/280 GHz) is reported. This transmitter consists of a 4 × 4 array of radiators based on coupled harmonic oscillators. By incorporating a signal filter structure called return-path gap coupler into a differential self-feeding oscillator, the proposed 320 GHz radiator simultaneously maximizes the fundamental oscillation power, harmonic generation, as well as on-chip radiation. To facilitate the TX-RX synchronization of a future terahertz (THz) heterodyne imaging chipset, a fully-integrated phase-locked loop (PLL) is also implemented in the transmitter. Such on-chip phase-locking capability is the first demonstration for all THz radiators in silicon. In the far-field measurement, the total radiated power and EIRP of the chip is 3.3 mW and 22.5 dBm, respectively. The transmitter consumes 610 mW DC power, which leads to a DC-to-THz radiation efficiency of 0.54%. To the authors' best knowledge, this work presents the highest radiated power and DC-to-THz radiation efficiency in silicon-based THz radiating sources.

340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

Abstract: This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22 nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption and decryption on mobile SOCs. Compared to conventional 128 bit AES implementations, this design uses a single 8 bit Sbox circuit along with ShiftRows byte-order data processing to compute all AES rounds in native ${\rm GF}(2^{4})^{2}$ composite-field. This approach along with a serial-accumulating MixColumns circuit, area-optimized encrypt and decrypt Galois-field polynomials and integrated on-the-fly key generation circuit results in a compact encrypt/decrypt layout occupying 2200/2736 $\mu$ m $^{2}$ and lowest-reported gate count of 1947/2090 respectively, while achieving: (i) maximum operating frequency of 1.133 GHz and total power consumption of 13 mW with leakage component of 500 $\mu$ W, measured at 0.9 V, 25 $^{\circ}$ C, (ii) nominal AES-128 encrypt/decrypt throughput of 432/671 Mbps respectively, with peak energy-efficiency of 289 Gbps/W measured at near-threshold operation of 430 mV (11 $\times$ higher than previously reported implementations), (iii) encrypt/decrypt latencies of 336/216 cycles and total energy consumption of 3.9/2.5 nJ respectively, (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 45 Mbps, 170 $\mu$ W, measured at 340 mV, 25 $^{\circ}$ C and (v) first-reported Galois-field polynomial-based micro-architectural co-optimization, resulting in distinct area-optimized encrypt and decrypt polynomials with up to 9% area reduction at iso-performance.

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Abstract: A digital fractional-N PLL that employs a high resolution TDC and a truly $\Delta \Sigma$ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out $\Delta \Sigma$ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than ${-}$ 106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fs $ _{{\rm rms}}$ integrated jitter. This translates to a FoM $ _{{\rm J}}$ of ${-}$ 240.5 dB, which is the best among the reported fractional-N PLLs.

Compact cascadable gm-C all-pass true time delay cell with reduced delay variation over frequency

Abstract: At low-GHz frequencies, analog time-delay cells realized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be approximated by all-pass filters exploiting transconductors and capacitors (g m -C filters). This paper presents an easily cascadable compact g m -C all-pass filter cell for 1-2.5 GHz. Compared to previous g m -RC and g m -C filter cells, it achieves at least 5x larger frequency range for the same relative delay variation, while keeping gain variation within 1 dB. This paper derives design equations for the transfer function and several non-idealities. Circuit techniques to improve phase linearity and reduce delay variation over frequency, are also proposed. A 160 nm CMOS chip with maximum delay of 550 ps is demonstrated with monotonous delay steps of 13 ps (41 steps) and an RMS delay variation error of less than 10 ps over more than an octave in frequency (1-2.5 GHz). The delay per area is at least 50x more than for earlier chips. The all-pass cells are used to realize a four element timed-array receiver IC. Measurement results of the beam pattern demonstrate the wideband operation capability of the g m -RC time delay cell and timed-array IC-architecture.

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

Abstract: This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and demultiplex the data NRZ TX includes a tree-structure MUX with built-in PLL and phase aligner NRZ RX adopts linear PD with special vernier technique to handle the 56 Gb/s input data All chips have been verified in silicon with reasonable performance, providing prospective design examples for next-generation 400 GbE

An 86% Efficiency 12 µW Self-Sustaining PV Energy Harvesting System With Hysteresis Regulation and Time-Domain MPPT for IOT Smart Nodes

Abstract: This paper presents a fully-integrated µW-level photovoltaic (PV) self-sustaining energy harvesting system proposed for smart nodes of Internet of Things (IOT) networks. A hysteresis regulation is designed to provide a constant 3.3 V output voltage for a host of applications, including powering sensors, signal processors, and wireless transmitters. Due to the stringent power budget in IOT scenarios, the power consumption of the harvesting system is optimized by multiple system and circuit level techniques. Firstly, the hill-climbing MPPT mechanism reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Secondly, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations. Thirdly, to execute the impedance tuning of MPPT, the capacitor value modulation (CVM) scheme is proposed instead of the conventional frequency modulation scheme, avoiding quiescent power consumption. Utilizing a commercial PV cell of 2.5 cm 2 , the proposed system provides 0–21 µW output power to the IOT smart nodes. Measured results showed that the PV harvesting system achieved both ultra-low power operation capability at 12 µW and a peak self-sustaining efficiency of 86%.

A 10 mW Bluetooth Low-Energy Transceiver With On-Chip Matching

Abstract: A mass-produced Bluetooth Low-Energy transceiver is presented in classic double frequency VCO architecture fabricated in TSMC 55 nm CMOS. The radio part occupies 2.9 mm $^{2}$ while the complete SoC occupies 5.9 mm $^{2}$ . The transceiver consumes 11 mW when receiving at $-$ 94 dBm and 10 mW when transmitting at 0 dBm. This is roughly a factor 2 lower than benchmark mass-produced designs. The power consumption is higher than recently published experimental sliding-IF designs, but it does not suffer from their inherent susceptibility to blocking and pulling. Easy application is enabled by a fully integrated single-ended 50 $\Omega $ RFIO and combined Buck- and Boost-mode DC-DC converter.

Haswell: A Family of IA 22 nm Processors

Abstract: We describe the 4th Generation Intel® Core™ processor family (codenamed “Haswell”) implemented on Intel® 22 nm technology and intended to support form factors from desktops to fan-less Ultrabooks™. Performance enhancements include a 102 GB/sec L4 eDRAM cache, hardware support for transactional synchronization, and new FMA instructions that double FP operations per clock. Power improvements include Fully-Integrated Voltage Regulators ( ~ 50% battery life extension), new low-power states (95% standby power savings), optimized MCP I/O system (1.0-1.22 pJ/b), and improved DDR I/O circuits (40% active and 100x idle power savings). Other improvements include full-platform optimization via integrated display I/O interfaces.

A Fully-Implantable Cochlear Implant SoC with Piezoelectric Middle-Ear Sensor and Arbitrary Waveform Neural Stimulation.

Abstract: A system-on-chip for an invisible, fully-implantable cochlear implant is presented. Implantable acoustic sensing is achieved by interfacing the SoC to a piezoelectric sensor that detects the sound-induced motion of the middle ear. Measurements from human cadaveric ears demonstrate that the sensor can detect sounds between 40 and 90 dB SPL over the speech bandwidth. A highly-reconfigurable digital sound processor enables system power scalability by reconfiguring the number of channels, and provides programmable features to enable a patient-specific fit. A mixed-signal arbitrary waveform neural stimulator enables energy-optimal stimulation pulses to be delivered to the auditory nerve. The energy-optimal waveform is validated with in-vivo measurements from four human subjects which show a 15% to 35% energy saving over the conventional rectangular waveform. Prototyped in a 0.18 μm high-voltage CMOS technology, the SoC in 8-channel mode consumes 572 μW of power including stimulation. The SoC integrates implantable acoustic sensing, sound processing, and neural stimulation on one chip to minimize the implant size, and proof-of-concept is demonstrated with measurements from a human cadaver ear.

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector

Abstract: A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-leakage digital process. A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this work to attain high conversion throughput and power savings at the same time using a simple, low-gain ( $\sim$ 30 dB) residue amplifier. The overall architecture and the digital calibration also enable the downsizing of the first SAR stage to that of the kT/C limit, yielding a wideband input network delivering an over 80 dB spurious-free dynamic range (SFDR) while digitizing a 300 MHz input at 160 MS/s. The core ADC consumes 4.96 mW and occupies an area of 0.042 mm $^{2}$ ; the calibration circuits dissipate 0.1 mW (estimated). An 86.9 dB SFDR and a 66.7 dB signal-to-noise plus distortion ratio (SNDR) were measured with a 2 V $_{\rm pp}$ , 5 MHz sine-wave input at full speed. The ADC achieves a Walden figure-of-merit (FoM) of 20.7 fJ/conversion-step with a Nyquist input.

A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter

Abstract: This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and techniques for minimizing these limitations are presented. For example, background calibration guarantees appropriate DTC gain, reducing spurs. Operating at 10 GHz the system achieves −38 dBc of integrated phase noise (280 fs RMS jitter) when a worst case fractional spur of −43 dBc is present. In-band phase noise is at the level of −104 dBc/Hz. The class-B VCO can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9 V and 1.8 V supplies.

A Wideband Highly Integrated and Widely Tunable Transceiver for In-Band Full-Duplex Communication

Abstract: A fully integrated wideband active duplexing transceiver with baseband noise-cancelling duplexing LNAs is presented. The circuit allows in-band full duplex operation with concurrent reception and transmission in the same band or closely-spaced channels. A passive mixer-first architecture is applied here, sharing a single passive mixer to perform simultaneous up-conversion and down-conversion. The bi-directional transparency of the passive mixer allows the duplexing function to be implemented at baseband instead of RF front end. Under the same condition as required for noise cancellation, the baseband duplexing LNAs buffer the transmitter input signals to the mixer while canceling those signals in receive path. Measurements from the transceiver implemented in 65 nm CMOS show a frequency tuning range of 0.1–1.5 GHz with ${\rm S}_{11} 20 dB, NF as low as 5.5 dB and transmitted power up to ${-}$ 7.1 dBm. A 30 dB linear isolation between receive and transmit is generally maintained across both LO frequency and in-band transmit/receive frequency separation. Significant suppression of transmit-induced noise and nonlinear intermodulation between received and transmitted signals are also achieved.

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

Abstract: A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10 -9 . The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm $^{2}$ per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A High-Power and Scalable 2-D Phased Array for Terahertz CMOS Integrated Systems

Abstract: This work introduces a 2-D phased array architecture that is suitable for high power radiation at mm-Wave and Terahertz frequencies. We address the challenge of signal generation above the cut-off frequency of transistors by presenting a radiation method based on the collective performance of a large number of synchronized sources. As theory shows, both frequency locking/tuning and beam steering can be independently achieved by manipulating the local coupling between the nearest neighbors. This control method results in a dynamical network that is insensitive to array dimensions and is scalable to the point that can achieve a level of output power and spectral purity beyond the reach of conventional sources. To demonstrate the concept, we implement a 4 $\times$ 4 version of this phased array at 340 GHz using a 65 nm bulk CMOS process. The paper presents the design and implementation of the oscillators, couplings and the integrated antennas. The measured results at 338 GHz reveal a peak equivalent isotropically radiated power (EIRP) of +17.1 dBm and a phase noise of -93 dBc/Hz at the 1 MHz offset frequency. This chip presents the first fully integrated terahertz phased array on silicon. Furthermore, the output power is higher than any lens-less silicon-based source above 200 GHz and the phase noise is lower than all silicon radiating sources above 100 GHz.

3D Ultrasonic Rangefinder on a Chip

Abstract: An ultrasonic 3D rangefinder uses an array of AlN MEMS transducers and custom readout electronics to localize targets over a $\pm 45^{\circ}$ field of view up to 1 m away. The rms position error at 0.5 m range is 0.4 mm, 0.2 $^{\circ}$ , and 0.8 $^{\circ}$ for the range, x-angle, and y-angle axes, respectively. The 0.18 $\mu{\rm m}$ CMOS ASIC comprises 10 independent channels with separate high voltage transmitters, readout amplifiers, and switched-capacitor bandpass $\Sigma\Delta$ ADCs with built-in continuous time anti-alias filtering. For a 1 m maximum range, power dissipation is 400 $\mu{\rm W}$ at 30 fps. For a 0.3 m maximum range, the power dissipation scales to 5 $\mu{\rm W/ch}$ at 10 fps.

A 1 × 400 Backside-Illuminated SPAD Sensor With 49.7 ps Resolution, 30 pJ/Sample TDCs Fabricated in 3D CMOS Technology for Near-Infrared Optical Tomography

Abstract: A 1 × 400 array of backside-illuminated SPADs fabricated in 130 nm 3D IC CMOS technology is presented Sensing is performed in the top tier substrate and time-to-digital conversion in the bottom tier Clusters of eight pixels are connected to a winner-take-all circuit with collision detection capabilities to realise an efficient sharing of the time-to-digital converter (TDC) The sensor's 100 TDCs are based on a dual-frequency architecture enabling 30 pJ per conversion at a rate of 133 ms/s per TDC The resolution (1 LSB) of the TDCs is 497 ps with a standard deviation of 08 ps across the entire array; the mean DNL is ±044 LSB and the mean INL is ±047 The chip was designed for use in near-infrared optical tomography (NIROT) systems for brain imaging and diagnostics Measurements performed on a silicon phantom proved its suitability for NIROT applications

A Dynamic Vision Sensor With 1% Temporal Contrast Sensitivity and In-Pixel Asynchronous Delta Modulator for Event Encoding

Abstract: A dynamic vision sensor (DVS) encodes temporal contrast (TC) of light intensity into address-events that are asynchronously transmitted for subsequent processing. This paper describes a DVS with improved TC sensitivity and event encoding. To enhance the TC sensitivity, each pixel employs a common-gate photoreceptor for low output noise and a capacitively-coupled programmable gain amplifier for continuous-time signal amplification without sacrificing the intra-scene dynamic range. A proposed in-pixel asynchronous delta modulator (ADM) better preserves signal integrity in event encoding compared with self-timed reset (STR) used in previous DVSs. A 60 $\times$ 30 prototype sensor array with a 31.2 $~\mu\hbox{m}$ pixel pitch was fabricated in a 1P6M 0.18 $~\mu\hbox{m}$ CMOS technology. It consumes 720 $~\mu\hbox{W}$ at a 100k event/s output rate. Measurements show that a 1% TC sensitivity with a 35% relative standard deviation is achieved and that the in-pixel ADM is up to 3.5 times less susceptible to signal loss than STR in terms of event number. These improvements can facilitate the application of DVSs in areas like optical neuroimaging which is demonstrated in a simulated experiment.