Showing papers in "IEEE Journal of the Electron Devices Society in 2014"

Tunnel Field-Effect Transistors: State-of-the-Art

Abstract: Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ \({{\mu }}\) m. A common approach to TFET characterization is proposed to facilitate future comparisons.

A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

Abstract: The pinned photodiode is the primary photodetector structure used in most CCD and CMOS image sensors. This paper reviews the development, physics, and technology of the pinned photodiode.

Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain

Abstract: In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET). Unlike in the conventional TFET where the gate controls the tunneling barrier width at both source-channel and channel-drain interfaces for different polarity of gate voltage, overlapping the gate on the drain limits the gate to control only the tunneling barrier width at the source-channel interface irrespective of the polarity of the gate voltage. As a result, the proposed overlapping gate-on-drain TFET exhibits suppressed ambipolar conduction even when the drain doping is as high as \(1 \times 10^{19}\) cm \(^{-3}\) .

Pixel Level Characterization of Pinned Photodiode and Transfer Gate Physical Parameters in CMOS Image Sensors

Abstract: A method to extract the pinned photodiode (PPD) physical parameters inside a CMOS image sensor pixel array is presented The proposed technique is based on the Tan et al pinning voltage characteristic This pixel device characterization can be performed directly at the solid-state circuit output without the need of any external test structure The presented study analyzes the different injection mechanisms involved in the different regimes of the characteristic It is demonstrated that in addition to the pinning voltage, this fast measurement can be used to retrieve the PPD capacitance, the pixel equilibrium full well capacity, and both the transfer gate threshold voltage and its channel potential at a given gate voltage An alternative approach is also proposed to extract an objective pinning voltage value from this measurement

GaN Schottky Barrier Diode With TiN Electrode for Microwave Rectification

Abstract: GaN Schottky barrier diodes (SBDs) with low turn-on voltage are developed for microwave rectification. The diodes with reactively-sputtered TiN electrodes have a lower turn-on voltage compared with the diodes with Ni electrode, while the on-resistance, the reverse leakage current, and the reverse breakdown characteristics are comparable to each other. Theoretically, the SBDs with TiN electrodes can enhance the efficiency of a rectenna circuit at 2.45 GHz from 84% to 89% when the turn-on voltage decreases from 1.0 to 0.5 V.

Graphene for Electron Devices: The Panorama of a Decade

Abstract: Graphene emerged in 2004 as the first 2-D material with exotic properties. Since then the literature has been flooded with reports, with physicists, material scientists, and engineers grabbing their respective shares. Numerous reviews have also been published. While these reviews have done excellent works in their own ways, new reports are coming up faster than they could draw the attentions of researchers. The authors, therefore, feel that there is a demanding scope for a fresh review. Further, many aspects of graphene are not covered in the reviews so far. New concept devices are also entering into the arena of graphene day by day. The purpose of this paper is therefore to present a comprehensive review on the conventional as well as novel device applications of graphene. While we believe that graphene is the material which will transform the electron devices from the classical regime to the quantum world, it is difficult to believe that it will be a complete substitute to silicon in the near future.

Enhanced field effect mobility on 4H-SiC by oxidation at 1500◦C

Abstract: A novel 1500°C gate oxidation process has been demonstrated on Si face of 4H-SiC. Lateral channel metal-oxide-semiconductor-field-effect-transistors (MOSFETs) fabricated using this process have a maximum field effect mobility of approximately 40 cm\ 2 V -1 s -1 without post oxidation passivation. This is substantially higher than other reports of MOSFETs with thermally grown oxides (typically grown at the standard silicon temperature range of 1100-1200°C). This result shows the potential of a high temperature oxidation step for reducing the channel resistance (thus the overall conduction loss), in power 4H-SiC MOSFETs.

4H-SiC N-Channel JFET for Operation in High-Temperature Environments

Abstract: Lateral depletion-mode 4H-SiC n-channel junction field-effect transistors (JFETs) are demonstrated to operate with well-behaved electrical characteristics at temperatures up to 600 °C in air. Ti/Ni/TiW metal stacks are used to form ohmic contacts to n-type 4H-SiC with specific contact resistance of \(1.14 \times 10^{-3}~{\boldsymbol{\Omega }}\) cm \(^{2 }\) at 600 °C. The on/off drain saturation current ratio and intrinsic gain at 600 °C are \(1.53 \times 10^{3}\) and 57.2, respectively. These results indicate that 4H-SiC JFETs can be used for extremely-high-temperature electronics applications.

Compact Modeling of Flicker Noise in HEMTs

Abstract: In this paper, we present a physics-based compact model for low frequency noise in high electron mobility transistors (HEMTs). The model is derived considering the physical mechanisms of carrier number fluctuation and mobility fluctuation in the channel. The model is tunable and hence applicable to a wide range of HEMT devices of different geometries and construction. The model is in excellent agreement with experimental data and TCAD simulations.

On the Device Design and Drive-Current Capability of SOI Lateral Bipolar Transistors

Abstract: The SOI symmetric lateral bipolar transistor is uniquely suitable for operation at high injection currents where the injected minority carrier density in the base region is larger than the base doping concentration. Transistors operating in high-injection can achieve record-high drive currents on the order of 3-5 mA/μm. The commonly used Shockley diode and bipolar current equations are modified to be applicable for all injection levels. Excellent agreement is shown between measured and modeled currents for data at V BC = 0. A novel partially depleted-base design can further increase the drive current and the current gain, especially at low V BE .

Junctionless Silicon Nanowire Resonator

Abstract: The development of nanoelectromechanical systems (NEMS) is likely to open up a broad spectrum of applications in science and technology. In this paper, we demonstrate a novel double-transduction principle for silicon nanowire resonators, which exploits the depletion charge modulation in a junctionless field effect transistor body and the piezoresistive modulation. A mechanical resonance at the very high frequency of 100 MHz is detected in the drain current of the highly doped silicon wire with a cross-section down to ~ 30 nm. We show that the depletion charge modulation provides a ~ 35 dB increase in output signal-to-noise compared to the second-order piezoresistive detection, which can be separately investigated within the same device. The proposed junctionless resonator stands, therefore, as a unique and valuable tool for comparing the field effect and the piezoresistive modulation efficiency in the same structure, depending on size and doping. The experimental frequency stability of 10 ppm translates into an estimated mass detection noise floor of ~ 60 kDa at a few seconds integration time in high vacuum and at room temperature. Integrated with conventional semiconductor technology, this device offers new opportunities for NEMS-based sensor and signal processing systems hybridized with CMOS circuitry on a single chip.

New Analytical Model for Nanoscale Tri-Gate SOI MOSFETs Including Quantum Effects

Abstract: In this paper, an analytical model for tri-Gate (TG) MOSFETs considering quantum effects is presented. The proposed model is based on the analytical solution of Schrodinger-Poisson's equation using variational approach. An analytical expression of the inversion charge distribution function (ICDF) or wave function for the TG MOSFETs has been developed. This obtained ICDF is used to calculate the device parameters, such as the inversion charge centroid, threshold voltage, inversion charge, gate capacitance, and drain current. These parameters are modeled for various device dimensions and applied bias. The results are validated against the TCAD simulation results.

Extraction and Estimation of Pinned Photodiode Capacitance in CMOS Image Sensors

Abstract: The pinned photodiode capacitance extraction method proposed by Goiffon et al. is discussed, and two additional new methods are presented and analyzed; one based on the full well dependence on photon flux and the other based on the full well dependence on transfer-gate off-voltage.

A Combined Modulation of Set Current With Reset Voltage to Achieve 2-bit/cell Performance for Filament-Based RRAM

Abstract: A combined operation scheme to realize multibit switching in filament-based bipolar RRAM device is proposed. By combining the modulations of the current compliance in set operations with the stop voltage in reset operations together, the size or the quantity of the filaments in the film bulk can be controlled. An RRAM device with the structure of Ag/HfO x /Pt is fabricated and the 2-bit/cell memory function is achieved by the proposed modulation. Furthermore, the 2-bit/cell data reliability is satisfactory including the high-temperature retention, cycling endurance.

All-Graphene Planar Double Barrier Resonant Tunneling Diodes

Abstract: In this work, we propose an atomically-thin all-graphene planar double barrier resonant tunneling diode that can be realized within a single graphene nanoribbon. The proposed device does not require any doping or external gating and can be fabricated using minimal process steps. The planar architecture of the device allows a simple in-plane connection of multiple devices in parallel without any extra processing steps during fabrication, enhancing the current driving capabilities of the device. Quantum mechanical simulation results, based on non-equilibrium Green's function formalism and the extended Huckel method, show promising device performance with a high reverse-to-forward current rectification ratio exceeding 50 000, and confirm the presence of negative differential resistance within the device's current-voltage characteristics.

Effect of Source/Drain Lateral Straggle on Distortion and Intrinsic Performance of Asymmetric Underlap DG-MOSFETs

Abstract: This paper presents a systematic study of the effect of source/drain (S/D) implant lateral straggle on the RF performance of the symmetric and asymmetric underlap double gate (UDG) MOSFET devices. The length of the underlap regions ( L \({}_{un}\) ) on each side of the gate is a critical technology parameter in determining the performance of UDG-MOSFETs. However, the value of L \({}_{un}\) is susceptible to variation due to S/D implant lateral diffusion. Therefore, it is critical to investigate the impact of S/D implant lateral straggle on the performance of UDG-MOSFETs. This paper shows that the improvement in the RF performance of the UDG-MOSFETs over the conventional DG-MOSFETs can be achieved by optimizing the S/D lateral straggle of the asymmetric UDG-MOSFETs. The RF performance study includes intrinsic capacitances and resistances, transport delay, inductance, and the cut-off frequency.

Sub-10-nm Asymmetric Junctionless Tunnel Field-Effect Transistors

Abstract: This study presents a new asymmetric junctionless tunnel field-effect transistor (AJ-TFET) to scale TFETs into sub-10-nm regimes. The asymmetric junctionless p+ source/body and junctional n/p+ drain/body separately optimize the lateral source and drain coupling to efficiently switch the TFETs, producing an abrupt on-off switching. Because of n-drain/p+body junction, the off-state tunnel barrier can be extended into the drain, ensuring an excellent short-channel effect without the limitation of channel lengths. Si/Ge heterojunctions and high-k gate insulators are combined with the AJ-TFETs for additional on-current boosting. Using compact structures and feasible parameters from practical Si-based CMOS technologies, the advancement in the on-off switching and short-channel effect make the AJ-TFET highly promising as an ideal approach into the sub-10-nm regimes.

CMOS Compatible Fabrication Processes for the Digital Micromirror Device

Abstract: DLP® technology has been widely used in the display products since it was first introduced to the world in 1996 by Texas Instruments. Projectors powered by DLP® technology range from cinema projectors that light up large movie theater screens to palm-sized “Pico” projectors. The heart of the technology is the digital micromirror device (DMD) that features an addressable array of up to 8 million microscopic mirrors. DMDs are fabricated using standard semiconductor processing equipment. However due to the unique nature of MOEMS application and digital operation of the DMDs, special CMOS-compatible fabrication processes have been developed to produce highly reflective digital micromirrors with robust operation margin and long term reliability. This paper will present an overview of the fabrication processes of the DMDs.

Integration of Micro Resistance Thermometer Detectors in AlGaN/GaN Devices

Abstract: Temperature measurements in AlGaN/GaN high electron mobility transistors are required for proper device design, modeling and achieving appropriate reliability. These measurements usually require sophisticated equipment and extensive calibration. This study evaluates the feasibility of temperature measurements by integration of a Pt resistance thermal detector (RTD) in an “un-gated” transistor and evaluating their electrical interactions. The integrated RTD presents the advantage of being independent of the device. Micro RTD showed a linear response in the calibration interval (0 to 206 °C). Measured temperature values using the micro RTD are in agreement with 3D finite element simulations at multiple bias conditions in the “un-gated” transistor. Measurements show no noticeable electrical perturbation between the device and RTD under simultaneous operation.

Electrical Hole Transport Properties of an Ambipolar Organic Compound With Zn-Atoms on a Crystalline Silicon Heterostructure

Abstract: In this paper, we investigate the electrical hole transport properties of an organic/inorganic heterostructure consisting of a thin organic film, that combines hole and electron conducting molecules around a bridging Zn-atom, deposited on top of an n-type crystalline silicon substrate. Current-voltage characteristics and capacitance voltage measurements have been used for the determination of the organic layer dielectric and hole conduction parameters.

Optically Powered Energy Source in a Standard CMOS Process for Integration in Smart Dust Applications

Abstract: In order to miniaturize nano-power sensor nodes or smart dust, an optically powered energy source is developed to replace traditional batteries or solar cells. This energy source consists of two photodiodes, which are P-well/DN-well and N-well/P-sub. The two photodiodes with an area of 1.5mm \(^{2}\) were fabricated using the UMC \(0.25{\mu }\) m CMOS process and tested using an 830nm laser. Measurement results show that the energy source is able to generate a voltage from 0.5V to 0.8V with a 3.5% conversion efficiency. The proposed energy source was made using a standard CMOS process and therefore can to be integrated with the smart dust circuit on a single chip.

Via Diode in Cu Backend Process for 3D Cross-Point RRAM Arrays

Abstract: In this paper, a fully logic compatible via diode is developed for high-density resistive random access memory (RRAM) array applications. This novel via diode is realized by advanced 28nm CMOS technology with Cu damascene via. The device is stacked between a top Cu via and a bottom Cu metal with a composite layer of TaN/TaON based dielectric film. An asymmetric current-voltage characteristic in this MIM structure provides a forward/reverse current ratio up to 10 6 . In a cross-point RRAM array, the suppression of sneak current path by incorporating this via diode enables array size to be greatly expended. Via diode provides an excellent solution for high-density embedded nonvolatile memory applications in the nano-scale CMOS technology.

Hybrid-Type Temperature Sensor Using Thin-Film Transistors

Abstract: We have developed a hybrid-type temperature sensor using thin-film transistors. First, we evaluate temperature dependences of transistor characteristics and find that the temperature dependence of the off-leakage current is much larger than that of the on current. Next, we combine a transistor, capacitor, and ring oscillator to develop the hybrid-type temperature sensor and detect the temperature by measuring the oscillation frequency. The large temperature dependences of the off-leakage currents can be utilized, and simultaneously only a digital circuit is required to count the digital pulse.

SiGe HBT Technology Based on a 0.13- $\mu{\rm m}$ Process Featuring an ${f}_{\rm MAX}$ of 325 GHz

Abstract: A self-aligned SiGe HBT technology achieving a cutoff frequency $({f}_{\rm T})$ of 253 GHz was developed using a selective SiGe epitaxial growth process. Germanium concentration in an i-SiGe layer just under a ${\rm p}^{+}$ intrinsic base region was raised to 27.4% to improve ${f}_{\rm T}$ , and boron concentration in the intrinsic base region reached $2.4\times 10^{20}~{\rm cm}^{-3}$ as a deposition to maintain a breakdown voltage of 1.5 V. A 0.13- $\mu{\rm m}$ SiGe BiCMOS technology geometrically advanced from an earlier 0.18- $\mu{\rm m}$ version shrinks the emitter width from 0.2 to 0.12 $\mu{\rm m}$ to reduce collector-base capacitance and base resistance. It achieves a maximum oscillation frequency $({f}_{\rm MAX})$ of 325 GHz. This technology can be applied to optical and mm wave communication systems.

Improvement in the Light Extraction of Blue InGaN/GaN-Based LEDs Using Patterned Metal Contacts

Abstract: We demonstrate a method to improve the light extraction from an LED using photonic crystal (PhC)-like structures in metal contacts. A patterned metal contact with an array of Silicon Oxide (SiOx) pillars (440 nm in size) on an InGaN/GaN-based MQW LED has shown to increase output illumination uniformity through experimental characterization. Structural methods of improving light extraction using transparent contacts or dielectric photonic crystals typically require a tradeoff between improving light extraction and optimal electrical characteristics. The method presented here provides an alternate solution to provide a 15% directional improvement (surface normal) in the radiation profile and ~ 30% increase in the respective intensity profile without affecting the electrical characteristics of the device. Electron beam patterning of hydrogen silesquioxane (HSQ), a novel electron beam resist is used in patterning these metal contacts. After patterning, thermal curing of the patterned resist is done to form SiOx pillars. These SiOx pillars aid as a mask for transferring the pattern to the p-metal contact. Electrical and optical characterization results of LEDs fabricated with and without patterned contacts are presented. We present the radiation and intensity profiles of the planar and patterned devices extracted using Matlab-based image analysis technique from 200 μm (diameter) circular unpackaged LEDs.

First Demonstration of Ultra-Thin SiGe-Channel Junctionless Accumulation-Mode (JAM) Bulk FinFETs on Si Substrate with PN Junction-Isolation Scheme

Abstract: A SiGe-channel junctionless-accumulation-mode (JAM) PMOS bulk FinFETs were successfully demonstrated on Si substrate with PN junction-isolation scheme for the first time. The JAM bulk FinFETs with fin width of 18 nm exhibits excellent subthreshold characteristics such as subthreshold swing of 64 mV/decade, drain-induced barrier lowering (DIBL) of 40 mV/V and high I on /I off current ratio (>1 × 10 5 ). The change of substrate bias from 0 to 5 V leads to the threshold voltage shift of 53 mV by modulating the effective channel thickness. When compared to the Si-channel bulk FinFETs with fin width of 18 nm, Si and SiGe channel devices exhibits comparable subthreshold swing and DIBL. For devices with longer fin width, SiGe channel devices exhibits much lower DIBL, indicating superior top-gate controllability and robustness to substrate bias compared to the Si channel devices. A zero temperature coefficient point was observed in the transfer curves as temperature increases from -120 to 120°C, confirming that mobility degradation is dominantly affected by phonon scattering mechanism.

Expansion of the J-EDS Editorial Board

Abstract: Anyone, anytime, anywhere is the hallmark of OPEN ACCESS publications. This philosophy is serving us well as the IEEE Journal of Electron Devices Society (J-EDS) continues to grow. On January 1st 2013, when J-EDS was launched , I had written to you introducing the five editors constituting the founding editorial board of the nascent J-EDS. At that time, I had also stated that the board will be expanded as the manuscript submission rate climbs. At this time, the editorial board is being doubled in size by adding five additional members. These professionals are established senior researchers in the field of electron devices and widely respected in their areas of specialty. They have been handpicked to reflect the J-EDS editorial culture of proactively helping authors publish their best work in the journal. As mentioned in my January 2013 editorial , “In a sense, the editor is to assume a supportive role in helping the author improve the quality of the manuscript rather than simply passing a judgment.”