Showing papers in "IEEE Journal of the Electron Devices Society in 2015"

Tunnel Field-Effect Transistors: Prospects and Challenges

Abstract: The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Two-Dimensional Heterojunction Interlayer Tunneling Field Effect Transistors (Thin-TFETs)

Abstract: Layered 2-D crystals embrace unique features of atomically thin bodies, dangling bond free interfaces, and step-like 2-D density of states. To exploit these features for the design of a steep slope transistor, we propose a Two-dimensional heterojunction interlayer tunneling field effect transistor (Thin-TFET), where a steep subthreshold swing (SS) of $\sim 14$ mV/dec and a high on-current of $\sim 300~\mu $ A/ $\mu $ m are estimated theoretically. The SS is ultimately limited by the density of states broadening at the band edges and the on-current density is estimated based on the interlayer charge transfer time measured in recent experimental studies. To minimize supply voltage $\mathrm{V}_{DD}$ while simultaneously maximizing on currents, Thin-TFETs are best realized in heterostructures with near broken gap energy band alignment. Using the WSe2/SnSe2 stacked-monolayer heterostructure, a model material system with desired properties for Thin-TFETs, the performance of both ${n}$ -type and ${p}$ -type Thin-TFETs is theoretically evaluated. Nonideal effects such as a nonuniform van der Waals gap thickness between the two 2-D semiconductors and finite total access resistance are also studied. Finally, we present a benchmark study for digital applications, showing the Thin-TFETs may outperform CMOS and III–V TFETs in term of both switching speed and energy consumption at low-supply voltages.

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Abstract: Guided by the Wentzel-Kramers–Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ${I} _{\rm D} = 64~\mu $ A/ $\mu $ m at ${V} _{\rm DS} = {V} _{\rm GS} - {V} _{\rm off} = -1.0$ V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at ${V} _{\rm DD}$ as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

TFET-Based Circuit Design Using the Transconductance Generation Efficiency $ {g}_{m}/ {I}_{d}$ Method

Abstract: Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g., GHz operation with sub-0.1 mW power consumption); 2) discuss and employ a compact TFET device model in the context of the $g_{m}/I_{d}$ integrated analog circuit design methodology; and 3) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being interband tunneling rather than thermionic emission. Starting from technology computer-aided design and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate TFETs at the 20-nm gate-length node, we conclude that GNR TFETs might promise larger bandwidths at low-voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.

Graphene Field-Effect Transistors for Radio-Frequency Flexible Electronics

Abstract: Flexible radio-frequency (RF) electronics require materials which possess both exceptional electronic properties and high-strain limits. While flexible graphene field-effect transistors (GFETs) have demonstrated significantly higher strain limits than FETs fabricated from thin films of Si and III-V semiconductors, to date RF performance has been comparatively worse, limited to the low GHz frequency range. However, flexible GFETs have only been fabricated with modestly scaled channel lengths. In this paper, we fabricate GFETs on flexible substrates with short channel lengths of 260 nm. These devices demonstrate extrinsic unity-power-gain frequencies, f max , up to 7.6 GHz and strain limits of 2%, representing strain limits an order of magnitude higher than the flexible technology with next highest reported f max .

Best Practices for Compact Modeling in Verilog-A

Abstract: Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.

Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells

Abstract: We use mixed device-circuit simulations to predict the performance of 6T static RAM (SRAM) cells implemented with tunnel-FETs (TFETs) Idealized template devices are used to assess the impact of device unidirectionality, which is inherent to TFETs and identify the most promising configuration for the access transistors The same template devices are used to investigate the $\text{V}_{\rm DD}$ range, where TFETs may be advantageous compared to conventional CMOS The impact of device ambipolarity on SRAM operation is also analyzed Realistic device templates extracted from experimental data of fabricated state-of-the-art silicon pTFET are then used to estimate the performance gap between the simulation of idealized TFETs and the best experimental implementations

A Time-of-Flight Range Image Sensor With Background Canceling Lock-in Pixels Based on Lateral Electric Field Charge Modulation

Abstract: This paper presents a CMOS time-of-flight (ToF) range image sensor using high-speed lock-in pixels with background light canceling capability. The proposed lock-in pixel uses MOS gate-induced lateral electric field control of depleted potential of pinned photodiode for implementing a multiple-tap charge modulator while achieving a high-speed charge transfer for high-time resolution. A TOF image sensor with 320 x 240 effective pixels is implemented using a 0.11- $\mu \text{m}$ CMOS image sensor process. The TOF sensor has a range resolution of less than 12 mm without background light and 20 mm under background line for the range from 0.8 to 1.8 m and integration time of 50 ms. The effectiveness of in-pixel background light canceling with a three-tap output pixel is demonstrated.

Ferroelectricity of HfZrO 2 in Energy Landscape With Surface Potential Gain for Low-Power Steep-Slope Transistors

Abstract: The corresponding energy landscape and surface potential are deduced from the experimental ferroelectricity of HfZrO2 (HZO) for low-power steep-slope transistor applications The anti-ferroelectric (AFE) in annealed 600°C HZO extracted electrostatic potential gain from the measured polarization hysteresis loop and calculated subthreshold swing 33 mV/dec over six decades of $I_{\rm DS} $ A feasible concept of coupling the AFE HZO is experimentally established with the validity of negative capacitance and beneficial for steep-slope FET development in future generation

Band-Offset Engineering for GeSn-SiGeSn Hetero Tunnel FETs and the Role of Strain

Abstract: In this paper a simulation study of the effect of conduction and valence band offsets on the subthreshold swing (SS) of a double-gate tunnel field-effect transistor (TFET) with gate-overlapped source is presented. The simulations show that if the pn-junction and the hetero-junction coincide, the band offsets can significantly improve the SS by suppressing the so-called point tunneling at the pn-junction. It turns out that the performance of an n-channel TFET is determined by the direct conduction band offset whereas that of a p-channel TFET is mainly effected by the energy difference between the light hole bands of the two materials. Thus, the performance of the hetero-junction TFET can be improved by selecting material systems with high conduction or valence band offsets. The misalignment between the pn-junction and the hetero-junction is shown to degrade the SS. The above-described band-offset engineering has been applied to the GeSn/SiGeSn hetero-structure system with and without strain. Simulations of GeSn/SiGeSn hetero-TFETs with band-to-band-tunneling parameters determined from pseudopotential calculations show that compressive strain in GeSn widens the design space for TFET application while tensile strain reduces it.

A Pump-Gate Jot Device With High Conversion Gain for a Quanta Image Sensor

Abstract: A new photodetector designed for Quanta image sensor application is proposed. The photodetector is a backside-illuminated, buried photodiode with a vertically integrated pump and transfer gate and a distal floating diffusion to reduce parasitic capacitance. The structure features compact layout and high conversion gain. The proposed device is modeled and simulated, and its performance characteristics estimated.

Characterization of Quanta Image Sensor Pump-Gate Jots With Deep Sub-Electron Read Noise

Abstract: Characterization of quanta image sensor pixels with deep sub-electron read noise is reported. Pixels with conversion gain of $423\mu \text{V}$ /e- and read noise as low as 0.22e- r.m.s. were measured. Dark current is 0.1e-/s at room temperature, and lag less than 0.1e-. This is one of the first works reporting detailed characterization of image sensor pixels with mean signals from sub-electron (0.25e-) to a few electrons level. Such pixels in a nearly-conventional CMOS image sensor process will allow realization of photon-counting image sensors for a variety of applications.

III-V Heterostructure Nanowire Tunnel FETs

Abstract: In this paper, InAs/GaSb nanowire tunnel field-effect transistors (TFETs) are studied theoretically and experimentally. A 2-band 1-D analytic tunneling model is used to calculate the on- and off-current levels of nanowire TFETs with staggered source/channel band alignment. Experimental results from lateral InAs/GaSb are shown, as well as first results on integration of vertical InAs/GaSb nanowire TFETs on Si substrates.

Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates

Abstract: In this paper, we introduce ${p}$ -channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III–V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, ${I} _{\rm on}$ of 6 $\mu $ A/ $\mu $ m ( $|V_{GS}| = |V_{DS}| = 1$ V) and a room-temperature subthreshold swing ( SS ) of $\sim 160$ mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET ${I} _{\rm on}$ performance by 1–2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.

Source/Drain Doping Effects and Performance Analysis of Ballistic III-V n-MOSFETs

Abstract: Effects of source/drain (S/D) doping density (N SD ) on the ballistic performance of III-V nanowire (NW) n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) are explored through atomistic quantum transport simulation. Different III-V materials (InAs, GaAs) and transport directions ( , ) are considered with Si included for benchmarking for a gate length of 13 nm. For III-V's, depending on the operating condition (OFF-current target for a given supply voltage), there exists an optimum N SD that maximizes ON-current (I ON ) by balancing source exhaustion versus tunneling leakage. For InAs, sub-threshold swing degrades significantly with increasing N SD due to the light effective mass (m*) and source-drain tunneling, so the optimum N SD is low. For GaAs, such dependence is much weaker due to the larger m*, and the optimum N SD is higher. With optimized N SD 's, InAs shows low ballistic I ON due to the low density-of-state (DOS) whereas GaAs NW with transport direction shows good ballistic I ON due to the improved DOS with still high injection velocity, making it a better candidate for high performance device.

An Improved Model for the Full Well Capacity in Pinned Photodiode CMOS Image Sensors

Abstract: An improved analytical model for quantifying the full well capacity in pinned photodiode (PPD) CMOS image sensors is proposed. The model captures the characteristics of the realistic technology-induced vertical doping nonuniformity in photon sensing N-type area of the PPD structure and the voltage dependency of the PPD capacitance, respectively, both of which were neglected in the existing works. Excellent agreement between measured and predicted data shows that the proposed model fits a wider range of technology conditions for a wider spectra responding compared to the up-to-date reported model.

Strain-Engineered Biaxial Tensile Epitaxial Germanium for High-Performance Ge/InGaAs Tunnel Field-Effect Transistors

Abstract: The structural, morphological, and energy band alignment properties of biaxial tensile-strained germanium epilayers, grown in-situ on GaAs via a linearly graded InxGa1−xAs buffer architecture and utilizing dual chamber molecular beam epitaxy, were investigated. Precise control over the growth conditions yielded a tunable in-plane biaxial tensile strain within the Ge thin films that was modulated by the underlying InxGa1−xAs “virtual substrate” composition. In-plane tensile strains up to 1.94% were achieved without Ge relaxation for layer thicknesses of 15 to 30 nm. High-resolution x-ray diffraction supported the pseudomorphic nature of the Ge/InxGa1−xAs interface, indicating a quasi-ideal stress transfer to the Ge lattice. High-resolution transmission electron microscopy revealed defect-free Ge epitaxy and a sharp, coherent interface at the Ge/InxGa1−xAs heterojunction. Surface morphology characterization using atomic force microscopy exhibited symmetric, 2-D cross-hatch patterns with root mean square roughness less than 4.5 nm. X-ray photoelectron spectroscopic analysis revealed a positive, monotonic trend in band offsets for increasing tensile strain. The superior structural and band alignment properties of strain-engineered epitaxial Ge suggest that tensile-strained Ge/InxGa1−xAs heterostructures show great potential for future high-performance tunnel field-effect transistor architectures requiring flexible device design criteria while maintaining low power, energy-efficient device operation.

1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design

Abstract: In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) devices. The Tunnel FET based DRAM cell has an asymmetric body and a partial overlap of the top gate (L $_{\rm G1}$ ) with a total overlap of the back gate over the channel region (L $_{\rm G2}$ ). A potential well is created by biasing the back gate (V $_{\rm G2}$ ) in accumulation while the front gate (V $_{\rm G1}$ ) is in inversion. Holes from the p+ source are injected by the forward-biased source/channel junction and stored in the electrically induced potential well. Programming conditions and related transients are reported and the role of temperature is investigated.

Exploiting Hetero-Junctions to Improve the Performance of III–V Nanowire Tunnel-FETs

Abstract: This paper presents full-quantum 3-D simulations predicting the electrical performance of nanowire tunnel-FETs based on III–V hetero-junctions. Our calculations exploit an eight-band $\mathrm {k}\cdot \mathrm {p}$ Hamiltonian within the nonequilibrium Green’s functions formalism and include phonon scattering. It is shown that the on-current of GaSb/InAs hetero-junction tunnel-FETs is limited by quantum confinement effects on the bandstructure induced by the small nanowire diameter necessary to preserve an optimal electrostatic integrity at short gate lengths. To circumvent this problem, additional on-current improvements with no substantial subthreshold swing degradation can be achieved by engineering the source region through the insertion of an InAs/GaSb/InAs quantum well along the transport direction. Such a design option is predicted to provide on/off-current ratios larger than $10^{7}$ even at $V_{DD}$ = 300 mV.

Exploring the Design Space for Crossbar Arrays Built With Mixed-Ionic-Electronic-Conduction (MIEC) Access Devices

Abstract: Large-scale 3-D crossbar arrays offer a path to both high-density storage class memory and novel non-Von Neumann computation. However, such arrays require each non-volatile memory (NVM) element to have its own non-linear access device (AD), which must pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Using circuit-level SPICE simulations, we explore design constraints on crossbar arrays composed of a generic NVM element (+1R) together with the novel AD developed by our group, based on Cu-containing mixed-ionic-electronic-conduction (MIEC) materials. We show that power consumption during write, not read margin, is the most stringent constraint for large 1AD+1R crossbar arrays. As array size grows, in order to keep NVM write power-efficient, the voltage at which the AD “turns on” must outpace the NVM switching voltage. Failure to achieve this condition causes the total array power, injected into the array to ensure the success of the worst-case single-bit write, to greatly exceed the actual NVM write power. Extensive tolerancing results show that NVM switching current and other AD parameters (subthreshold slope and series resistance) are also important, but not to the same degree as AD and NVM voltage characteristics. We show that scaled MIEC devices (Voltage Margin $V_{m} \sim $ 1.54V) can support 1 Mb arrays for NVM switching voltages up to 1.2V, and that stacking two MIEC devices could enable $\sim 2.4\text{V}$ . The impact of $V_{m}$ variability is quantified—we show that there is minimal degradation in write power and read margin at variabilities (standard deviation in $V_{m}$ ) not very different from those already demonstrated experimentally.

Impact of Super-Linear Onset, Off-Region Due to Uni-Directional Conductance and Dominant $\mathrm{C}_{\text {GD}}$ on Performance of TFET-Based Circuits

Abstract: This paper investigates the consequences of several distinctive device characteristics of tunnel FETs (TFET), namely super-linear onset, uni-directional conduction, and the dominant gate-drain capacitance, regarding the energy consumption, propagation delay, and noise resilience. Simulations have shown that these TFET specific characteristics have a detrimental effect on the dynamic response. We also report that their impact remains significant when operating voltage is scaled. Thus device level optimizations are required to eliminate these attributes to take full advantage of TFETs small subthreshold swing and low voltage operation.

A 3-Phase AC–AC Matrix Converter GaN Chipset With Drive-by-Microwave Technology

Abstract: This paper describes an ultracompact GaN 3 × 3 matrix power converter with drive-by-microwave (DBM) technology, which comprises a radio frequency (RF)-triggered GaN-gate injection transistor (GIT) bidirectional power switches integration chip with co-integrated RF rectifiers, novel isolated dividing couplers in a printed circuit board to reduce complicated gate lines, and low-consumption GaN/Si DBM gate driver on a chip that controls nine bi-directional power switches. The proposed 4.0-kW GaN 3 × 3 matrix power converter is extremely compact, measuring only 18 × 25 mm due to the use of GaN-GIT power device integration technology and DBM technology that provides isolated gate signals by microwave wireless power transmission and eliminates the need for photo-couplers and isolated power supplies. The GaN/Si DBM driver realizes low power consumption of only 2.0 W as a result of gate power sharing with three RF oscillators. The sequential switching operation by the fabricated GaN 3 × 3 matrix converter was successfully achieved.

Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model

Abstract: In this paper, an analytical model of threshold voltage for bulk MOSFET is developed. The model is derived from the physical charge-based core of BSIM6 MOSFET model, taking into account short channel effects, and is intended to be used in commercial SPICE simulators for operating point information. The model is validated with measurement data from IBM 90-nm technology node using various popular threshold voltage extraction techniques, and good agreement is obtained.

Investigation and Simulation of Work-Function Variation for III–V Broken-Gap Heterojunction Tunnel FET

Abstract: This paper investigates and compares the impacts of metal-gate work-function variation (WFV) on III–V heterojunction tunnel FET (HTFET), homojunction TFET, and FinFET devices using a novel Voronoi method to capture the realistic metal-gate grain patterns for Technology Computer Aided Design atomistic simulations. Due to the broken-gap nature, HTFET shows significantly steeper subthreshold slope and higher susceptibility to WFV near OFF state. For ON current variation, both the HTFET and homojunction TFET show better immunity to WFV than the III–V FinFET. Device design using source-side underlap to mitigate the impact of WFV on HTFET is also assessed.

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

Abstract: A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high ${I}_{\rm on} /{I}_{\rm off} $ current ratio of $7\times 10^{8} $ ( $V_{\rm G} = 4$ V and $V_{\rm D} = 1$ V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs

Abstract: An improved analytical model for flicker noise (1/ $f$ noise) in MOSFETs is presented. Current models do not capture the effect of high-trap density in the halo regions of the devices, which leads to significantly different bias dependence of flicker noise across device geometry. The proposed model is the first compact model implementation capturing such effect and show distinct improvements over other existing noise models. The model is compatible with BSIM6, the latest industry standard model for bulk MOSFET, and is validated with measurements from 45-nm low-power CMOS technology node.

High Brightness GaN-on-Si Based Blue LEDs Grown on 150 mm Si Substrates Using Thin Buffer Layer Technology

Abstract: The commercial adoption of GaN-on-Si light emitting diode (LED) chip technology is lagging behind incumbent sapphire substrates due to significantly longer growth time and poorer crystalline quality. To address these challenges, we report on the growth of high-quality crack-free InGaN/GaN LED structure on 150 mm Si (111) substrate using thin buffer layer technology. The total epilayer thickness is only $3.75~{\mu } \text{m}$ , offering significant growth time savings and faster manufacturing process throughput. A SiNx interlayer is inserted in the buffer layer to promote lateral overgrowth and improve material quality, resulting in full width at half maximum ${ }$ and ${ - $12{>}$ of 380 and 390 arcsec, respectively. Reducing dislocation density and optimizing KOH roughening of the n-GaN layer is found to be critical toward improving device performance. The devices were processed as 1 $\times$ 1 mm2 vertical thin film dies and mounted into a conventional 3535 package with silicone dome lens. The result is a light output power of 563 mW and an operating voltage of 3.05 V, corresponding to a wall-plug-efficiency of 52.7% when driven at 350 mA. These results attest the feasibility of thin buffer GaN-on-Si technology for solid state lighting applications.

X-Band Compatible Flexible Microwave Inductors and Capacitors on Plastic Substrate

Abstract: Microwave inductors and capacitors compatible with low temperature processes form a route to high-frequency electronics on flexible substrates in conjunction with high speed thin film transistors. We report here the process by which one can fabricate passive components with X-band compatible performance on polyethylene terephthalate substrate by changing dielectric layer material and optimized design, where the method can be applied with most of the active device technologies developed up to date on flexible substrates. High resonance frequencies were obtained, comparing with former results, confirming the effectiveness of the approach with flexible dielectric materials. Studies on bending effects for the spiral inductors and metal on insulator capacitors show miniscule difference in performance related to bending radius. Performance enhancements compared to previously reported passive elements enable higher radio-frequency electronics on plastic substrates.

Heteroepitaxial Ge MOS Devices on Si Using Composite AlAs/GaAs Buffer

Abstract: Structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated. Electrical characteristics of N-type metal-oxide-semiconductor (MOS) capacitors, fabricated from the aforementioned material stack are then presented. Simulated and experimental X-ray rocking curves show distinct Ge, AlAs, and GaAs epilayer peaks. Moreover, secondary ion mass spectrometry, energy dispersive X-ray spectroscopy (EDS) profile, and EDS line profile suggest limited interdiffusion of the underlying buffer into the Ge layer, which is further indicative of the successful growth of device-quality epitaxial Ge layer. The Ge MOS capacitor devices demonstrated low frequency dispersion of 1.80% per decade, low frequency-dependent flat-band voltage, $V_{FB}$ , shift of 153 mV, efficient Fermi level movement, and limited C-V stretch out. Low interface state density $(D_{it} )$ from $8.55 \times 10^{11} $ to $1.09 \times 10^{12}~ {\rm cm}^{-2} ~{\rm eV}^{-1} $ is indicative of a high-quality oxide/Ge heterointerface, an effective electrical passivation of the Ge surface, and a Ge epitaxy with minimal defects. These superior electrical and material characteristics suggest the feasibility of utilizing large bandgap III-V buffers in the heterointegration of high-mobility channel materials on Si for future high-speed complementary metal-oxide semiconductor logic applications.

On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET

Abstract: Dual-independent-gate silicon FinFET has demonstrated a steep subthreshold slope (SS) when a positive feedback induced by weak impact ionization is triggered. In this paper, we study the temperature dependency of the steep SS by characterizing the fabricated device from 100 to 380 K. The measured characteristics of SS show a reduced sensitivity to temperature as compared to conventional MOSFETs. Based on the temperature-dependent characterization, we further analyze the steep-SS characteristics and propose feasible improvements for optimizing the device performance.