Showing papers in "IEEE Journal of the Electron Devices Society in 2019"

Ferroelectric HfO 2 Tunnel Junction Memory With High TER and Multi-Level Operation Featuring Metal Replacement Process

Abstract: We have investigated device design of HfO2-based ferroelectric tunnel junction (FTJ) memory. Asymmetry of dielectric screening property in top and bottom electrodes is the key for high tunneling electroresistance (TER) ratio. Thus, metal and semiconductor electrodes are proposed. There exists a design space of ferroelectric material parameters to achieve high TER ratio under the constraint of depolarizing field. We have developed an FTJ fabrication process to realize the design. Large polarization charge and symmetric switching voltage are obtained by top metal replacement process. High TER ratio >30 and multi-level cell operation have been successfully demonstrated. Retention characteristics is promising, however, endurance characteristics should be improved for reliable operation.

Direct Correlation of Ferroelectric Properties and Memory Characteristics in Ferroelectric Tunnel Junctions

Abstract: Ferroelectric memories have made big advancements in the last years due to the discovery of ferroelectricity in already widely used hafnium oxide. Here we investigate ferroelectric tunnel junctions (FTJ) consisting of a ferroelectric hafnium zirconium oxide layer and a dielectric aluminum oxide layer. By varying the set and reset amplitude and pulse width the fraction of reversed ferroelectric domains can be controlled. Due to the statistical distribution of the coercive voltage the current can be tuned between the minimum off-state and maximum on-state current. This leads to possible multi-level information storage in our FTJs. In this paper a detailed study of the set/reset operation and the intermediate current levels is presented. Furthermore, the endurance properties of the memory device can be directly correlated to the wake-up and fatigue phenomena in the ferroelectric layer. While the usability of the memory window is still limited by the initial polarization increase and ultimately by the hard breakdown of the device, a further optimization of the ferroelectric layer itself and the ferroelectric/dielectric interface can directly improve the viability of the tunnel junction. Finally, we show that the current of our FTJs scales as expected and reproducible results across different devices are obtained.

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

Abstract: As a possible pathway to continue Moore’s law indefinitely into the future as well as unprecedented beyond-Moore heterogeneous integration, we examine the prospects of building monolithic 3D integrated circuits (M3D-IC) with atomically-thin or 2D van der Waals materials in terms of overcoming the major drawbacks of current 3D-ICs, including low process thermal budget, inter-tier signal delay, chip-overheating, and inter-tier electrical interference problems. Our holistic evaluation includes consideration of the electrical performance, thermal issues, and electromagnetic interference as well as attention to the synthesis methods necessary for low-temperature transfer-free 2D materials growth in M3D fabrication. Both in-plane and out-of-plane heat-dissipation in 3D-ICs made with 2D materials are evaluated and compared with those of bulk materials. Electrostatic and high-frequency electric-field simulations are conducted to assess the screening effect by graphene and effect of scaling down the inter-layer dielectric (ILD) thickness. Our analysis reveals for the first time that the 2D-based M3D integration can offer >ten-folds higher integration density compared with through-silicon-via (TSV)-based 3D integration, and >150% integration density improvement with respect to conventional M3D integration. Therefore, 2D materials provide a significantly better platform, with respect to bulk materials (such as Si, Ge, GaN), for realizing ultra-high-density M3D-ICs of ultimate thinness for next-generation electronics.

High Performance and Highly Robust AlN/GaN HEMTs for Millimeter-Wave Operation

Abstract: We report on a 3 nm AlN/GaN HEMT technology for millimeter-wave applications. Electrical characteristics for a 110 nm gate length show a maximum drain current density of 1.2 A/mm, an excellent electron confinement with a low leakage current below $10~\mu \text{A}$ /mm, a high breakdown voltage and a FT/Fmax of 63/300 GHz at a drain voltage of 20V. Despite residual trapping effects, state of the art large signal characteristics at 40 GHz and 94 GHz are achieved. For instance, an outstanding power added efficiency of 65% has been reached at VDS = 10V in pulsed mode at 40 GHz. Also, an output power density of 8.3 W/mm at VDS = 40V is obtained associated to a power added efficiency of 50%. At 94 GHz, a record CW output power density for Ga-polar GaN transistors has been reached with 4 W/mm. Additionally, room temperature preliminary robustness assessment at 40 GHz has been performed at VDS = 20V. 24 hours RF monitoring showed no degradation during and after the test.

Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention

Abstract: Achieving a reliable multi-level operation in resistive random access memory (RRAM) arrays is currently a challenging task due to several threats like the post-algorithm instability occurring after the levels placement, the limited endurance, and the poor data retention capabilities at high temperature. In this paper, we introduced a multi-level variation of the state-of-the-art incremental step pulse with verify algorithm (M-ISPVA) to improve the stability of the low resistive state levels. This algorithm introduces for the first time the proper combination of current compliance control and program/verify paradigms. The validation of the algorithm for forming and set operations has been performed on 4-kbit RRAM arrays. In addition, we assessed the endurance and the high temperature multi-level retention capabilities after the algorithm application proving a 1 k switching cycles stability and a ten years retention target with temperatures below 100 °C.

On the Characterization and Separation of Trapping and Ferroelectric Behavior in HfZrO FET

Abstract: $N$ -channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope under certain conditions. Possible origins of ${I} _{D}$ – ${V} _{G}$ hysteresis, the hysteresis versus subthreshold slope tradeoff, dependence on the bias voltage and temperature and the competition between trapping and FE behavior are reported and discussed. A band of active traps in the FE layer responsible for charge trapping during device operation is characterized. Transient ${I} _{D}$ – ${V} _{G}$ measurements are introduced to facilitate differentiating between trapping and FE behavior during subthreshold slope measurements.

High Performance ${\beta}$ -Ga 2 O 3 Nano-Membrane Field Effect Transistors on a High Thermal Conductivity Diamond Substrate

Abstract: To suppress severe self-heating under high power density, we herein demonstrate top-gate nano-membrane ${\beta }$ -gallium oxide ( ${\beta }$ -Ga2O3) field effect transistors on a high thermal conductivity diamond substrate. The devices exhibit enhanced performance, with a record high maximum drain current of 980 mA/mm for top-gate ${\beta }$ -Ga2O3 field effect transistors and 60% less temperature increase from reduced self-heating, compared to the device on a sapphire substrate operating under identical power density. With improved heat dissipation, ${\beta }$ -Ga2O3 field effect transistors on a diamond substrate are validated using an ultrafast high-resolution thermoreflectance imaging technique, Raman thermography, and thermal simulations.

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

Abstract: Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet’s extreme conditions of ~460°C, ~9.3 MPa (~92 Earth atmospheres) chemically reactive environment. Here, we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost threefold and were accomplished using prototype SiC JFET chips of more than sevenfold increased complexity. The demonstrated advancement marks a significant step toward realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.

2-Bit/Cell Operation of Hf 0.5 Zr 0.5 O 2 Based FeFET Memory Devices for NAND Applications

Abstract: The multilevel memory performances of ferroelectric field effect transistor (FeFET) with Hf0.5Zr0.5O2 (HZO) ferroelectric thin film are investigated. First, similar retention characteristics are observed for intermediate and saturated polarization states of HZO ferroelectric thin film, which enables memories for multi-bit data storage. And then, 2-bit/cell operation of HZO-based FeFET is demonstrated utilizing two NAND architecture compatible write schemes of varying program pulse amplitude and width. Low cycle-to-cycle variability, long retention to extrapolation of 10 years at 85°C, and endurance of 500 cycles are achieved for the both schemes. Moreover, the mechanism for multilevel memory operations of the FeFET is illustrated based on the polarization switching dynamics of HZO ferroelectric thin film.

Design of Power- and Variability-Aware Nonvolatile RRAM Cell Using Memristor as a Memory Element

Abstract: A 3 CNFETs and 2 memristors-based half-select disturbance free 3T2R resistive RAM (RRAM) cell is proposed in this paper. While the two memristors act as the nonvolatile memory elements, CNFETs are employed as high-performance switches. The proposed cell is capable of implementing bit-interleaving architecture and various error correction coding (ECC) schemes can be applied to mitigate soft-errors. The 3T2R cell has been compared with the standard 6T SRAM (S6T) and 2T2R cells. At a supply voltage of 2 V, the 3T2R cell exhibits $7.24\times $ shorter write delay ( ${T} _{\text {WA}}$ ) and $2.89\times $ lower variability in ${T} _{\text {WA}}$ than that of 2T2R. Moreover, it exhibits $5.08\times /4.33\times $ lower variability in ${T} _{\text {RA}}$ and $1.46\times 10^{7}\times /2.07\times $ lower hold power ( ${H} _{\text {PWR}}$ ) dissipation than that of S6T/ 2T2R at ${V} _{\text {DD}} = 2$ V. In addition, it exhibits tolerance to variations in ${V} _{\text {th}}$ of memristor while being immune to resistance-state drift and random telegraph noise (RTN)-induced instabilities during the read operation. The vastly superior characteristics of CNFET devices over MOSFETs, in combination with memristor technology, leads to such appreciable improvement in design metrics of the proposed design.

A High Performance Operational Amplifier Using Coplanar Dual Gate a-IGZO TFTs

Abstract: We fabricate an operational amplifier (op-amp) composed with the coplanar amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). The circuit consisted of 19-TFTs and designed on a glass substrate in both dual gate (DG) and single gate (SG) structure for performance evaluation. Having the yield of a total voltage gain ( $A_{v}$ ) of 23.5 dB, a cutoff frequency ( $f_{c}$ ) of 500 kHz, a unit gain frequency ( $f_{\mathrm{ ug}}$ ) of 2.37 MHz, gain-bandwidth product (GBWP) of 7500 kHz, a slew rate (up/down) of (2.1/1.2) V/ $\mu \text{s}$ , and a phase margin (PM) of 102° at a supply voltage of ±10 V, the fabricated DG TFT op-amp demonstrates good performance among all a-IGZO-based literature.

Operation Up to 500 °C of Al 0.85 Ga 0.15 N/Al 0.7 Ga 0.3 N High Electron Mobility Transistors

Abstract: AlGaN channel high electron mobility transistors (HEMTs) are the potential next step after GaN channel HEMTs, as the high aluminum content channel leads to an ultra-wide bandgap, higher breakdown field, and improved high temperature operation. Al0.85Ga0.15N/Al0.7Ga0.3N (85/70) HEMTs were operated up to 500 °C in ambient causing only 58% reduction of dc current relative to 25 °C measurement. The low gate leakage current contributed to high gate voltage operation up to +10 V under Vds = 10 V, with $\text{I}_{\mathrm{ ON}}/\text{I}_{\mathrm{ OFF}}$ ratios of $> 2 \times 10^{11}$ and 3 $\times \,\,10^{6}$ at 25 and 500 °C, respectively. Gate-lag measurements at 100 kHz and 10% duty cycle were ideal and only slight loss of pulsed current at high gate voltages was observed. Low interfacial defects give rise to high quality pulsed characteristics and a low subthreshold swing value of 80 mV/dec at room temperature. Herein is an analysis of AlGaN-channel HEMTs and their potential future for high power and high temperature applications.

Impact of Self-Heating Effect on Transistor Characterization and Reliability Issues in Sub-10 nm Technology Nodes

Abstract: FinFET and fully depleted silicon-on-insulator (FDSOI) structures could further improve transistor’s performance and, however, also introduce some new problems, especially the increasingly severer self-heating effect (SHE). In this paper, by utilizing the ultra-fast sub-1 ns measurement technique, I–V characteristics of FinFETs and FDSOI devices at different switch speeds are obtained. Furthermore, dynamic SHE phenomena as well as the time-resolved channel temperature change during transistor’s switch on and off are able to be experimentally observed. And, more accurate device parameters like ballistic transport efficiency are extracted by the ultra-fast measurements. Moreover, it is experimentally confirmed that several nanoseconds are required to heat up the channel of transistors by the direct electrical characterization and, therefore, in sub-10 nm devices, SHE might be alleviated under high frequency/speed operations.

Impact of the Stacking Order of HfO x and AlO x Dielectric Films on RRAM Switching Mechanisms to Behave Digital Resistive Switching and Synaptic Characteristics

Abstract: Resistive random access memory (RRAM) devices with analog resistive switching are expected to be beneficial for neuromorphic applications, and consecutive voltage sweeps or pulses can be applied to change the device conductance and behave synaptic characteristics. In this paper, RRAM devices with a reverse stacking order of 6-nm-thick HfO x and 2-nm-thick AlO x dielectric films were fabricated. The device with TiN/Ti/AlO x /HfO x /TiN stacked layers exhibited digital resistive switching, while the other device with TiN/Ti/HfO x /AlO x /TiN stacked layers could demonstrate synaptic characteristics that were analog set and reset processes under consecutive positive and negative voltage sweeps or a train of potentiation and depression pulses. Moreover, this device could also implement synaptic learning rules, spike-timing-dependent plasticity (STDP). Varying temperature measurements and linear fittings of the measured data were conducted to analyze current conduction mechanisms. As a result, the variation of resistive switching behavior between these two devices is attributed to the varying effectiveness of the oxygen scavenging ability of the Ti layer when put into contact with either AlO x or HfO x . Moreover, AlO x functioned as a diffusion limiting layer (DLL) in the device with TiN/Ti/HfO x /AlO x /TiN stacked layers, and gradual modulation of the production and annihilation of oxygen vacancies is the cause of synaptic characteristics.

Operation Scheme of Multi-Layer Neural Networks Using NAND Flash Memory as High-Density Synaptic Devices

Abstract: We propose a designing of multi-layer neural networks using 2D NAND flash memory cell as a high-density and reliable synaptic device. Our operation scheme eliminates the waste of NAND flash cells and allows analogue input values. A 3-layer perceptron network with 40,545 synapses is trained on a MNIST database set using an adaptive weight update method for hardware-based multi-layer neural networks. The conductance response of NAND flash cells is measured and it is shown that the unidirectional conductance response is suitable for implementing multi-layer neural networks using NAND flash memory cells as synaptic devices. Using an online-learning, we obtained higher learning accuracy with NAND synaptic devices compared to that with a memristor-based synapse regardless of weight update methods. Using an adaptive weight update method based on a unidirectional conductance response, we obtained a 94.19% learning accuracy with NAND synaptic devices. This accuracy is comparable to 94.69% obtained by synapses based on the ideal perfect linear device. Therefore, NAND flash memory which is mature technology and has great advantage in cell density can be a promising synaptic device for implementing high-density multi-layer neural networks.

Effect of Hot Electron Stress on AlGaN/GaN HEMTs of Hydrogen Poisoning

Abstract: We have investigated the effect of hot electron stress on the electrical properties of AlGaN/GaN high electron mobility transistors (HEMTs) of hydrogen poisoning. The AlGaN/GaN HEMTs were biased at the semi-on state, and they suffered from the hot electron stress. The devices of hydrogen poisoning were degraded, while there is almost no degradation for the fresh ones. The hot electron stress leads to the significantly positive shift of threshold voltage and the notable decrease of drain-to-source current for the AlGaN/GaN HEMTs of hydrogen poisoning. For the AlGaN/GaN HEMTs of hydrogen poisoning, the trap density increases by about one order of magnitude after the hot electron stress experiment. The physical mechanism can be attributed to electrically active traps due to the dehydrogenation of passivated point defects at AlGaN surface, AlGaN barrier layer, and heterostructure interface. The results of this paper may be useful in the design and application of AlGaN/GaN HEMTs.

Improving the Scalability of SOI-Based Tunnel FETs Using Ground Plane in Buried Oxide

Abstract: Tunnel field-effect transistors (TFETs) are known to exhibit degraded electrical characteristics at smaller channel lengths, primarily due to direct source-to-drain band-to-band tunneling (BTBT). In this paper, we propose a technique to suppress direct source-to-drain BTBT by increasing the effective distance between the source and the drain. We propose to add a ground plane (GP) in the buried oxide of a silicon-on-insulator (SOI) TFET which depletes the drain and increases the effective source-to-drain distance. Using 2-D device simulations it is shown that the introduction of the ground plane is effective in reducing OFF-state current and ambipolar current, as well as, in improving the average subthreshold swing for the small channel length SOI-TFETs. Additionally, the addition of GP is helpful in ameliorating the short-channel effects, such as drain-induced barrier lowering and threshold voltage roll-off.

Process Dependence of Soft Errors Induced by Alpha Particles, Heavy Ions, and High Energy Neutrons on Flip Flops in FDSOI

Abstract: Soft-error tolerance depending on threshold voltage of transistors was evaluated by $\alpha $ -particle, heavy-ion, and neutron irradiation. Three chips were fabricated, one embeds low-threshold general-purpose (GP) transistors and the others embed high-threshold low-power (LP) transistors in a 65 nm fully depleted silicon on insulator (FDSOI) process. There were a few errors on LPDFFs (DFFs with LP transistors). Error probability (EP) of LPDFFs was 99.88% smaller than that of GPDFFs (DFFs with GP transistors) by $\alpha $ particles. Average cross sections (CSs) of LPDFFs by heavy ions were 50% smaller than those of GPDFFs. Average soft-error rates (SERs) of LPDFFs by neutrons were 68% smaller than those of GPDFFs. 3-D device simulations revealed that CSs of the LP and GP transistors are changed by fitting methods using the work function of the gate material and doping concentration of the substrate under the BOX layer. The difference is due to the number of carriers in diffusion and silicon thickness of the raised layer above drain and source terminals.

Ferroelectric Field Effect Transistors Based on PZT and IGZO

Abstract: Ferroelectric field effect transistors (FeFETs) based on lead zirconate titanate (PZT) ferroelectric material and amorphous-indium-gallium-zinc oxide (a-IGZO) were developed and characterized. The PZT material was processed by a sol-gel method and then used as ferroelectric gate. The a-IGZO thin films, having the role of channel semiconductor, were deposited by radio-frequency magnetron sputtering, at a temperature of ~50°C. Characteristics of a typical field effect transistor with SiO2 gate insulator, grown on highly doped silicon, and of the PZT-based FeFET were compared. It was proven that the FeFETs had promising performances in terms of Ion/Ioff ratio (i.e., 106) and IDS retention behavior.

A New Dual-Direction SCR With High Holding Voltage and Low Dynamic Resistance for 5 V Application

Abstract: Dual-directional silicon-controlled rectifiers (DDSCRs), which provide both positive and negative electrostatic discharge (ESD) surge paths, are ESD protection devices with an excellent area efficiency. However, DDSCRs have a low holding voltage for use in 5 V-class applications, with a relatively high on-state resistance because of the elongated ESD surge path compared to unidirectional SCRs. In this paper, we propose a novel DDSCR with a higher holding voltage and a better ESD tolerance than conventional low-triggering DDSCRs (LTDDSCRs), realized by operating two additional parasitic bipolar transistors. The proposed ESD protection device was developed through a 0.18- $\mu \text{m}$ CMOS process, and a timeline pulse system was used to verify its properties. The measurement results show that the proposed ESD protection device exhibits an improved tolerance and a high holding voltage and is expected to be reliable in 5 V-class applications

On the Physical Mechanism of Transient Negative Capacitance Effect in Deep Subthreshold Region

Abstract: We have investigated the physical mechanism of steep subthreshold slope (SS) in ferroelectric FET (FeFET) based on a dynamic ferroelectric (FE) model without traversing the negative capacitance (NC) region of the S-shaped polarization-voltage predicted by Landau theory. The dynamic FE model is applied to an FE-dielectric (FE-DE) series capacitor as well as FeFET after calibration and verification by transient measurement of an FE-HfO2 capacitor. By investigating current through the FE-DE series capacitor and the gate capacitor of FeFET, we find that incomplete screening of spontaneous polarization charge results in transient NC and sub-60 mV/dec SS. Also, it should be noted that, for FeFET, small depletion layer capacitance has an important role to cause strong depolarization effect and thus steep SS. Moreover, reverse drain induced barrier lowering happens even with this FE model. The model presented in this paper provides a reasonable interpretation for the previously reported steep SS of NC FETs.

Dynamic Switching Characteristics of 1 A Forward Current $\boldsymbol{\beta}$ -Ga 2 O 3 Rectifiers

Abstract: An inductive load test circuit was used to measure the switching performance of fieldplated edge-terminated Schottky rectifiers with a reverse breakdown voltage of 760 V (0.1 cm diameter, $7.85 \times 10.3 {\mathrm {cm}}^{2}$ area) and an absolute forward current of 1 A on 8 m thick epitaxial $\beta$ -Ga2O3 drift layers. The recovery characteristics for these vertical geometry $\beta$ -Ga2O3 Schottky rectifiers switching from forward current of 1 A to reverse off-state voltage of −300 V showed a recovery time (trr) of 64 ns. There was no significant temperature dependence of trr up to 150 °C.

Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs

Abstract: Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of $2.4 ~\text{mS}/\mu\text{m}$ , high on-current, and off-current below $1 ~\text{nA}/\mu\text{m}$ . An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance.

Oxide TFT Rectifiers on Flexible Substrates Operating at NFC Frequency Range

Abstract: This paper presents the experimental characterization of different rectifier circuits using indium–gallium–zinc-oxide thin-film transistor technologies either at NFC or a high frequency range (13.56 MHz) of RFID. These circuits include a single ended rectifier, its differential counterpart, a bridge rectifier, and a cross-coupled full wave rectifier. Diodes were implemented with transistors using conventional processing steps, without requiring short channel devices ( $L =15\,\,\mu \text{m}$ ). Hence, there is no need for either extra masks or processing steps unlike the Schottky diode-based implementation. These circuits were fabricated on a PEN substrate with an annealing temperature not exceeding 180 °C. This paper finds a direct application in flexible low-cost RFID tags since they enable integration of the required electronics to implement tags with the same fabrication steps.

First Demonstration of Short-Circuit Capability for a 1.2 kV SiC SWITCH-MOS

Abstract: In this paper, the authors report a unique short circuit failure mechanism of a 1.2 kV silicon carbide (SiC) SBD-wall-integrated trench MOSFET (SWITCH-MOS), using numerical simulations and experimental validation. When the Schottky barrier height in the SWITCH-MOS was set at 1.20 eV, the short-circuit withstand time was roughly half that of a conventional SiC trench MOSFET. This is because, in the SWITCH-MOS, the thermionic-field emission electrons passing through the embedded SBD continue flowing into the high electric field in the n− drift region, even after the gate is turned off. This causes heat generation in the device, resulting in thermal runaway. Using a novel methodology for improving the short-circuit capability, it was confirmed that metal with a high Schottky barrier height of 1.75 eV can significantly improve the SWITCH-MOS short-circuit capability, making it comparable to that of conventional SiC trench MOSFETs, and suggesting SWITCH-MOS devices may be superior power devices for use in high frequency inverters.

Investigation of Self-Heating Effect on DC and RF Performances in AlGaN/GaN HEMTs on CVD-Diamond

Abstract: -We have investigated the self-heating effect on DC and RF performances of identically fabricated AlGaN/GaN HEMTs on CVD-Diamond (GaN/Dia) and Si (GaN/Si) substrates. Self-heating induced device performances were extracted at different values drain bias voltage ( $V_{D}$ ) and dissipated DC power density ( $P_{D}$ ) in continuous wave (CW) operating condition. The effect of self-heating was observed much lesser in GaN/Dia HEMTs than GaN/Si HEMTs in terms of $I_{\mathrm{D}}$ , $I_{\mathrm{G}}$ , $g_{\mathrm{m}}$ , $f_{\mathrm{T}}$ and $f_{\mathrm{max}}$ reduction. Increased channel temperature caused by joule heating at high $P_{\mathrm{D}}$ reduces the 2-DEG carrier mobility in the channel of the device. This behaviour was also confirmed by TCAD simulation which showed ~3.9-times lower rising rate of maximum channel temperature and lowers thermal resistance ( $R_{\mathrm{th}}$ ) in GaN/Dia HEMTs than GaN/Si HEMTs. Small signal measurements and equivalent circuit parameter extraction were done to analyze the variation in performance of the devices. Our investigation reveals that the GaN/Dia HEMT is a promising candidate for high power density CW operation without significant reduction in electrical performance in a large drain bias range.

High Performance Single Crystalline Diamond Normally-Off Field Effect Transistors

Abstract: High performance normally-off hydrogen-terminated diamond (H-diamond) MOSFETs were fabricated on single crystalline diamond grown in our lab. The device with 2- $\mu \text{m}$ gate length shows threshold voltage of −1.0 V, and a drain current of 51.6 mA/mm at $V_{\mathrm{ GS}}= {V}_{\mathrm{ DS}} = -4.5$ V and an on-resistance of $65.39~ \Omega \cdot $ mm. The transconductance keeps increasing when $\text{V}_{\mathrm{ GS}}$ shifts from $\text{V}_{\mathrm{ TH}}$ toward more negative direction, and reaches the record high value of 20 mS/mm at $\text{V}_{\mathrm{ GS}}$ of −4.5 V, which benefitted from the almost constant mobility of the holes in the gate voltage range of −4 V $ V. The critical device process to realize these low on-resistance normally-off MOSFETs consists of 2-min UV ozone treatment of the H-diamond surface and thermal oxidation of aluminum film in the air to form an alumina gate dielectric.

Effect of Grain Boundary Protrusion on Electrical Performance of Low Temperature Polycrystalline Silicon Thin Film Transistors

Abstract: We studied the impact of grain boundary (GB) protrusion on the electrical properties of low temperature polycrystalline silicon thin film transistors. The analysis of atomic force microscopy and transmission electron microscopy images indicate the grain size of ~350 nm and a protrusion height of ~35 nm. The transfer and output characteristics are well fitted by technology computer-aided design using two different density of states for poly-Si grain and GB, respectively. From 2-D contour mapping, a drastic reduction of hole concentration ( ${\sim }5\times 10^{16}\,\,{\mathrm{cm}}^{-3}$ ) at GB protrusion site was obtained as compared to the grain ( ${\sim }3\times 10^{18}\,\,{\mathrm{cm}}^{-3} $ ). Trapping concentration at GB is much higher, which leads to the reduction in the mobility.

Comprehensive Analysis and Optimal Design of Ge/GeSn/Ge p-n-p Infrared Heterojunction Phototransistors

Abstract: We present a comprehensive analysis of practical p-n-p Ge/Ge1– x Sn x /Ge heterojunction phototransistors (HPTs) for design optimization for efficient infrared detection. Our design includes a Ge1– x Sn x narrow-bandgap semiconductor as the active layer in the base layer, enabling extension of the photodetection range from near-infrared to mid-infrared to perform wide-range infrared detection. We calculate the current gain, signal-to-noise ratio (SNR), and optical responsivity and investigate their dependences on the structural parameters to optimize the proposed Ge1– x Sn x p-n-p HPTs. The results show that the SNR is strongly dependent on the operation frequency and that the introduction of Sn into the base layer can improve the SNR in the high-frequency region. In addition, the current gain strongly depends on the Sn content in the Ge1– x Sn x base layer, and a Sn content of 6%–9% maximizes the optical responsivity achievable in the infrared range. These results provide useful guidelines for designing and optimizing practical p-n-p Ge1– x Sn x HPTs for high-performance infrared photodetection.

Proton Conductor Gated Synaptic Transistor Based on Transparent IGZO for Realizing Electrical and UV Light Stimulus

Abstract: Synaptic transistors mimicking the biological synapse’s short term plasticity and short-term memory property were demonstrated using the amorphous indium–gallium–zinc oxide channel in combination with the nanogranular SiO2 as the gate oxide. The lowest energy consumption was 1.08 pJ per pulse activity and the operating voltage was within 100 mV. The device’s plasticity and memory characteristics can be explained by the movement of protons in the insulating layer. The proton relaxation was revealed by two ways of dual sweeping: continuous and discontinuous sweepings. We observed that the excitatory postsynaptic current (EPSC) rose as the voltage decreased anomaly during the backward sweeping process. In the electrical stimulus, both the short-term potentiation and depression were observed for this proposed device. The amplitude of the EPSC changed with the pulse number following a saturating exponential function. For the electrical stimulus under constant illumination, the UV light wavelength, intensity and duration time were found to have little effect on the paired pulse facilitation. While in the light stimulus, the light frequency promoted the paired pulse facilitation and had more effect on the synapse’s plasticity than the other light pulse parameters including intensity, numbers and width.