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JournalISSN: 1943-0582

IEEE Solid-State Circuits Magazine 

Institute of Electrical and Electronics Engineers
About: IEEE Solid-State Circuits Magazine is an academic journal published by Institute of Electrical and Electronics Engineers. The journal publishes majorly in the area(s): Electronic circuit & Event (particle physics). It has an ISSN identifier of 1943-0582. Over the lifetime, 611 publications have been published receiving 5052 citations. The journal is also known as: Institute of Electrical and Electronics Engineers solid state circuits magazine & Solid state circuits magazine.


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Journal ArticleDOI
TL;DR: The typical power requirements of some current portable devices, including a body sensor network, are shown in Figure 1.
Abstract: Wireless sensor nodes (WSNs) are employed today in many different application areas, ranging from health and lifestyle to automotive, smart building, predictive maintenance (e.g., of machines and infrastructure), and active RFID tags. Currently these devices have limited lifetimes, however, since they require significant operating power. The typical power requirements of some current portable devices, including a body sensor network, are shown in Figure 1.

611 citations

Journal ArticleDOI
TL;DR: This tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STTMRAM), phase-change randomAccess memory (PCRAM), and resistive random accessMemory (RRAM).
Abstract: This tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STTMRAM), phase-change random access memory (PCRAM), and resistive random access memory (RRAM). Emerging NVM cell characteristics are summarized, and device-level engineering trends are discussed. Emerging NVM array architectures are introduced, including the onetransistor?one-resistor (1T1R) array and the cross-point array with selectors. Design challenges such as scaling the write current and minimizing the sneak path current in cross-point array are analyzed. Recent progress on megabit-to gigabit-level prototype chip demonstrations is summarized. Finally, the prospective applications of emerging NVM are discussed, ranging from the last-level cache to the storage-class memory in the memory hierarchy. Topics of three-dimensional (3D) integration and radiation-hard NVM are discussed. Novel applications beyond the conventional memory applications are also surveyed, including physical unclonable function for hardware security, reconfigurable routing switch for field-programmable gate array (FPGA), logic-in-memory and nonvolatile cache/register/flip-flop for nonvolatile processor, and synaptic device for neuro-inspired computing.

391 citations

Journal ArticleDOI
TL;DR: The StrongARM latch topology finds wide usage as a sense amplifier, a comparator, or simply a robust latch with high sensitivity as mentioned in this paper, and it consumes zero static power, produces rail-to-rail outputs, and its input-referred offset arises from primarily one differential pair.
Abstract: i»?The StrongARM latch topology finds wide usage as a sense amplifier, a comparator, or simply a robust latch with high sensitivity. The term “StrongARM” commemorates the use of this circuit in Digital Equipment Corporation’s StrongARM microprocessor [1], but the basic structure was originally introduced by Toshiba’s Kobayashi et al. [2]. The StrongARM latch has become popular for three reasons: 1) it consumes zero static power, 2) it directly produces rail-to-rail outputs, and 3) its input-referred offset arises from primarily one differential pair. In this column, we study the circuit and its properties.

291 citations

Journal ArticleDOI
TL;DR: An overview of the fundamentals of IMC is provided to better explain these challenges and then promising paths forward among the wide range of emerging research are identified.
Abstract: High-dimensionality matrix-vector multiplication (MVM) is a dominant kernel in signal-processing and machine-learning computations that are being deployed in a range of energy- and throughput-constrained applications. In-memory computing (IMC) exploits the structural alignment between a dense 2D array of bit cells and the dataflow in MVM, enabling opportunities to address computational energy and throughput. Recent prototypes have demonstrated the potential for 10 t benefits in both metrics. However, fitting computation within an array of constrained bit-cell circuits imposes a number of challenges, including the need for analog computation, efficient interfacing with conventional digital accelerators (enabling the required programmability), and efficient virtualization of the hardware to map software. This article provides an overview of the fundamentals of IMC to better explain these challenges and then identifies promising paths forward among the wide range of emerging research.

189 citations

Journal ArticleDOI
TL;DR: The same foundries and processes that were developed to build transistors are being repurposed to build chips that can generate, detect, modulate, and otherwise manipulate light as discussed by the authors.
Abstract: Something very surprising has been happening in photonics recently: the same foundries and processes that were developed to build transistors are being repurposed to build chips that can generate, detect, modulate, and otherwise manipulate light. This is pretty counterintuitive, since the electronics industry spends billions of dollars to develop tools, processes, and facilities that lend themselves to building the very best transistors without any thought about how to make these processes compatible with photonics (with the obvious exception of the processes designed to make CMOS and CCD camera chips).

143 citations

Performance
Metrics
No. of papers from the Journal in previous years
YearPapers
2023139
2022180
202143
202030
201935
201825