Showing papers in "IEEE Transactions on Advanced Packaging in 2004"

SOP: what is it and why? A new microsystem-integration technology paradigm-Moore's law for system integration of miniaturized convergent systems of the next decade

Abstract: In the past, microsystems packaging played two roles: 1) it provided I/O connections to and from integrated circuits (ICs) or wafer-level packaging (WLP), and 2) it interconnected both active and passive components on system level boards, referred to as systems packaging. Both were accomplished by interconnections or multilayer wiring at the package or board level. More recently, the IC devices have begun to integrate not only more and more transistors, but also active and passive components on an individual chip, leading the community to believe that someday there may be a single-chip complete system, referred to as system-on-chip (SOC). This can be called horizontal or two-dimensional (2-D) integration of IC blocks in a single-chip toward end-product systems. The community began to realize, however, that such an approach presents fundamental, engineering, and investment limits, as well as computing and communication limits for wireless and wired systems over the long run. This led to 3-D packaging approaches, often referred to as system-in-package (SIP). The SIP, while providing major opportunities in both miniaturization and integration for advanced and portable electronic products, is a subsystem, limited by the CMOS process just like the SOC. Some existing and emerging applications, however, include sensors, memory modules and embedded processors with DRAMs. More recent 3-D solutions, which incorporate stacked package approaches, offer solutions toward faster time-to-market and business impediments that have plagued MCM deployment for the past decade. There is a new emerging concept called system-on-package (SOP). With SOP, the package, not the board, is the system. As such, SOP is beginning to address the shortcomings of both SOC and SIP, as well as traditional packaging which is bulky, costly, and lower in performance and reliability than ICs, in two ways: 1) It uses CMOS-based silicon for what it is good for, namely, for transistor integration, and the package, for what it is good for, namely, RF, optical, and digital integration by means of IC-package-system codesign. The SOP package, therefore, overcomes both the computing limitations and integration limitations of SOC, SIP, MCM, and traditional system packaging. It does this by having global wiring as well as RF, digital, and optical component integration in the package, not in the chip. The SOP, therefore, includes both active and passive components in thin-film form, in contrast with indiscrete or thick-film form, including embedded digital, RF, and optical components, and functions in a microminiaturized package or board.

Power distribution networks for system-on-package: status and challenges

Abstract: The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

Recent advances in flip-chip underfill: materials, process, and reliability

Abstract: In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.

Electromagnetic interference (EMI) of system-on-package (SOP)

Abstract: Electromagnetic interference (EMI) issues are expected to be crucial for next-generation system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits. Ordinarily in SOPs, high-performance digital LSIs are sources of EMI, while RF and analog circuits are affected by EMI (victims). This paper describes the following aspects of EMI in SOPs: 1) die/package-level EMI; 2) substrate-level EMI; 3) electromagnetic modeling and simulation; and 4) near electromagnetic field measurement. First, LSI designs are discussed with regard to radiated emission. The signal-return path loop and switching current in the power/ground line are inherent sources of EMI. The EMI of substrate, which work as coupling paths or unwanted antennas, is described. Maintaining the return current path is an important aspect of substrate design for suppressing EMI and for maintaining signal integrity (SI). In addition, isolating and suppressing the resonance of the DC power bus in a substrate is another important design aspect for EMI and for power integrity (PI). Various electromagnetic simulation methodologies are introduced as indispensable design tools for achieving high-performance SOPs without EMI problems. Measurement techniques for near electric and magnetic fields are explained, as they are necessary to confirm the appropriateness of designs and to investigate the causes of EMI problems. This paper is expected to be useful in the design and development of SOPs that take EMI into consideration.

The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

Abstract: From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

3-D-integrated RF and millimeter-wave functions and modules using liquid crystal polymer (LCP) system-on-package technology

Abstract: Electronics packaging evolution involves system, technology, and material considerations. In this paper, we present a novel three-dimensional (3-D) integration approach for system-on-package (SOP)-based solutions for wireless communication applications. This concept is proposed for the 3-D integration of RF and millimeter (mm) wave embedded functions in front-end modules by means of stacking substrates using liquid crystal polymer (LCP) multilayer and /spl mu/BGA technologies. Characterization and modeling of high-Q RF inductors using LCP is described. A single-input-single-output (SISO) dual-band filter operating at ISM 2.4-2.5 GHz and UNII 5.15-5.85 GHz frequency bands, two dual-polarization 2/spl times/1 antenna arrays operating at 14 and 35 GHz, and a WLAN IEEE 802.11a-compliant compact module (volume of 75/spl times/35/spl times/0.2 mm/sup 3/) have been fabricated on LCP substrate, showing the great potential of the SOP approach for 3-D-integrated RF and mm wave functions and modules.

Design of compact stacked-patch antennas in LTCC multilayer packaging modules for wireless applications

Abstract: A simple procedure for the design of compact stacked-patch antennas is presented based on LTCC multilayer packaging technology. The advantage of this topology is that only one parameter, i.e., the substrate thickness (or equivalently the number of LTCC layers), needs to be adjusted in order to achieve an optimized bandwidth performance. The validity of the new design strategy is verified through applying it to practical compact antenna design for several wireless communication bands, including ISM 2.4-GHz band, IEEE 802.11a 5.8-GHz, and LMDS 28-GHz band. It is shown that a 10-dB return-loss bandwidth of 7% can be achieved for the LTCC (/spl epsiv//sub r/=5.6) multilayer structure with a thickness of less than 0.03 wavelengths, which can be realized using a different number of laminated layers for different frequencies (e.g., three layers for the 28-GHz band).

Low-cost test of embedded RF/analog/mixed-signal circuits in SOPs

Abstract: Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages (SOPs) very difficult. Testing packages with multigigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40% of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an "intelligent" manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented.

A coupled efficient and systematic full-wave time-domain macromodeling and circuit Simulation method for signal integrity analysis of high-speed interconnects

Abstract: This paper presents an accurate and systematic approach for analysis of the signal integrity of the high-speed interconnects, which couples the full-wave finite difference time domain (FDTD) method with scattering (S) parameter based macromodeling by using rational function approximation and the circuit simulator. Firstly, the full-wave FDTD method is applied to characterize the interconnect subsystems, which is dedicated to extract the S parameters of the subnetwork consisting of interconnects with fairly complex geometry. Once the frequency-domain discrete data of the S parameters of the interconnect subnetwork is constructed, the rational function approximation is carried out to establish the macromodel of the interconnect subnetwork by employing the vector fitting method, which provides a more robust and accurate solution for the overall problem. Finally, the analysis of the signal integrity of the hybrid circuit can be fulfilled by using the S parameters based macromodel synthesis and simulation program with integrated circuits emphasis (SPICE) circuit simulator. Numerical experiments demonstrate that the proposed approach is accurate and efficient to address the hybrid electromagnetic (interconnect part) and circuit problems, in which the electromagnetic field effects are fully considered and the strength of SPICE circuit simulator is also exploited.

Statistical signal integrity analysis and diagnosis methodology for high-speed systems

Abstract: This paper discusses an efficient statistical analysis methodology for system-level signal integrity analysis. In the proposed method, statistical variations of the design and operational parameters are mapped to system performance through simulations based on orthogonal Taguchi arrays. Using the sensitivity functions derived from these simulations, statistical distributions of the performance measures are computed. The sensitivity functions and probability distributions of the design parameters are utilized as a diagnosis tool to estimate the design parameters of a system for a given measured performance. The statistical methodology is applied for design space exploration to improve system performance. For demonstrating the concept, a source synchronous memory bus and a peripheral input-output (I/O) bus have been analyzed under design and operational variations.

Comparison between epi-down and epi-up bonded high-power single-mode 980-nm semiconductor lasers

Abstract: Epi-down and epi-up bonded high-power single-mode 980-nm lasers have been studied in terms of bonding process, thermal behavior, optical performances, and long-term laser reliability. We demonstrated that epi-down bonding can offer lower thermal resistance and improved optical performance without degrading the long-term laser reliability. An optical power of 630 mW was obtained for the first time from an epi-down bonded 980-nm pump module. Our studies have shown that epi-down bonding of single-mode 980-nm lasers can reduce junction temperature and thermal resistance by up to 30%. Experimental measurements showed over 20% in thermal rollover power improvement and over 25% reduction in wavelength shift versus current in epi-down mounted lasers compared to epi-up mounted lasers. Lifetime test over 14 000 h at 500 mA and 80/spl deg/C of the epi-down bonded lasers is reported for the first time.

Materials and processes for implementing high-temperature liquid interconnects

Abstract: This paper describes the results of a study investigating liquid solder joints at elevated temperatures (up to 200/spl deg/C). The reactions of eutectic 52In/48Sn solder, which melts at 118/spl deg/C, with various metal barrier layers is presented. The main emphasis of the research was to find a combination of solder and substrate metallization which has good adhesion strength but also remains stable during temperature cycling and high-temperature storage when the solder is molten. Intermetallic growth rates and solder-substrate adhesion strength have been measured for a range of potential barrier layers including Ni, Cr, Pt, Ti, V, Nb, Ta, and W. Of these, only Nb was found to have acceptable properties for a high-temperature barrier layer to In/Sn solder. Other aspects of liquid solder interconnections that have been studied include stability of the molten solder-underfill interface under electrical bias and retention of electrical contact during vibration and phase change. Plastic ball grid array (PBGA) devices have been assembled with Nb barrier layers and liquid solder joints and their reliability during temperature cycling (-20/spl deg/C to +180/spl deg/C) has been compared to PBGA joints with Sn95.5/Ag4/Cu0.5 solder balls.

SOP integration and codesign of antennas

Abstract: The successful deployment of wireless systems requires the integration of small, cost-effective antennas while preserving a reasonable electrical performance in the required bandwidth. This paper begins with a short overview of the most important antenna characteristics, and then uses these to describe the minimum requirements and fundamental performance-size limits for electrically small integrated antennas. The performance-size tradeoff is further illustrated by the design of a planar integrated antenna for WLAN. Codesign guidelines are given to avoid parasitic coupling between the integrated antenna and RF circuits. A concluding comparison is made between on-chip and on-package integration of a small antenna for microwave and millimeter wave systems.

Future microprocessors and off-chip SOP interconnect

Abstract: Limits to chip power dissipation and power density and limits on the benefits of hyperpipelining in microprocessors threaten to stop the exponential performance growth in microprocessor performance that we have grown accustomed to. Multicore processors can continue to provide historical performance growth on most modern consumer and business applications. However, power efficiency of these cores must also be improved to stay within reasonable power budgets. This can be achieved by simplifying the processor core architecture, and reversing the trend toward ever more-complex and less power-efficient cores. To maintain overall performance growth with stunted per-core and per-thread performance, growth rates will require an even more rapid increase in the number of cores per die. Growing performance by increasing the number of cores on a die at this rate, however, puts unprecedented requirements on the corresponding growth of off-chip bandwidth. We argue that contrary to the international roadmap for semiconductors (ITRS) predictions, off-chip signaling frequencies are likely to exceed the frequencies of processor cores in the not too distant future, consistent with the system-on-package (SOP) concept in the first paper of this issue. If this approach is followed, a 1-TFlops multiprocessor die with 1 TB/s of off-chip bandwidth is feasible at reasonable cost before the end of the decade.

Embedded resistors and capacitors for organic-based SOP

Abstract: System-on-package (SOP) architectures take advantage of compact, high-performance designs to place the maximum amount of functionality on a subsystem that can then be mounted on a lower-cost, lower density interconnect board. Embedding passive components is a key technology in achieving these goals since this enables smaller SOP substrate footprints or, equivalently, higher functional density, along with better power distribution, increased design flexibility and improved reliability. The resulting footprint areas of integrating capacitors will have more of an effect on the layer count of SOP assemblies than will integrating resistors due to the rather low specific capacitances of most embeddable dielectrics, but the situation is improving steadily. It may be necessary to use two different dielectric materials to cover the entire required range. The inherently lower parasitic inductance of embedded capacitors makes them much more useful in decoupling than surface mount capacitors, enabling more robust power distribution and decreased power/ground noise. The key to this performance enhancement in large boards is the use of a thin dielectric to decrease the inductance but, for the smaller SOP substrates, the dielectric constant must also be high to provide sufficient decoupling capacitance in the reduced area.

Next-generation microvia and global wiring technologies for SOP

Abstract: As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-/spl mu/m area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 /spl mu/m diameter and lines and spaces of 25 /spl mu/m. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for micro via wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 /spl mu/m and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation.

Chip-to-chip optoelectronics SOP on organic boards or packages

Abstract: In this paper, we demonstrate compatibility of hybrid, large-scale integration of both active and passive devices and components onto standard printed wiring boards in order to address mixed signal system-on-package (SOP)-based systems and applications. Fabrication, integration and characterization of high density passive components are presented, which includes the first time fabrication on FR-4 boards of a polymer buffer layer with nano scale local smoothness, blazed polymer surface relief gratings recorded by incoherent illumination, arrays of polymer micro lenses, and embedded bare die commercial p-i-n photodetectors. These embedded optical components are the essential building blocks toward a highly integrated SOP technology. The effort in this research demonstrates the potential for merging high-performance optical functions with traditional digital and radio frequency (RF) electronics onto large area and low-cost manufacturing methodologies for multifunction applications.

Stackable system-on-packages with integrated components

Abstract: In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in the Z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology.

A reworkable epoxy resin for isotropically conductive adhesive

Abstract: Electrically conductive adhesive (ECA) is a promising alternative to the toxic eutectic tin-lead solder as an interconnect material. Typical ECAs use epoxy resin as their matrix, which has superior properties over other polymers, such as high adhesion, and low dielectric constant. However, once cured, it is not reworkable. In this study, a liquid diepoxide was designed and synthesized, and used in isotropically conductive adhesive (ICA) formulations. This diepoxide has a molecular structure able to thermally decompose at mild temperature that allows selective individual removal of the bad component without damaging the board and its surroundings. The characterizations including proton and carbon 13 nuclear magnetic resonance, infrared spectroscopy indicated the success of the synthesis. A dual-epoxy system containing this secondary diepoxide and an equivalent bisphenol-A diepoxide were formulated and cured with an anhydride hardener and an imidazole catalyst. Thermal analyses, such as differential scanning calorimetry, thermo-gravimetry analysis (TGA), thermo-mechanical analysis (TMA) and dynamic mechanical analysis (DMA) were employed for the curing kinetics, thermal degradation behavior, glass transition temperature, coefficient of thermal expansion (CTE), and mechanical modulus, respectively. The dual-epoxy system showed two exothermal curing peaks at 140/spl deg/C and 180/spl deg/C, respectively. The thermoset of this dual-epoxy system has a decomposition temperature around 234/spl deg/C, a glass transition temperature around 80 to 90/spl deg/C, and CTEs of 74 ppm//spl deg/C and 225 ppm//spl deg/C below and above its Tg, respectively. The rework test on a surface mount component bonded to copper surface showed this ECA can be easily and quickly removed from the copper surface. The bulk resistance and contact resistance of ICAs were measured before and during an accelerated aging process in a temperature/humidity chamber (85/spl deg/C/85% RH). The ECA showed good bulk resistivity and contact resistance comparable to its control and a commercial ECA on gold and copper surface finishes.

Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design

Abstract: An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC, is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally, some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.

Stacked modular package

Abstract: This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is a cost-effective solution to save placement and routing area on the board. Furthermore, a vertical module enables the benefit of several IC processes in the same module. The goal was to develop a method to produce a stacked modular package on a small scale, and to verify the feasibility of the solution. The main focus has been to test the bare die connections to the interposer and the vertical connections between interposers. The structure enables also, e.g., thin discretes, and passive arrays to be assembled on the interposer, thus enabling system-in-package (SiP) solutions. The method has been tested using thin daisy chain dice and daisy chain vertical interconnections. The dimensions of the developed six chip modules were 14/spl times/8/spl times/0.8-1 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were either 100 or 150-/spl mu/m thick, and the chips were thinned down to 90 /spl mu/s. Eutectic tin-lead solder bumps were used to mount the flip chips to the interposer. Solder-coated polymer spheres were used to stack the interposers on top of each other. The developed stacking process and vertical area interconnections by plastic core balls give good reliability and uniform stand-off height. Thermal cycling test +125/-40/spl deg/C until 2000 cycles proved reliability of the structure. Flip-chip failures were found after 500 cycles and only 1 of 32 vertical connection failures occurred during the test. Furthermore, this was caused, at least partly, by excess solder. Plastic ball as interconnection media between stacked layers gives good reliability and uniform stand-off height.

Twisted differential line structure on high-speed printed circuit boards to reduce crosstalk and radiated emission

Abstract: Differential signaling has become a popular choice for high-speed digital interconnection schemes on printed circuit boards (PCBs), offering superior immunity to crosstalk and external noise. However, conventional differential lines on PCBs still have unsolved problems, such as crosstalk and radiated emission. When more than two differential pairs run in parallel, a line is coupled to the line adjacent to it because all the lines are parallel in a fixed order. Accordingly, the two lines that constitute a differential pair are subject to the differential-mode crosstalk that cannot be canceled out by virtue of the differential signaling. To overcome this, we propose a twisted differential line (TDL) structure on a high-speed multilayer PCB by using a concept similar to a twisted pair in a cable interconnection. It has been successfully demonstrated by measurement and simulation that the TDL is subject to much lower crosstalk and achieves a 13-dB suppression of radiated emission, even when supporting a 3-Gb/s data rate.

Innovative circuit board level routing designs for BGA packages

Abstract: Advances in the performance of electronic devices have resulted in high input/output counts both at the chip and the package level, which has led to the development of new packaging technologies that can accommodate these high counts. This paper presents and analyzes a novel method for the placement of ball grid array (BGA) bonding pads and routing wires on printed circuit boards to maximize signal density, which ultimately reduces the number of circuit board layers needed for routing. This method has been termed as the "balls shifted as needed" method and all the ball placement/trace routing designs shown in this paper are based on this method. We also present a performance metric defined as the number of balls routed out divided by the area of package footprint on the circuit board, and we compare various placement/routing schemes using this method.

Generating compact, guaranteed passive reduced-order models of 3-D RLC interconnects

Abstract: As very large scale integration (VLSI) circuit speeds and density continue to increase, the need to accurately model the effects of three-dimensional (3-D) interconnects has become essential for reliable chip and system design and verification. Since such models are commonly used inside standard circuit simulators for time or frequency domain computations, it is imperative that they be kept compact without compromising accuracy, and also retain relevant physical properties of the original system, such as passivity. In this paper, we describe an approach to generate accurate, compact, and guaranteed passive models of RLC interconnects and packaging structures. The procedure is based on a partial element equivalent circuit (PEEC)-like approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior. The resulting formulation, based on nodal or mixed nodal and mesh analysis, enables the application of existing model order reduction techniques. Compactness and passivity of the model are then ensured with a two-step reduction procedure where Krylov-subspace moment-matching methods are followed by a recently proposed, nearly optimal, passive truncated balanced realization-like algorithm. The proposed approach was used for extracting passive models for several industrial examples, whose accuracy was validated both in the frequency domain as well as against measured time-domain data.

High-speed interconnects with underlayer orthogonal metal grids

Abstract: On-chip high-speed interconnects with underlayer orthogonal metal grids, including grid-backed lines (GBLs) and grid-backed coplanar waveguides (GBCPWs), are characterized through s-parameter measurements. For GBL test structures, the presence of underlayer metal grids reduces dispersion by a factor of 4 while the local speed of light decreases by a factor of 2 in comparison to those of conventional microstrip lines. The dispersion reduction comes from suppressing higher order modes; the local speed of light reduction comes from a longer current return path. These characteristics are beneficial for compact CMOS analog circuit designs. Losses caused by substrate and conductor lines are restrained by shielding the substrate and by involving weaker electric fields. Resonance at a frequency characterized by that of a patch antenna was observed and needs to be considered in high-speed circuit designs. The grids have weaker effects in the case of CPWs, where the side ground plate effects are significant. A signal transmission example shows that dispersion and frequency-dependent losses are important in determining the signal rise edge. Semi-empirical distributed resistance-inductance-capacitance-conductance (RLCG) equivalent circuit models are constructed for the interconnects below the resonant frequencies.

A novel algorithm for fiber-optic alignment automation

Abstract: An efficient and robust fiber-optic active alignment algorithm for locating the optimal fiber-optic coupling position is critical to the fiber-optic packaging automation, and thus to the cost effective manufacturing of fiber optic components and modules. A robust and speedy fiber-optic alignment algorithm must be capable of avoiding local power peak trapping and simultaneous multidegree of freedom alignment. The currently most widely employed fiber-optic alignment algorithms are based on the so-called hill-climbing method. Because the hill-climbing method is a "one-dimensional-at-a-time" gradient searching method, it can only deal with the alignment on one direction at one time, so it is usually time-consuming and often the real peak cannot be detected because of local peak trapping. Another disadvantage of the hill-climbing method is that it is especially difficult when dealing with angular alignment and arrayed device alignment. Our novel approach is based on the application of the Nelder-Mead Simplex optimization method. The performance of the algorithm is investigated for the first time for three different fiber-optic alignment conditions, i.e., 1) two-dimensional (X and Y) alignment in the presence of side-modes for a single channel fiber-optic device; 2) simultaneous six-dimensional (i.e., three linear, two angular, and one rotational) alignment for a wedged fiber to a laser diode; 3) three-dimensional (X, Y, and rotation) alignment of eight-channel fiber-arrayed devices. We have found that this method has the advantage of fast convergence and easy-implementation. Simulation results indicates that the algorithm converges five times faster than the conventional hill-climbing method; it works well in the presence of side-modes; and it converges to the maximum coupling efficiency within 15 Simplex iterations for the six-DOF alignment; for the arrayed devices, it also only requires less than 15 iterations to reach a balanced optimal coupling position for each channel.

Packaging of copper/low-k IC devices: a novel direct fine pitch gold wirebond ball interconnects onto copper/low-k terminal pads

Abstract: The trend toward finer pitch and higher performance devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and/or silicon nitride passivation, a Cu/low-k combination offers higher on-chip communication speed and a lower overall device cost. However, the process of packaging Cu/low-k devices has been proven to be difficult, relying either on additional lithography and deposition steps or on costly new process tools. Thus, this paper presents a novel methodology to bond fine pitch Au wire directly onto the Cu/low-k pad structure using the industry standard tool set. A Cu/low-k test vehicle is designed with the required slotted low-k fillings for dual damascene chemical mechanical polishing (CMP) process need. In addition, a thin organic passivation film is developed for coating the exposed Cu/low-k pad temporarily from copper oxidation and to provide a wirebondable surface to form the proper interconnects. A design of experiment is performed to optimize wirebonding parameters [power, time, and ultrasonic gauge (USG) bleed], along with key physical contributors from wafer sawing and die attaching steps that impact the interconnect shear strength and quality. In addition, electrical and optical characterization and surface failure analysis are performed to confirm the feasibility of the technology. Finally, reliability results of the pad structure design and recommendations for further process optimization are presented.

Online-offline laser ultrasonic quality inspection tool for multilayer ceramic capacitors - part II

Abstract: The adoption of surface mount technology has provided many competitive advantages for the electronics industry. Smaller, lighter, and more efficient packages create better products for consumers, but new manufacturing problems are created through the adoption of new technology. Inspection and verification systems are employed to prevent known defective parts from reaching consumers, but not all future reliability problems can be identified through traditional inspection methods. In multilayer ceramic capacitors (MLCCs), flex cracks can be created during manufacturing. However, traditional online and offline inspection methods have been unable to consistently identify these defects. The location and orientation of the cracks, perpendicular to the printed wiring board (PWB) and obscured by the MLCCs end metallization for solder connection, makes detection using immersion ultrasound or x-ray inspection difficult. The metallization occludes the ability of these methods to image the defect. Therefore, a new inspection technique is required to identify these defects. A laser-generated ultrasonic system has been designed and constructed to meet the need of a noncontact, nondestructive, fast, and accurate system for identifying defects in a laboratory environment, as well as on the manufacturing fine. The system consists of a pulsed infrared laser that excites samples of both an 0805, 10 /spl mu/F, 6.3 V, X5R and an 0603, X5R, 6.3 V, 1 /spl mu/F, MLCC, both having square cross sections, into small-amplitude structural vibration after attachment to the PWB through the process of laser-generated ultrasound. An interferometer, sampled with a synchronized data acquisition system, records the structural impulse response of the MLCC. Monitoring the impulse response for changes indicates changes in the structure of the device. Several MLCC samples were prepared and mounted on PWBs, and some of them were intentionally flexed until a loss of insulation resistance was recorded, indicating the presence of a flex crack. Measurements were taken on the as-manufactured and flexed-to-failure samples. The test results contained in part I were obtained with 0805 MLCC samples with rectangular cross sections, which are less stiff than MLCCs with square cross sections. These results indicated potential for success using the method described here to identify flex cracks. These results indicated potential for success using the method described here to identify flex cracks. The current results also indicate that the laser ultrasonic system could be used to detect flex cracks in 0805 MLCCs with a square cross section and in the smaller 0603 package configuration with a square cross section. Classification of the capacitors requires a reduction in the variance of the error ratio values, so an average of the values computed in comparison with each of the reference devices is implemented.

De-embedding procedure based on computed/measured data set for pcb structures characterization

Abstract: This paper uses a de-embedding procedure, based on measured and numerically computed S-parameters, to obtain the characterization of portions of a structure difficult to obtain by direct measurements. The results are validated by measurements and independent calculations.

Characterization of an experimental ferrite LTCC tape system for microwave and millimeter-wave applications

Abstract: An experimental-low temperature cofired ceramic (LTCC) ferrite tape system is characterized using circuits that are fabricated from the very material under test. Such in situ circuits provide data that are thought to be more representative of the performance obtainable by more complicated circuitry that will eventually be made from the same material using the same fabrication method. Emphasis is placed on simple measurements that can be performed using a minimum amount of equipment. For the first time, a compact in situ LTCC solenoid transformer is used to measure the magnetostatic properties of the ferrite, yielding a measured saturation flux density of 230 mT, a remanence of 136 mT, and a coercivity of 688 A/m. The peak linear relative permeability of the ferrite is 97 and its Curie temperature is low, only 117/spl deg/C. A novel two-port line-connected ring resonator is used to characterize the material in the 6-40 GHz range. At frequencies above 20 GHz, the relative permittivity of the ferrite is 11.0, whereas its loss tangent ranges from 0.002 to 0.004, demonstrating the ferrite's suitability for use in microwave and millimeter-wave circuitry.