Showing papers in "IEEE Transactions on Advanced Packaging in 2006"

Design and Characterization of Purely Textile Patch Antennas

Abstract: In this paper, we present four purely textile patch antennas for Bluetooth applications in wearable computing using the frequency range around 2.4 GHz. The textile materials and the planar antenna shape provide a smooth integration into clothing while preserving the typical properties of textiles. The four antennas differ in the deployed materials and in the antenna polarization, but all of them feature a microstrip line as antenna feed. We have developed a manufacturing process that guarantees unaffected electrical behavior of the individual materials when composed to an antenna. Thus, the conductive textiles possess a sheet resistance of less than 1Omega/squarein order to keep losses at a minimum. The process also satisfies our requirements in terms of accuracy meeting the Bluetooth specifications. Our investigations not only characterize the performance of the antennas in planar shape, but also under defined bending conditions that resemble those of a worn garment. We show that the antennas can withstand clothing bends down to a radius of 37.5 mm without violating specifications

Bumpless interconnect through ultrafine Cu electrodes by means of surface-activated bonding (SAB) method

Abstract: In this paper, we demonstrate the feasibility of ultrahigh-density bumpless interconnect by realizing the ultrafine pitch bonding of Cu electrodes at room temperature. The bumpless interconnect is a novel concept of bonding technology that enables a narrow bonding pitch of less than 10 /spl mu/m by overcoming the thermal strain problem. In the bumpless structure, two thin layers including an insulator and metallic interconnections on the same surface are bonded at room temperature by the surface-activated bonding (SAB) method. In order to realize the bumpless interconnect, we invented a SAB flip-chip bonder that enabled the alignment accuracy of /spl plusmn/1 /spl mu/m in the high vacuum condition. Moreover, the fabrication process of ultrafine Cu electrodes was developed by using the damascene process and reactive ion beam etching (RIE) process, and the bumpless electrodes of 3 /spl mu/m in diameter, 10 /spl mu/m in pitch, and 60 nm in height were formed. As a result, we succeeded in the interconnection of 100 000 bumpless electrodes with the interfacial resistance of less than 1 m/spl Omega/. An increase of the resistance was considerably small after thermal aging at 150/spl deg/C for 1000 h.

An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

Abstract: Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it Full-wave methods are often employed to study the power integrity problem While full-wave methods can be accurate, they are time and memory consuming The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived This allows both frequency and transient responses to be done with SPICE simulation

The development of Cu bonding wire with oxidation-resistant metal coating

Abstract: Although Cu bonding wire excels over Au bonding wire in some respects such as production costs, it has not been widely used because of its poor bondability at second bonds due to surface oxidation. We conceived an idea of electroplating oxidation-resistant metal on the Cu bonding wire to prevent the surface oxidation. The electroplating of Au, Ag, Pd, and Ni over Cu bonding wire all increased bond strengths as expected, but it caused problematic ball shapes except Pd-plated Cu bonding wire. The wire could produce the same ball shape as that of Au bonding wire. It was also proved to have excellent bondability sufficient to replace Au bonding wire. That is, it excelled in bond strengths, defective bonding ratio, and wideness of "Parameter Windows". It also showed the same stability as Au bonding wire in reliability tests, while bonds of Cu bonding wire were deteriorated in a few of the tests. In short, the Pd-plated Cu bonding wire can realize excellent bonding similar to Au bonding wire, while having much lower production costs.

On the generation of large passive macromodels for complex interconnect structures

Abstract: This paper addresses some issues related to the passivity of interconnect macromodels computed from measured or simulated port responses. The generation of such macromodels is usually performed via suitable least squares fitting algorithms. When the number of ports and the dynamic order of the macromodel is large, the inclusion of passivity constraints in the fitting process is cumbersome and results in excessive computational and storage requirements. Therefore, we consider in this work a post-processing approach for passivity enforcement, aimed at the detection and compensation of passivity violations without compromising the model accuracy. Two complementary issues are addressed. First, we consider the enforcement of asymptotic passivity at high frequencies based on the perturbation of the direct coupling term in the transfer matrix. We show how potential problems may arise when off-band poles are present in the model. Second, the enforcement of uniform passivity throughout the entire frequency axis is performed via an iterative perturbation scheme on the purely imaginary eigenvalues of associated Hamiltonian matrices. A special formulation of this spectral perturbation using possibly large but sparse matrices allows the passivity compensation to be performed at a cost which scales only linearly with the order of the system. This formulation involves a restarted Arnoldi iteration combined with a complex frequency hopping algorithm for the selective computation of the imaginary eigenvalues to be perturbed. Some examples of interconnect models are used to illustrate the performance of the proposed techniques.

Noise reduction using compensation capacitance for bend discontinuities of differential transmission lines

Abstract: Differential signaling has become a popular choice for multigigabit digital applications in favor of its low-noise generation and high common-mode noise immunity. Recalling from the full-wave solution of S-parameters, this paper presented a design methodology of analysis scheme to extract the equivalent circuits of discontinuities observed on the strongly coupled differential lines. Signal integrity effects of the bent differential transmission lines in a high-speed digital circuit were then simulated in the time domain. A dual back-to-back routing topology of bent differential lines to reduce the common-mode noise was further investigated. To alleviate the common-mode noise at the receiver, a novel compensation scheme in use of the shunt capacitance was also proposed. Furthermore, the comparison between the simulation and measured results validated the equivalent circuit model, coupled bends with compensation capacitance patch, and analysis approach

A novel aluminum-filled composite dielectric for embedded passive applications

Abstract: This paper presents the development of a novel aluminum-filled high dielectric constant composite for embedded passive applications. Aluminum is well known as a low-cost and fast self-passivation metal. The self-passivation forms a nanoscale insulating boundary outside of the metallic spheres, which has dramatic effects on the electrical, mechanical, and chemical behaviors of the resulting composites. Influences of aluminum particle size and filler loading on the dielectric properties of composites were studied. Because of the self-passivated insulating oxide layer of fine aluminum spheres, a high loading level of aluminum can be used while the composite materials continues to be insulating. Dielectric property measurement demonstrated that, for composites containing 80 wt% 3.0 /spl mu/m aluminum, a dielectric constant of 109 and a low dissipation factor of about 0.02 can be achieved. The dielectric constant of epoxy-aluminum composites increased almost 30 times as compared with that of the pure epoxy matrix, which is about 3.5. Die shear tests showed that at such loading level, materials still had good processability and good adhesion toward the substrate. Bulk resistivity measurement, high-resolution transmission electron microscope (HRTEM) observation, and thermogravimetric analysis (TGA) were conducted to characterize the aluminum powders in order to understand the dielectric behavior of aluminum-filled composites. Bimodal aluminum-filled composites were also systematically studied in order to further increase the dielectric constant. Ouchiyama-Tanaka's model was used to calculate the theoretical maximum packing fraction (MPF) of bimodal systems. Based on the calculation, rheology studies were performed to find the optimum bimodal filler volume fraction ratio that led to the best packing efficiency of bimodal fillers. It was found that the viscosity of polymer composites showed a minimum at optimum bimodal filler volume fraction ratio. A high dielectric constant of 160 (@10 kHz) with a low dissipation factor of less than 0.025 was achieved with the optimized bimodal aluminum composites. The developed aluminum composite is a promising candidate material for embedded capacitor applications.

On the operation of a press pack IGBT module under short circuit conditions

Abstract: Press pack insulated gate bipolar transistor (IGBT) modules connected in series for high-voltage direct current (HVDC) converter applications are designed such that when a failure occurs, it occurs in a safe manner by the formation of a stable short circuit, while redundant modules take up the voltage blocking function of the failed module. One such design using individual pressure contacts is described and the events occurring from the initiation of the short circuit to its final failure due to open circuit are reported from an electronics packaging materials design point of view. Experiments to hasten the failure under accelerated test conditions on modules were performed and interrupted at various stages of operation under a short circuit condition. The formation and subsequent aging of the metallurgical alloy under short circuit conditions was investigated by analyzing cross sections of the alloy forming the short circuit. Liquid metal corrosion along with the formation of intermetallics with poor conductivities lead to the final failure by open circuit

Simulation of coupled interconnects using waveform relaxation and transverse partitioning

Abstract: The large number of coupled lines in an interconnect structure is a serious limiting factor in simulating high-speed circuits. A new method is presented for efficient simulation of large interconnects based on transverse partitioning and waveform relaxation techniques. The computational cost of the proposed algorithm grows linearly with the number of coupled lines. In addition, the algorithm is highly suitable for parallel implementation leading to further significant reduction in the computational complexity.

Modeling and measurement of simultaneous switching noise coupling through signal via transition

Abstract: The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach

Modeling of striplines between a power and a ground plane

Abstract: In this paper, a stripline model is presented for coupled signal lines routed between a power and a ground plane based on multiconductor transmission line (MTL) theory. Through a suitable diagonalization of the MTL equations for striplines, the transverse electromagnetic (TEM) parallel-plate mode is decoupled from the stripline mode. In this way, stripline models that are obtained assuming ideal planes at ground potential can be extended to take into account the nonideal behavior of the planes. The presented model is applied to represent mode conversion due to vias, holes in the reference planes, and terminations of the stripline. Influence of inhomogeneous media is discussed

Macromodeling of nonlinear digital I/O drivers

Abstract: In this paper, a modeling technique using spline functions with finite time difference approximation is discussed for modeling moderately nonlinear digital input/output (I/O) drivers. This method takes into account both the static and the dynamic memory characteristics of the driver during modeling. Spline function with finite time difference approximation includes the previous time instances of the driver output voltage/current to capture the output dynamic characteristics of digital drivers accurately. In this paper, the speed and the accuracy of the proposed method is analyzed and compared with the radial basis function (RBF) modeling technique, for modeling different test cases. For power supply noise analysis, the proposed method has been extended to multiple ports by taking the previous time instances of the power supply voltage/current into account. The method discussed can be used to capture sensitive effects like simultaneous switching noise (SSN) and cross talk accurately when multiple drivers are switching simultaneously. A comparison study between the presented method and the transistor level driver models indicate a computational speed-up in the range of 10-40 with an error of less than 5%. For highly nonlinear drivers, a method based on recurrent artificial neural networks (RNN) is discussed.

Room-temperature microfluidics packaging using sequential plasma activation process

Abstract: A sequential plasma activation process consisting of oxygen reactive ion etching (RIE) plasma and nitrogen radical plasma was applied for microfluidics packaging at room temperature. Si/glass and glass/glass wafers were activated by the oxygen RIE plasma followed by nitrogen microwave radicals. Then, the activated wafers were brought into contact in atmospheric pressure air with hand-applied pressure where they remained for 24 h. The wafers were bonded throughout the entire area and the bonding strength of the interface was as strong as the parents bulk wafers without any post-annealing process or wet chemical cleaning steps. Bonding strength considerably increased with the nitrogen radical treatment after oxygen RIE activation prior to bonding. Chemical reliability tests showed that the bonded interfaces of Si/Si could significantly withstand exposure to various microfluidics chemicals. Si/glass and glass/glass cavities formed by the sequential plasma activation process indicated hermetic sealing behavior. SiOx Ny was observed in the sequentially plasma-treated glass wafer, and it is attributed to binding of nitrogen with Si and oxygen and the implantation of N2 radical in the wafer. High bonding strength observed is attributed to a diffusion of absorbing water onto the wafer surfaces and a reaction between silicon oxynitride layers on the mating wafers. T-shape microfluidic channels were fabricated on glass wafers by bulk micromachining and the sequential plasma-activated bonding process at room temperature

Polymer Optical Interconnects—A Scalable Large-Area Panel Processing Approach

Abstract: A flexible approach to producing optical interconnects on 6096 $ast ,$ 6096 mm large-area panels is demonstrated Stepwise projection patterning from 1016 $ast ,$ 1016 mm masks has generated optical waveguide patterns over the whole panel using large-area projection lithography equipment The waveguide routing design allows optical waveguides on different 1016 $ast ,$ 1016 mm tiles to be interconnected Four different waveguide connecting geometries in the border region between tiles have been fabricated and tested Multimode waveguides from inorganic-organic hybrid polymers (ORMOCER) (cross section: $le hbox 50~muhbox mast hbox 10~muhbox m$ ) with refractive index step between core and cladding $Delta n=hbox 001$ were produced The index step was adjusted by mixing two diffrent ORMOCER systems The materials show good adhesion to numerous substrates, such as glass and silicon Application concepts such as flexible manufacturing of optoelectrical hybrid backplanes with two-dimensional interconnect, a three-dimensional optical interconnect with optical vias, and a hybrid backplane with the optical interconnect in a strip-format on a separate plane right above the electrical plane are proposed Promising new technologies are presented along with preliminary demonstrativ viability

Silicon micromachining of high aspect ratio, high-density through-wafer electrical interconnects for 3-D multichip packaging

Abstract: This paper presents a novel silicon micromachining method, which combines tetra methyl ammonium hydroxide (TMAH) etching and deep-reactive ion etching (DRIE) along with bottom-up copper electroplating, to fabricate high-density and high-aspect ratio through-wafer electrical interconnects (TWEIs) for three-dimensional multichip packaging. The silicon wafer was locally etched with TMAH from the backside until the desired membrane thickness was reached, and then DRIE was performed on the membrane until the holes were etched through. TMAH etching preserved large areas of the wafers at the original thickness, thus, ensuring relatively strong mechanical strength and manipulability. DRIE made it possible to realize high-aspect ratio holes with minimized wafer area consumption. A new bottom-up copper electroplating technique was developed to fill the high-aspect ratio through-wafer holes. This method can avoid seams and voids while achieving attractive electrical features. Through-wafer holes, as small as 5 mum in diameter, have been realized by using the combination of TMAH and DRIE, and have been completely and uniformly filled by using bottom-up copper electroplating

A Fully Embedded 60-GHz Novel BPF for LTCC System-in-Package Applications

Abstract: In this paper, a novel LTCC stripline (SL) 60-GHz band-pass filter (BPF) composed of transitions to coplanar waveguide (CPW) pads for monolithic microwave integrated circuit integration is presented. For low-loss interconnection with active devices, a CPW-to-SL vertical via transition integrating air cavities and a CPW-to-CPW planar transition using internal ground planes are proposed and implemented. The fabricated transition shows an insertion loss of 1.6 dB and a reflection loss below -20 dB at the passband of the filter. The implemented SL BPF using dual-mode patch resonators shows a center frequency of 60.4 GHz, 3.5 % bandwidth, and reflection losses below -15 dB at the passband. Excluding the insertion loss of the transitions, the filter insertion loss reveals 4.0 dB

Thermal Fatigue of SnPb and SAC Resistor Joints: Analysis of Stress-Strain as a Function of Cycle Parameters

Abstract: Accelerated thermal cycling (ATC) has been widely used in the microelectronics industry for reliability assessment. The relative effects of thermal cycling parameters (temperature range, dwell time, and ramp rate) and the failure mechanisms they induce have been the subject of many studies; however, uncertainty remains, particularly regarding the role of a very high ramp rate such as encountered in a thermal shock chamber. In the present research, thermomechanical finite-element (FE) models were used to analyze the stress/strain response of a resistor test vehicle during ATC testing under three accelerated test conditions: two ramp rates (14 degC/min and 95 degC/min) and two temperature ranges (DeltaT=0degC-100degC and -40degC-125degC), denoted 14-100 (ramp rate-temperature range), 95-100, and 95-165. The temperature gradients through the thickness of the assemblies were measured during the ATC test with the high ramp rate and were used to create an FE model that included transient stresses and strains. The effect of the transient temperature gradients during thermal shock was found to be negligible in these resistor joints. The FE models were then used to simulate the above three ATC test conditions with either SnPb or Pb-free (SAC) solders and were compared with previously published thermal fatigue lives for this resistor test vehicle. For both SnPb and SAC resistors, the maximum total solder strains (sum of elastic, plastic, and creep) and strain energy dissipation per cycle predicted by the FE models in the 95-165 test condition were much greater than those in either the 14-100 or 95-100 test conditions, which produced almost identical strains and energy dissipation. In all cases, the strain energy density dissipation per cycle due to creep was much larger than that due to plastic deformation. The trend of these results was in accordance with the ATC tests, which showed that the thermal cycling lives decreased in the same order for both the SAC and SnPb solders; i.e., the fatigue life decreased as the predicted total strain increased

An accurate experimental method for characterizing transmission lines embedded in multilayer printed circuit boards

Abstract: We have developed an accurate method for measuring the complex propagation constant and characteristic impedance of transmission lines embedded in multilayer printed circuit boards. It is based on mathematical error-removal schemes using two different length transmission lines and an advanced via-hole structure that minimizes coupling. Consequently, associated errors, due to discontinuities and interference can be effectively eliminated, and the frequency dependencies of the transmission line parameters can be clarified in wide frequency bandwidths. We verified the validity of this method in frequency ranges up to at least 18 GHz, by comparing the determined values with the theory derived from transverse electromagnetic (TEM) approximations.

Transient simulation of wire pull test on Cu/low-K wafers

Abstract: This paper focuses on the numerical analysis of pull test reliability of gold wires bonded on the Cu/low-K wafer. Prior to wire pull, transient analysis of the complete wirebonding process, which involves both impact and ultrasonic vibration stages, is performed to allocate residual stresses within the wire and the Cu/low-K structure. After wirebonding, fracturing of the wire subjected to a pull load is modeled using the eroding technique so that failure patterns and bonding strength of the wire can be investigated. The analysis applies the explicit time integration scheme, which is feasible in dealing with nonlinear transient structural behavior. Parametric studies show that as the yield stress of the low-K material decreases, the pull force reduces significantly. Furthermore, the pull force increases as the bond force increases but not very significantly

Advances in Vapor Pressure Modeling for Electronic Packaging

Abstract: Two advanced techniques have been developed for modeling vapor pressure within the plastic IC packages during solder reflow. The first involves the extension of the "wetness" technique to delamination along multimaterial interface and during dynamic solder reflow. Despite its simplicity, this technique is capable of offering reliable and accurate prediction for packages with high flexural rigidity. For packages with low flexural rigidity, the new "decoupling" technique that integrates thermodynamics, moisture diffusion, and structural analysis into a unified procedure has been shown to be more useful. The rigorous technique has been validated on both leadframe-based as well as laminate-based packages. With high accuracy and computational efficiency, these dynamic modeling tools will be valuable for optimization of package construction, materials, and solder reflow profile against popcorn cracking for both SnPb and Pb-free solders

A new circuit augmentation method for modeling of interconnects and passive components

Abstract: This paper presents a new methodology for automated broadband model generation from S-parameter data for interconnects and passive components. The new methodology is based on augmenting an existing equivalent circuit model with a macromodel (black-box) network described by rational functions while simultaneously perturbing the equivalent circuit component values. The macromodel network is determined using standard least-squares or vector-fitting approaches. The perturbation of the equivalent circuit parameter values is achieved during the macromodel generation by means of global optimization based on intelligent search algorithms. The new approach is demonstrated on several two-port test example structures including a broadband probe tip structure and a CMOS spiral inductor.

Fluxless Flip-Chip Solder Joint Fabrication Using Electroplated Sn-Rich Sn–Au Structures

Abstract: A fluxless flip-chip bonding process in hydrogen environment using newly developed Sn-rich Sn-Au electroplated multilayer solder bumps is presented. Cr/Au dual layer is employed as the plating seed layer and the underbump metallurgy (UBM). This UBM design, seldom used in the electronic industry, is explained in some details. To realize the fluxless possibility, proper intermetallic growth over the composite structure is needed. In this connection, we like to point out that it is much harder to achieve fluxless bonding using Sn-rich Sn-Au design than the familiar Au-rich 80Au20Sn eutectic design. This is so because Sn-rich Sn-Au alloys have numerous Sn atoms on the surface that can get oxidized easily while the Au-Sn eutectic alloy at thermal equilibrium consists of only Au5Sn and AuSn compounds. Intermetallic nucleation and growth mechanism of sequential electroplating of Au over thick Sn layer is studied with scanning electron microscope (SEM), energy dispersive X-ray spectroscopy (EDX), and X-ray diffraction method (XRD). It is found that Au-Sn intermetallic forms as Au is plated over the Sn layer and acts as a barrier that prevents the oxidation of the inner Sn layer, making fluxless possibility a reality. It is found that the SnAu intermetallic compounds are randomly distributed in the Sn rich joint making the joint strong. The resulting joints contain few voids as examined by an SEM and a scanning acoustic microscope (SAM) and have a remelting temperature of 217degC-222degC. The plated Sn-Au solder bumps on silicon with 50 mum in height are flip-chip bonded to borosilicate glass substrate. This new fluxless flip-chip bonding process is valuable in many applications where the use of flux is prohibited

Study on the effects of wafer thinning and dicing on chip strength

Abstract: Die cracking is an annoying problem in the packaging industry. In this paper, we identified the weak regions, in terms of mechanical strength, in chips in a semiconductor wafer using the three-point bending test. The weak regions were observed in two sectors approximately 45/spl deg/ wide, axisymmetric to the wafer center. The strength of the chips within these weak regions was about 30%-35% lower than the average chip strength of the whole wafer. The existence of these weak regions was related to spiral grinding marks, which, in turn, were formed by backside mechanical grinding. The probability distributions of the chip strength and the chip fragmentary pattern confirmed this relationship. When wafers were mechanically ground until they were 50-/spl mu/m thick, chip warpage was found to be oriented to the direction of the grinding marks. Meanwhile, by slowing the mechanical grinding speed by 50%, we were able to increase the average chip strength by 56%. Either plasma etching or polishing after mechanical grinding eliminated the weak regions, and the optimal amount of mechanical grinding and the polishing depths were observed, beyond which the chip strength would not increase. On the other hand, a preprocess for blunting a new saw blade for chip dicing was found to be essential as the chip strength increased five-fold, whereas increasing the dicing speed or using dual saw instead of a single saw had only small effects on the chip strength degradation.

Embedded power: a 3-D MCM integration technology for IPEM packaging application

Abstract: Embedded power (EP) is the name for an integration technology for the power electronics switching stage, in which the multiple bare power chips, such as IGBTs, MOSFETs, and diodes, are buried in a ceramic frame and covered by a dielectric layer with via holes on the Al pads of the chips. Then, a planar metallization pattern is deposited onto it both for bonding to the power chips and a circuit wiring. The ceramic frame can be used as an extra thermal path and substrate for fabrication of the hybrid circuit with compatible thin- or thick-film techniques. When this integrated chips component is stacked with a base substrate and the associated components, a novel three-dimensional (3-D) multichip module (MCM) is produced. Such an integrated power electronics module (IPEM) offers performance improvement, functional integration, and process integration, as compared to conventional power hybrid modules. This paper presents the details of this technology, including the process design and implementation. A subsystem IPEM, incorporating power factor correction (PFC) and dc/dc switching stages for a distributed power system (DPS) front-end converter application, has been fabricated and characterized to demonstrate the feasibility of this power electronics integration technology. The capability for functional integration and the electrical performance improvement, which includes reduction in parasitics and increase in efficiency, are presented

Advanced acoustic microimaging using sparse signal representation for the evaluation of microelectronic packages

Abstract: Acoustic microimaging (AMI) has been widely used to nondestructively evaluate microelectronic packages for the presence of internal defects. To detect defects in small devices such as /spl mu/BGA, flip-chip, and chip-scale packages, high acoustic frequencies are required for the conventional AMI systems. The acoustic frequency used in practice, however, is limited by its penetration through materials. In this paper, a novel acoustic microimaging technique, which utilizes nonlinear signal processing techniques to improve the resolution and robustness of conventional AMI, is proposed and investigated. The technique is based on the concept of sparse signal representations in overcomplete time-frequency dictionaries. Simulation and experimental results show its super resolution and high robustness.

Circuit models for power bus structures on printed circuit boards using a hybrid FEM-SPICE method

Abstract: Power bus structures consisting of two parallel conducting planes are widely used on high-speed printed circuit boards In this paper, a full-wave finite-element method (FEM) method is used to analyze power bus structures, and the resulting matrix equations are converted to equivalent circuits that can be analyzed using SPICE programs Using this method of combining FEM and SPICE, power bus structures of arbitrary shape can be modeled efficiently both in the time-domain and frequency-domain, along with the circuit components connected to the bus Dielectric loss and losses due to the finite resistance of the power planes can also be modeled Practical examples are presented to validate this method

Comprehensive dynamic analysis of wirebonding on Cu/low-K wafers

Abstract: Comprehensive dynamic analysis is performed in this paper to simulate wirebonding on Cu/low-K wafers, which involves both the impact and the ultrasonic vibration stages. After the impact stage, the contact region between the pad and the gold ball is welded to allow subsequent ultrasonic vibrations to take place. Parametric studies are carried out to investigate structural responses of the Cu/low-K layer due to variation of the moduli of Cu/low-K components.

Effect of Chromium–Gold and Titanium–Titanium Nitride–Platinum–Gold Metallization on Wire/Ribbon Bondability

Abstract: Gold metallization on wafer substrates for wire/ribbon bond applications requires good bond strength to the substrate without weakening the wire/ribbon. This paper compares the ribbon bondability of Cr-Au and Ti-TiN-Pt-Au metallization systems for an optoelectronic application. Both Chromium and Titanium are used to promote adhesion between semiconductor substrates and sputtered gold films. However, both will be oxidized if they diffuse to the gold surface and result in the degradation of the wire/ribbon bondability. Restoring bondability by ceric ammonium nitrate (CAN) etch was investigated. Experiments were conducted to investigate the effect of Cr-Au and Ti-TiN-Pt-Au, annealing, and CAN etch processes, on 25.4times254 mum (1 times 10 mil) ribbon bonding. All bonds were evaluated by noting pull strengths and examining specific failure modes. The results show that there is no significant difference in bondability between Cr-Au and Ti-TiN-Pt-Au before the annealing process. At this point, excellent bond strength can be achieved. However, wire/ribbon bondability of Cr-Au degraded after the wafers were annealed. The experimental results also show that a CAN etch can remove Cr oxide, and that the improvement in wire/ribbon bondability of Cr-Au depends on the CAN etch time. It is further demonstrated that the same annealing process does not have a significant effect on the bondability of Ti-TiN-Pt-Au metallization on the same type substrate materials. Auger electron spectroscopy was used to investigate the causes of the difference in bondability between these two metallizations

Cavity resonance suppression in power delivery systems using electromagnetic band gap structures

Abstract: The utilization of electromagnetic band gap (EBG) structures is a new and promising approach in plane pair noise cavity resonance suppression. In this paper, EBG/plane pair structures are studied with full-wave methods and results are experimentally verified. A new equivalent circuit modeling approach of characterizing the frequency behavior of the entire EBG/plane pair structure is presented. The equivalent circuit of the unit cell is proposed and the procedure to extract circuit parameters is described. The influence of EBG patch parameters on the band gap characteristics is quantified and the results provide some design rules to circuit designers. Examples of applications of EBG structures to power/ground plane noise suppression are given.

High- $Q$ Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA

Abstract: High-Q inductors are important for the realization of high-performance, low-power RF-circuits. In this paper, on-chip inductors with Q-factors above 40 have been realized above the passivation of a 90-nm RF-CMOS process using wafer-level packaging (WLP) techniques . The influence of a patterned polysilicon and metal ground shield on the inductor-Q is compared and the influence of highly doped active area underneath the inductors is shown. A 5-15 GHz above-IC balun has been realized on 20 Omegamiddotcm silicon with the use of patterned ground shield. The technology is demonstrated by a low-power 90-nm RF-CMOS 5-GHz VCO with a core current consumption of only 150 muA with a 1.2-V supply, and a 10% tuning range with a worst case phase noise of -111 dBc/Hz at 1-MHz offset. A 24-GHz single-stage common-source low-noise amplifier has been realized, with a noise figure of 3.2 dB, a gain of 7.5 dB, and a low power consumption of 10.6 mW