Showing papers in "IEEE Transactions on Biomedical Circuits and Systems in 2011"

Design and Optimization of Resonance-Based Efficient Wireless Power Delivery Systems for Biomedical Implants

Abstract: Resonance-based wireless power delivery is an efficient technique to transfer power over a relatively long distance. This technique typically uses four coils as opposed to two coils used in conventional inductive links. In the four-coil system, the adverse effects of a low coupling coefficient between primary and secondary coils are compensated by using high-quality (Q) factor coils, and the efficiency of the system is improved. Unlike its two-coil counterpart, the efficiency profile of the power transfer is not a monotonically decreasing function of the operating distance and is less sensitive to changes in the distance between the primary and secondary coils. A four-coil energy transfer system can be optimized to provide maximum efficiency at a given operating distance. We have analyzed the four-coil energy transfer systems and outlined the effect of design parameters on power-transfer efficiency. Design steps to obtain the efficient power-transfer system are presented and a design example is provided. A proof-of-concept prototype system is implemented and confirms the validity of the proposed analysis and design techniques. In the prototype system, for a power-link frequency of 700 kHz and a coil distance range of 10 to 20 mm, using a 22-mm diameter implantable coil resonance-based system shows a power-transfer efficiency of more than 80% with an enhanced operating range compared to ~40% efficiency achieved by a conventional two-coil system.

Design and Optimization of a 3-Coil Inductive Link for Efficient Wireless Power Transmission

Abstract: Inductive power transmission is widely used to energize implantable microelectronic devices (IMDs), recharge batteries, and energy harvesters. Power transfer efficiency (PTE) and power delivered to the load (PDL) are two key parameters in wireless links, which affect the energy source specifications, heat dissipation, power transmission range, and interference with other devices. To improve the PTE, a 4-coil inductive link has been recently proposed. Through a comprehensive circuit-based analysis that can guide a design and optimization scheme, we have shown that despite achieving high PTE at larger coil separations, the 4-coil inductive links fail to achieve a high PDL. Instead, we have proposed a 3-coil inductive power transfer link with comparable PTE over its 4-coil counterpart at large coupling distances, which can also achieve high PDL. We have also devised an iterative design methodology that provides the optimal coil geometries in a 3-coil inductive power transfer link. Design examples of 2-, 3-, and 4-coil inductive links have been presented, and optimized for a 13.56-MHz carrier frequency and 12-cm coupling distance, showing PTEs of 15%, 37%, and 35%, respectively. At this distance, the PDL of the proposed 3-coil inductive link is 1.5 and 59 times higher than its equivalent 2- and 4-coil links, respectively. For short coupling distances, however, 2-coil links remain the optimal choice when a high PDL is required, while 4-coil links are preferred when the driver has large output resistance or small power is needed. These results have been verified through simulations and measurements.

Sensor Positioning for Activity Recognition Using Wearable Accelerometers

Abstract: Activities of daily living are important for assessing changes in physical and behavioral profiles of the general population over time, particularly for the elderly and patients with chronic diseases. Although accelerometers have been used widely in wearable devices for activity classification, the positioning of the sensors and the selection of relevant features for different activity groups still pose significant research challenges. This paper investigates wearable sensor placement at different body positions and aims to provide a systematic framework that can answer the following questions: 1) What is the ideal sensor location for a given group of activities? and 2) Of the different time-frequency features that can be extracted from wearable accelerometers, which ones are the most relevant for discriminating different activity types?

A $160~\mu {\rm W}$ 8-Channel Active Electrode System for EEG Monitoring

Abstract: This paper presents an active electrode system for gel-free biopotential EEG signal acquisition. The system consists of front-end chopper amplifiers and a back-end common-mode feedback (CMFB) circuit. The front-end AC-coupled chopper amplifier employs input impedance boosting and digitally-assisted offset trimming. The former increases the input impedance of the active electrode to 2 GΩ at 1 Hz and the latter limits the chopping induced output ripple and residual offset to 2 mV and 20 mV, respectively. Thanks to chopper stabilization, the active electrode achieves 0.8 μVrms (0.5-100 Hz) input referred noise. The use of a back-end CMFB circuit further improves the CMRR of the active electrode readout to 82 dB at 50 Hz. Both front-end and back-end circuits are implemented in a 0.18 μm CMOS process and the total current consumption of an 8-channel readout system is 88 μA from 1.8 V supply. EEG measurements using the proposed active electrode system demonstrate its benefits compared to passive electrode systems, namely reduced sensitivity to cable motion artifacts and mains interference.

SoC CMOS UWB Pulse Radar Sensor for Contactless Respiratory Rate Monitoring

Abstract: An ultra wideband (UWB) system-on-chip radar sensor for respiratory rate monitoring has been realized in 90 nm CMOS technology and characterized experimentally. The radar testchip has been applied to the contactless detection of the respiration activity of adult and baby. The field operational tests demonstrate that the UWB radar sensor detects the respiratory rate of person under test (adult and baby) associated with sub-centimeter chest movements, allowing the continuous-time non-invasive monitoring of hospital patients and other people at risk of obstructive apneas such as babies in cot beds, or other respiratory diseases.

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

Abstract: This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 μVrms and the power consumption is 7.92 μW from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are - 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 μm × 256 μm in 0.18-μm complementary metal-oxide semiconductor technology.

A Low-Power 32-Channel Digitally Programmable Neural Recording Integrated Circuit

Abstract: We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm2 and 0.02 mm2 respectively, making our design simultaneously area efficient and power efficient, thus enabling scaling to high channel-count systems.

Floating Gate Synapses With Spike-Time-Dependent Plasticity

Abstract: This paper describes a single transistor floating-gate synapse device that can be used to store a weight in a nonvolatile manner, compute a biological EPSP, and demonstrate biological learning rules such as Long-Term Potentiation, LTD, and spike-time dependent plasticity. We also describe a highly scalable architecture of a matrix of synapses to implement the described learning rules. Parameters for weight update in the 0.35 um process have been extracted and can be used to predict the change in weight based on time difference between pre- and post-synaptic spike times.

Modeling of the Lung Impedance Using a Fractional-Order Ladder Network With Constant Phase Elements

Abstract: The self similar branching arrangement of the airways makes the respiratory system an ideal candidate for the application of fractional calculus theory. The fractal geometry is typically characterized by a recurrent structure. This study investigates the identification of a model for the respiratory tree by means of its electrical equivalent based on intrinsic morphology. Measurements were obtained from seven volunteers, in terms of their respiratory impedance by means of its complex representation for frequencies below 5 Hz. A parametric modeling is then applied to the complex valued data points. Since at low-frequency range the inertance is negligible, each airway branch is modeled by using gamma cell resistance and capacitance, the latter having a fractional-order constant phase element (CPE), which is identified from measurements. In addition, the complex impedance is also approximated by means of a model consisting of a lumped series resistance and a lumped fractional-order capacitance. The results reveal that both models characterize the data well, whereas the averaged CPE values are supraunitary and subunitary for the ladder network and the lumped model, respectively.

A 2.4 GHz ULP OOK Single-Chip Transceiver for Healthcare Applications

Abstract: This paper describes an ultra-low power (ULP) single chip transceiver for wireless body area network (WBAN) applications. It supports on-off keying (OOK) modulation, and it operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands. It is implemented in 90 nm CMOS technology. The direct modulated transmitter transmits OOK signal with 0 dBm peak power, and it consumes 2.59 mW with 50% OOK. The transmitter front-end supports up to 10 Mbps. The transmitter digital baseband enables digital pulse-shaping to improve spectrum efficiency. The super-regenerative receiver front-end supports up to 5 Mbps with -75 dBm sensitivity. Including the digital part, the receiver consumes 715 μW at 1 Mbps data rate, oversampled at 3 MHz. At the system level the transceiver achieves PER=10 -2 at 25 meters line of site with 62.5 kbps data rate and 288 bits packet size. The transceiver is integrated in an electrocardiogram (ECG) necklace to monitor the heart's electrical property.

A Power-Efficient Neural Tissue Stimulator With Energy Recovery

Abstract: This paper presents a power-efficient neural stimulator integrated circuit, designed to take advantage of our understanding of iridium-oxide electrode impedance. It efficiently creates a programmable set of voltage supplies directly from a secondary power telemetry coil, then switches the target electrode sequentially through the voltage steps. This sequence of voltages mimics the voltage of the electrode under the constant current drive, resulting in approximately constant current without the voltage drop of the more commonly used linear current source. This method sacrifices some precision, but drastically reduces the series losses seen in traditional current sources and attains power savings of 53%-66% compared to these designs. The proof-of-concept circuit consumes 125 μW per electrode and was fabricated in a 1.5-μm CMOS process, in a die area of 4.76 mm2.

Wireless Sensor Networks for Monitoring Physiological Signals of Multiple Patients

Abstract: This paper presents the design of a novel wireless sensor network structure to monitor patients with chronic diseases in their own homes through a remote monitoring system of physiological signals. Currently, most of the monitoring systems send patients' data to a hospital with the aid of personal computers (PC) located in the patients' home. Here, we present a new design which eliminates the need for a PC. The proposed remote monitoring system is a wireless sensor network with the nodes of the network installed in the patients' homes. These nodes are then connected to a central node located at a hospital through an Internet connection. The nodes of the proposed wireless sensor network are created by using a combination of ECG sensors, MSP430 microcontrollers, a CC2500 low-power wireless radio, and a network protocol called the SimpliciTI protocol. ECG signals are first sampled by a small portable device which each patient carries. The captured signals are then wirelessly transmitted to an access point located within the patients' home. This connectivity is based on wireless data transmission at 2.4-GHz frequency. The access point is also a small box attached to the Internet through a home asynchronous digital subscriber line router. Afterwards, the data are sent to the hospital via the Internet in real time for analysis and/or storage. The benefits of this remote monitoring are wide ranging: the patients can continue their normal lives, they do not need a PC all of the time, their risk of infection is reduced, costs significantly decrease for the hospital, and clinicians can check data in a short time.

Wireless Neural/EMG Telemetry Systems for Small Freely Moving Animals

Abstract: We have developed miniature telemetry systems that capture neural, EMG, and acceleration signals from a freely moving insect or other small animal and transmit the data wirelessly to a remote digital receiver. The systems are based on custom low-power integrated circuits (ICs) that amplify, filter, and digitize four biopotential signals using low-noise circuits. One of the chips also digitizes three acceleration signals from an off-chip microelectromechanical-system accelerometer. All information is transmitted over a wireless ~ 900-MHz telemetry link. The first unit, using a custom chip fabricated in a 0.6- μm BiCMOS process, weighs 0.79 g and runs for two hours on two small batteries. We have used this system to monitor neural and EMG signals in jumping and flying locusts as well as transdermal potentials in weakly swimming electric fish. The second unit, using a custom chip fabricated in a 0.35-μ m complementary metal-oxide semiconductor CMOS process, weighs 0.17 g and runs for five hours on a single 1.5-V battery. This system has been used to monitor neural potentials in untethered perching dragonflies.

A Programmable Implantable Microstimulator SoC With Wireless Telemetry: Application in Closed-Loop Endocardial Stimulation for Cardiac Pacemaker

Abstract: A low-power, wireless, and implantable microstimulator system on chip with smart powering management, immediate neural signal acquisition, and wireless rechargeable system is proposed. A system controller with parity checking handles the adjustable stimulus parameters for the stimulated objective. In the current paper, the rat's intra-cardiac electrogram is employed as the stimulated model in the animal study, and it is sensed by a low-voltage and low-power monitoring analog front end. The power management unit, which includes a rectifier, battery charging and detection, and a regulator, is used for the power control of the internal circuits. The stimulation data and required clock are extracted by a phase-locked-loop-based phase shift keying demodulator from an inductive AC signal. The full chip, which consumes 48 μW only, is fabricated in a TSMC 0.35 μm 2P4M standard CMOS process to perform the monitoring and pacing functions with inductively powered communication in the in vivo study.

Pulse-Modulation Imaging—Review and Performance Analysis

Abstract: In time-domain or pulse-modulation (PM) imaging, the incident light intensity is not encoded in amounts of charge, voltage, or current as it is in conventional image sensors. Instead, the image data are represented by the timing of pulses or pulse edges. This method of visual information encoding optimizes the phototransduction individually for each pixel by abstaining from imposing a fixed integration time for the entire array. Exceptionally high dynamic range (DR) and improved signal-to-noise ratio (SNR) are immediate benefits of this approach. In particular, DR is no longer limited by the power-supply rails as in conventional complementary metal-oxide semiconductor (CMOS) complementary metal-oxide semiconductor active pixel sensors, thus providing relative immunity to the supply-voltage scaling of modern CMOS technologies. In addition, PM imaging naturally supports pixel-parallel analog-to-digital conversion, thereby enabling high temporal resolution/frame rates or an asynchronous event-based array readout. The applications of PM imaging in emerging areas, such as sensor network, wireless endoscopy, retinal prosthesis, polarization imaging, and energy harvesting are surveyed to demonstrate the effectiveness of PM imaging in low-power, high-performance machine vision, and biomedical applications of the future. The evolving design innovations made in PM imaging, such as high-speed arbitration circuits and ultra-compact processing elements, are expected to have even wider impacts in disciplines beyond CMOS image sensors. This paper thoroughly reviews and classifies all common PM image sensor architectures. Analytical models and a universal figure of merit - image quality and dynamic range to energy complexity factor are proposed to quantitatively assess different PM imagers across the entire spectrum of PM architectures.

A CMOS In-Pixel CTIA High-Sensitivity Fluorescence Imager

Abstract: Traditionally, charge-coupled device (CCD)-based image sensors have held sway over the field of biomedical imaging. Complementary metal-oxide semiconductor (CMOS)-based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility, and compactness of CMOS imagers. We present a 132 × 124 high sensitivity imager array with a 20.1-μ m pixel pitch fabricated in a standard 0.5- μm CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA)-based in-pixel amplification, pixel scanners, and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 frames/s, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3-V supply. The peak signal-to-noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4 × 4 binning allowed the frame rate to be increased to 675 frames/s. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 frames/s. The chip was used to image single-cell fluorescence at 28 frames/s with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 frames/s with an average SNR of 33.2 dB under the same illumination while consuming more than a watt.

A Novel Low-Power-Implantable Epileptic Seizure-Onset Detector

Abstract: A novel implantable low-power integrated circuit is proposed for real-time epileptic seizure detection. The presented chip is part of an epilepsy prosthesis device that triggers focal treatment to disrupt seizure progression. The proposed chip integrates a front-end preamplifier, voltage-level detectors, digital demodulators, and a high-frequency detector. The preamplifier uses a new chopper stabilizer topology that reduces instrumentation low-frequency and ripple noises by modulating the signal in the analog domain and demodulating it in the digital domain. Moreover, each voltage-level detector consists of an ultra-low-power comparator with an adjustable threshold voltage. The digitally integrated high-frequency detector is tunable to recognize the high-frequency activities for the unique detection of seizure patterns specific to each patient. The digitally controlled circuits perform accurate seizure detection. A mathematical model of the proposed seizure detection algorithm was validated in Matlab and circuits were implemented in a 2 mm2 chip using the CMOS 0.18- μm process. The proposed detector was tested by using intracerebral electroencephalography (icEEG) recordings from seven patients with drug-resistant epilepsy. The seizure signals were assessed by the proposed detector and the average seizure detection delay was 13.5 s, well before the onset of clinical manifestations. The measured total power consumption of the detector is 51 μW.

Exponential Current Pulse Generation for Efficient Very High-Impedance Multisite Stimulation

Abstract: We describe in this paper an intracortical current-pulse generator for high-impedance microstimulation. This dual-chip system features a stimuli generator and a high-voltage electrode driver. The stimuli generator produces flexible rising exponential pulses in addition to standard rectangular stimuli. This novel stimulation waveform is expected to provide superior energy efficiency for action potential triggering while releasing less toxic reduced ions in the cortical tissues. The proposed fully integrated electrode driver is used as the output stage where high-voltage supplies are generated on-chip to significantly increase the voltage compliance for stimulation through high-impedance electrode-tissue interfaces. The stimuli generator has been implemented in 0.18-μm CMOS technology while a 0.8-μm CMOS/DMOS process has been used to integrate the high-voltage output stage. Experimental results show that the rectangular pulses cover a range of 1.6 to 167.2 μA with a DNL and an INL of 0.098 and 0.163 least-significant bit, respectively. The maximal dynamic range of the generated exponential reaches 34.36 dB at full scale within an error of ± 0.5 dB while all of its parameters (amplitude, duration, and time constant) are independently programmable over wide ranges. This chip consumes a maximum of 88.3 μ W in the exponential mode. High-voltage supplies of 8.95 and -8.46 V are generated by the output stage, boosting the voltage swing up to 13.6 V for a load as high as 100 kΩ.

CMOS Amperometric Instrumentation and Packaging for Biosensor Array Applications

Abstract: An integrated CMOS amperometric instrument with on-chip electrodes and packaging for biosensor arrays is presented. The mixed-signal integrated circuit supports a variety of electrochemical measurement techniques including linear sweep, constant potential, cyclic and pulse voltammetry. Implemented in 0.5 μm CMOS, the 3 × mm2 chip dissipates 22.5 mW for a 200 kHz clock. The highly programmable chip provides a wide range of user-controlled stimulus rate and amplitude settings with a maximum scan range of 2 V and scan rates between 1 mV/sec and 400 V/sec. The amperometric readout circuit provides ±500 fA linear resolution and supports inputs up to ±47 μA. A 2 × 2 gold electrode array was fabricated on the surface of the CMOS instrumentation chip. An all-parylene packaging scheme was developed for compatibility with liquid test environments as well as a harsh piranha electrode cleaning process. The chip was tested using cyclic voltammetry of different concentrations of potassium ferricyanide at 100 mV/s and 200 mV/s, and results were identical to measurements using commercial instruments.

An Area and Power-Efficient Analog Li-Ion Battery Charger Circuit

Abstract: The demand for greater battery life in low-power consumer electronics and implantable medical devices presents a need for improved energy efficiency in the management of small rechargeable cells. This paper describes an ultra-compact analog lithium-ion (Li-ion) battery charger with high energy efficiency. The charger presented here utilizes the tanh basis function of a subthreshold operational transconductance amplifier to smoothly transition between constant-current and constant-voltage charging regimes without the need for additional area- and power-consuming control circuitry. Current-domain circuitry for end-of-charge detection negates the need for precision-sense resistors in either the charging path or control loop. We show theoretically and experimentally that the low-frequency pole-zero nature of most battery impedances leads to inherent stability of the analog control loop. The circuit was fabricated in an AMI 0.5-μm complementary metal-oxide semiconductor process, and achieves 89.7% average power efficiency and an end voltage accuracy of 99.9% relative to the desired target 4.2 V, while consuming 0.16 mm2 of chip area. To date and to the best of our knowledge, this design represents the most area-efficient and most energy-efficient battery charger circuit reported in the literature.

Ratiometric Artifact Reduction in Low Power Reflective Photoplethysmography

Abstract: This paper presents effective signal-processing techniques for the compensation of motion artifacts and ambient light offsets in a reflective photoplethysmography sensor suitable for wearable applications. A ratiometric comparison of infrared (IR) and red absorption characteristics cancels out noise that is multiplicative in nature and amplitude modulation of pulsatile absorption signals enables rejection of additive noise. A low-power, discrete-time pulse-oximeter platform is used to capture IR and red photoplethysmograms so that the data used for analysis have noise levels representative of what a true body sensor network device would experience. The proposed artifact rejection algorithm is designed for real-time implementation with a low-power microcontroller while being robust enough to compensate for varying levels in ambient light as well as reducing the effects of motion-induced artifacts. The performance of the system is illustrated by its ability to extract a typical plethysmogram heart-rate waveform since the sensor is subjected to a range of physical disturbances.

Spike Latency Coding in Biologically Inspired Microelectronic Nose

Abstract: Recent theoretical and experimental findings suggest that biological olfactory systems utilize relative latencies or time-to-first spikes for fast odor recognition. These time-domain encoding methods exhibit reduced computational requirements and improved classification robustness. In this paper, we introduce a microcontroller-based electronic nose system using time-domain encoding schemes to achieve a power-efficient, compact, and robust gas identification system. A compact (4.5 cm × 5 cm × 2.2 cm) electronic nose, which is integrated with a tin-oxide gas-sensor array and capable of wireless communication with computers or mobile phones through Bluetooth, was implemented and characterized by using three different gases (ethanol, carbon monoxide, and hydrogen). During operation, the readout circuit digitizes the gas-sensor resistances into a concentration-independent spike timing pattern, which is unique for each individual gas. Both sensing and recognition operations have been successfully demonstrated in hardware. Two classification algorithms (rank order and spike distance) have been implemented. Both algorithms do not require any explicit knowledge of the gas concentration to achieve simplified training procedures, and exhibit comparable performances with conventional pattern-recognition algorithms while enabling hardware-friendly implementation.

A Library of Analog Operators Based on the Hodgkin-Huxley Formalism for the Design of Tunable, Real-Time, Silicon Neurons

Abstract: In this paper, we present a library of analog operators used for the analog real-time computation of the Hodgkin-Huxley formalism. These operators make it possible to design a silicon (Si) neuron that is dynamically tunable, and that reproduces different kinds of neurons. We used an original method in neuromorphic engineering to characterize this Si neuron. In electrophysiology, this method is well known as the “voltage-clamp” technique. We also compare the features of an application-specific integrated circuit built with this library with results obtained from software simulations. We then present the complex behavior of neural membrane voltages and the potential applications of this Si neuron.

A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System

Abstract: The bulkiness of current electronic nose (E-Nose) systems severely limits their portability. This study designed and fabricated an E-Nose signal-processing chip by using TSMC 0.18-μ m 1P6M complementary metal-oxide semiconductor technology to overcome the need to connect the device to a personal computer, which has traditionally been a major stumbling block in reducing the size of E-Nose systems. The proposed chip is based on a conductive polymer sensor array chip composed of multiwalled carbon nanotubes. The signal-processing chip comprises an interface circuit, an analog-to-digital converter, a memory module, and a microprocessor embedded with a pattern-recognition algorithm. Experimental results have verified the functionality of the proposed system, in which the E-Nose signal-processing chip successfully classified three odors, carbon tetrachloride (CCl4), chloroform (CHCl3), and 2-Butanone (MEK), demonstrating its potential for portable applications. The power consumption of this signal-processing chip was maintained at a very low 2.81 mW using a 1.8-V power supply, making it highly suitable for integration as an electronic nose system-on-chip.

Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture

Abstract: A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

Adaptive Resolution ADC Array for an Implantable Neural Sensor

Abstract: This paper describes an analog-to-digital converter (ADC) array for an implantable neural sensor which digitizes neural signals sensed by a microelectrode array. The ADC array consists of 96 variable resolution ADC base cells. The resolution of each ADC cell in the array is varied according to neural data content of the signal from the corresponding electrode. The resolution adaptation algorithm is essentially to periodically recalibrate the required resolution and this is done without requiring any additional ADC cells. The adaptation implementation and results are described. The base ADC cell is implemented using a successive approximation charge redistribution architecture. The choice of architecture and circuit design are presented. The base ADC has been implemented in 0.13 μm CMOS as a 100 kS/s SAR ADC whose resolution can be varied from 3 to 8 bits with corresponding power consumption of 0.23 μW to 0.90 μW achieving an ENOB of 7.8 at the 8-bit setting. The energy per conversion step figure of merit is 48 fJ/step at the 8-bit setting. Resolution adaptation reduces power consumption by a factor of 2.3 for typical motor neuron signals while maintaining an effective 7.8-bit resolution across all channels.

Two-Dimensional Multi-Channel Neural Probes With Electronic Depth Control

Abstract: This paper presents multi-electrode arrays for in vivo neural recording applications incorporating the principle of electronic depth control (EDC), i.e., the electronic selection of recording sites along slender probe shafts independently for multiple channels. Two-dimensional (2D) arrays were realized using a commercial 0.5- μm complementary-metal-oxide-semiconductor (CMOS) process for the EDC circuits combined with post-CMOS micromachining to pattern the comb-like probes and the corresponding electrode metallization. A dedicated CMOS integrated front-end circuit was developed for pre-amplification and multiplexing of the neural signals recorded using these probes.

Global and Robust Stability Analysis of Genetic Regulatory Networks With Time-Varying Delays and Parameter Uncertainties

Abstract: The study of stability is essential for designing or controlling genetic regulatory networks. This paper addresses global and robust stability of genetic regulatory networks with time delays and parameter uncertainties. Most existing results on this issue are based on the linear matrix inequalities (LMIs) approach, which results in checking the existence of a feasible solution to high dimensional LMIs. Based on M-matrix theory, we will present several novel global stability conditions for genetic regulatory networks with time-varying and time-invariant delays. All of these stability conditions are given in terms of M-matrices, for which there are many and very easy ways to be verified. Then, we extend these results to genetic regulatory networks with time delays and parameter uncertainties. To illustrate the effectiveness of our theoretical results, several genetic regulatory networks are analyzed. Compared with existing results in the literature, we also show that our results are less conservative than existing ones with these illustrative genetic regulatory networks.

A Low-Power Bidirectional Telemetry Device With a Near-Field Charging Feature for a Cardiac Microstimulator

Abstract: In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted cardiac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump circuit are included to generate a stable, low-voltage, and high-potential supply voltage, respectively. A miniature digital processor includes a phase-shift-keying (PSK) demodulator to decode the transmission data and a self-protective system controller to operate the entire system. To acquire the cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs immediate threshold detection and data conversion. In addition, the pacing circuit, which consists of a pulse generator (PG) and its digital-to-analog (D/A) controller, is responsible for stimulating heart tissue. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) with 0.35-μm complementary metal-oxide semiconductor technology to perform the monitoring and pacing functions with inductively powered communication. Using a model with lead and heart tissue on measurement, a -5-V pulse at a stimulating frequency of 60 beats per minute (bpm) is delivered while only consuming 31.5 μW of power.

A Stimulator ASIC Featuring Versatile Management for Vestibular Prostheses

Abstract: This paper presents a multichannel stimulator ASIC for an implantable vestibular prosthesis. The system features versatile stimulation management which allows fine setting of the parameters for biphasic stimulation pulses. To address the problem of charge imbalance due to rounding errors, the digital processor can calculate and provide accurate charge correction. A technique to reduce the data rate to the stimulator is described. The stimulator ASIC was implemented in 0.6-μ m high-voltage CMOS technology occupying an area of 2.27 mm2. The measured performance of the ASIC has been verified using vestibular electrodes in saline.