Showing papers in "IEEE Transactions on Circuits and Systems in 1989"
TL;DR: In this article, the adaptive weighted median filter (AWMF) is proposed for reducing speckle noise in medical ultrasonic images. But it is not suitable for image segmentation.
Abstract: A method for reducing speckle noise in medical ultrasonic images is presented. It is called the adaptive weighted median filter (AWMF) and is based on the weighted median, which originates from the well-known median filter through the introduction of weight coefficients. By adjusting the weight coefficients and consequently the smoothing characteristics of the filter according to the local statistics around each point of the image, it is possible to suppress noise while edges and other important features are preserved. Application of the filter to several ultrasonic scans has shown that processing improves the detectability of small structures and subtle gray-scale variations without affecting the sharpness or anatomical information of the original image. Comparison with the pure median filter demonstrates the superiority of adaptive techniques over their space-invariant counterparts. Examples of processed images show that the AWMF preserves small details better than other nonlinear space-varying filters which offer equal noise reduction in uniform areas. >
715 citations
TL;DR: In this paper, an improved algorithm is presented for the discrete optimization of finite-impulse response (FIR) digital filter coefficients which are represented by a canonic signed-digit (CSD) code, i.e., numbers representable as sums or differences of powers of two.
Abstract: An improved algorithm is presented for the discrete optimization of finite-impulse-response (FIR) digital filter coefficients which are represented by a canonic signed-digit (CSD) code, ie, numbers representable as sums or differences of powers-of-two The proposed search algorithm allocates an extra nonzero digit in the CSD code to the larger coefficients to compensate for the very nonuniform nature of the CSD coefficient distribution This results in a small increase in the filter complexity; however, the improvement in the frequency response is substantial The coefficient optimization is performed in two stages The first stage searches for an optimum scale factor and the second stage consists of a local bivariate search in the neighborhood of the scaled and rounded coefficients >
447 citations
TL;DR: In this article, a family of modular VLSI architectures and chip implementations of the motion-compensation full-search block-matching algorithm are described, motivated by the intensive computations required to perform motion compensation in real time.
Abstract: A family of modular VLSI architectures and chip implementations of the motion-compensation full-search block-matching algorithm are described. This set of application-specific integrated circuits is motivated by the intensive computations required to perform motion compensation in real time. The architectures are based on data-flow designs, which allow sequential inputs but perform parallel processing with 100% efficiency. On the basis of these architectures, a programmable chip can be designed for motion vector estimation with different block sizes. The chips can be cascaded for a larger tracking range or for a video source with a higher pixel sampling rate. A chip-pair design is also derived for calculating fractional motion vectors with quarter-pel precision. The chip-pair design has been laid out, and the chip characteristics are given. Test circuitry is also included to increase the testability of the chips. >
369 citations
TL;DR: In this paper, a description of VLSI architectures for block-matching algorithms utilizing systolic array processors is given, and a well-known mapping procedure has been applied to derive the array processors from the algorithm.
Abstract: A description is given of VLSI architectures for block-matching algorithms utilizing systolic array processors. A well-known mapping procedure has been applied to derive the array processors from the algorithm. Examples of two- and one-dimensional systolic arrays are presented. The transistor-count of the architectures using presently available CMOS technology and their maximum processable frame rates for real-time computation of video signals have been estimated. >
349 citations
TL;DR: Results from the qualitative theory of large-scale interconnected dynamical systems are surveyed and utilized to develop a qualitative theory for the Hopfield model of neural networks, which will make them highly useful as constraints in synthesis or design procedures.
Abstract: Results from the qualitative theory of large-scale interconnected dynamical systems are surveyed and utilized to develop a qualitative theory for the Hopfield model of neural networks. Such networks are viewed as an interconnection of many single neurons. The results are phrased in terms of the qualitative properties of the individual neurons and in terms of the properties of the interconnecting structure of the neural networks. This method of analysis makes it frequently possible to circumvent difficulties usually encountered in the analysis of complex systems with high dimension. Aspects of neural networks which are addressed include asymptotic stability, exponential stability, and instability of an equilibrium; estimates of trajectory bounds; estimates of the domain of attraction of an asymptotically stable equilibrium: and stability of neural networks under structural perturbations (arising, e.g. during adaptive learning schemes). The results are not overly conservative. Furthermore, they are in a form which will make them highly useful as constraints in synthesis or design procedures. >
328 citations
TL;DR: A proof is given that the maximum number of separable regions (M) in the input space is a function of both H and input space dimension (d).
Abstract: Recent results indicate that the number of hidden nodes (H) in a feedforward neural net depend only on the number of input training patterns (T). There appear to be conjectures that H is on the order of T-1 and of log/sub 2/T. A proof is given that the maximum number of separable regions (M) in the input space is a function of both H and input space dimension (d). The authors also show that H=M -1 and H=log/sub 2/M are special cases of that formulation. M defines a lower bound on T, the number of input patterns that may be used for training. Application to some experiments are investigated. >
285 citations
TL;DR: It is shown that for small changes around the optimum solution, the proposed update algorithm approximates the Gauss-Newton update without requiring a matrix inversion, and the transient response is approximately independent of the number of sinusoids or their power levels.
Abstract: A constrained adaptive infinite-impulse-response (IIR) filter consisting of a cascade of biquadratic notch sections is used to track multiple sinusoids. The structure can be used to isolate individual sinusoids. It is shown that for small changes around the optimum solution, the proposed update algorithm approximates the Gauss-Newton update without requiring a matrix inversion. Furthermore, the transient response is approximately independent of the number of sinusoids or their power levels. Important adaptive line enhancement performance criteria, such as signal-to-noise improvement ratio and the bias in the frequency estimate assuming white noise, are derived for the single-sinusoid case. Computer simulations are used to demonstrate the performance of the notch filter under a wide range of conditions. >
256 citations
TL;DR: In this article, the authors propose a VLSI implementation of the full-search block-matching algorithm using linear arrays in conjunction with compact memory blocks based on three-transistor cells.
Abstract: Systolic VLSI architectures for implementing the full-search block-matching algorithm are described. A large range of data rates can be efficiently covered by the proposed architectures. The input bandwidth problem for the search-area data is solved by on-chip line buffers, allowing a low frame-buffer access rate. An architecture for block-scan data input is described in detail. A VLSI realization with a low transistor count can be achieved by linear arrays in conjunction with compact memory blocks based on three-transistor cells. >
254 citations
TL;DR: An investigation was conducted of the qualitative properties of a class of neural networks described by a system of first-order linear ordinary differential equations defined on a closed hypercube of the state space with solutions extended to the boundary of the hypercube.
Abstract: An investigation was conducted of the qualitative properties of a class of neural networks described by a system of first-order linear ordinary differential equations which are defined on a closed hypercube of the state space with solutions extended to the boundary of the hypercube. When solutions are located on the boundary of the hypercube, the system is said to be in a saturated mode. The class of systems considered retains the basic structure of the Hopfield model but is easier to analyze, synthesize, and implement. An efficient analysis method is developed which can be used to determine completely the set of asymptotically stable equilibrium points and the set of unstable equilibrium points. The latter set can be used to estimate the domains of attraction for the elements of the former set. The class of systems considered can easily be implemented in analog integrated circuits. The applicability of the results is demonstrated by means of several examples. >
250 citations
TL;DR: In this paper, the implementation of a 16*16 discrete cosine transform (DCT) chip using a concurrent architecture is presented, which performs an equivalent of a half billion multiplications and accumulations per second.
Abstract: The implementation of a 16*16 discrete cosine transform (DCT) chip using a concurrent architecture is presented. The chip contains 32 processing elements working in parallel and a random-access memory (RAM) which performs a 16*16 matrix transposition. The structure is highly regular and modular, and thus very efficient for VLSI implementation. The chip was designed for real-time processing of 14.3-MHz sample video data. It performs an equivalent of a half billion multiplications and accumulations per second. Fabricated in 2- mu m double-metal CMOS technology, the chip contains approximately 73000 transistors which occupy a 7.2*7.0-mm/sup 2/ area. The 68-pad die size is 8.3*8.1 mm/sup 2/. It is fully functional and is the first working 16*16 DCT chip. The architecture and accuracy studies for finite-wordlength processing are presented. The circuit design and layout using the symbolic design tool MULGA are described in detail. Possible variations are also discussed for multipurpose (variable transform sizes, forward-inverse transform) applications. >
209 citations
TL;DR: In this paper, a novel learning algorithm is developed for the training of multilayer feedforward neural networks, based on a modification of the Marquardt-Levenberg least-squares optimization method.
Abstract: A novel learning algorithm is developed for the training of multilayer feedforward neural networks, based on a modification of the Marquardt-Levenberg least-squares optimization method. The algorithm updates the input weights of each neuron in the network in an effective parallel way. An adaptive distributed selection of the convergence rate parameter is presented, using suitable optimization strategies. The algorithm has better convergence properties than the conventional backpropagation learning technique. Its performance is illustrated, using examples from digital image halftoning and logical operations such as the XOR function. >
TL;DR: In this paper, the authors considered the problem of constructing a planar grid embedding for G, which maps vertices to distinct grid points and edges to nonintersecting grid paths.
Abstract: The authors consider the problem of constructing a planar grid embedding for G, where G is a planar graph with n vertices, which maps vertices to distinct grid points and edges to nonintersecting grid paths. A new algorithm is presented that runs in O(n) time and produces grid embeddings with the following properties: (1) the total number of bends is at most 2.4n+2; (2) the number of bends along each edge is at most 4; (3) the length of every edge is O(n); and (4) the area of the embedding is O(n/sup 2/). >
TL;DR: In this article, the authors compared five real-valued orthogonal transforms in terms of learning characteristics and computational complexity, and showed that the effect of an ideal transform is to convert equal error contours that are initially hyperellipses in the parameter space into hyperspheres.
Abstract: It has been previously shown that a real-time decomposition of the incoming signal into a set of partially uncorrelated components via an orthogonal transform, and a subsequent adaptation on these individual components, leads to faster convergence rates. Here, transform domain processing is characterized by the effect of the transform on the shape of the mean-square error surface. It is shown that the effect of an ideal transform is to convert equal error contours that are initially hyperellipses in the parameter space into hyperspheres. Five specific real-valued orthogonal transforms are compared in terms of learning characteristics and computational complexity. Since the Karhunen-Loeve transform (KLT) is the ideal transform for this application, and since the KLT is defined in terms of the statistics of the input signal, it is certain that no fixed-parameter transform can deliver optimal learning characteristics for all input signals. However, the simulations suggest that transforms can be found which give much improved performance in a given situation. >
TL;DR: In this paper, the tradeoffs among sampling rate, quantization stepsize, and quantization distortion are examined, and it is shown that symmetric neural networks offer a natural means for efficient implementation of the proposed technique.
Abstract: Various novel techniques for A/D conversion of signals subject to a fidelity criterion are presented, leading to optimum digital representations, in which each signal sample is not necessarily quantized to the closest reconstruction level. Quantization is treated as an optimization problem, and the tradeoffs among sampling rate, quantization stepsize, and quantization distortion are examined. It is shown that symmetric neural networks offer a natural means for efficient implementation of the proposed technique. Applications include digital image halftoning, as well as all forms of PCM coding and oversampled A/D conversion. It is shown that concepts and structures used in digital image halftoning are directly applicable to oversampled sigma-delta modulation of sound signals. A novel kind of parallel analog network is introduced and shown to be appropriate for this task. These networks contain a nonmonotonic nonlinearity in lieu of the sigmoid function and perform error diffusion in all directions. Ideas for massively parallel analog VLSI implementation are offered. >
TL;DR: In this article, the authors present an algorithm that requires a significantly smaller number of comparisons and is significantly faster than the traditional approach to order statistics filtering, and also propose a filter structure for order statistics that is much faster than known sorting structures.
Abstract: Order statistics are used in a variety of filtering techniques (e.g. median, alpha -trimmed mean, nonlinear order statistics filtering, morphological filtering). Their computation is relatively fast, because it requires only comparisons. The author presents an algorithm that requires a significantly smaller number of comparisons and is significantly faster than the traditional approach to order statistics filtering. Also proposed are filter structures for order statistics filtering that are much faster than the known sorting structures. >
TL;DR: It is shown that the function of a stack filter can be realized in k-step recursive use of one binary processing circuit, and the time-area complexity of the proposed filter is O(k) as compared with O(2/sup k/) for stack filters.
Abstract: It is shown that the function of a stack filter can be realized in k-step recursive use of one binary processing circuit. The time-area complexity of the proposed filter is O(k) as compared with O(2/sup k/) for stack filters. The proposed digital realizations are simple and modular in structure, and suitable for VLSI implementation. Analog/digital (A/D) hybrid realizations have the advantage that there is no need for an A/D converter array when the original signals come from an integrated sensor array. An experimental digital rank-order filter with a window size of three and arbitrary number of input bits is designed and implemented in a 3- mu m double-metal polysilicon gate CMOS process. The chip has been fabricated and measurement results are correct with a clock frequency of up to 110 MHz. >
TL;DR: In this paper, a modal scattering parameter formulation for the analysis of transients in coupled transmission lines is presented. But the method is applicable to the case of lossy lines and nonlinear terminations.
Abstract: A novel approach for the analysis of transients in coupled transmission lines is presented. The method uses a modal scattering parameter formulation and is applicable to the case of lossy lines and nonlinear terminations. The advantage of this method over other techniques resides in the computational stability, in its flexibility in the choice of a reference system, and in the simplicity of the solutions in the case where losses are neglected. An analysis of different types of coupled-line problems is presented, and the scattering parameter approach is developed to lead to the solutions for various special cases. Experimental and computer simulations are analyzed in order to evaluate the efficiency, accuracy, and computational speed of the developed scheme. >
TL;DR: A design technique for variable filters with coefficients that are directly computable from the specified spectral parameters is proposed, which expresses the frequency specifications by using a curve-fitting technique.
Abstract: In some applications the frequency characteristics of a filter may be required to change during the course of signal processing. This requirement can be satisfied by filters with coefficients that are directly computable from the specified spectral parameters. Such filters are referred to as variable filters. A design technique for variable filters is proposed. The filter coefficients are expressed as analytical functions of the frequency specifications by using a curve-fitting technique. Several examples are presented to illustrate the method. >
TL;DR: In this paper, a methodology for building very large-scale integrated (VLSI) chips of visual and motor subsystems has been developed using analog micropower circuit elements that can be hierarchically combined.
Abstract: Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems. >
TL;DR: In this paper, a nonlinear dynamic model of the onload tap changers, impedance loads and decoupled reactive power-voltage relations is used to reconstruct the voltage-collapse phenomenon.
Abstract: The destabilizing behavior of onload tap changers (OLTC) is an important mechanism responsible for the voltage collapse of interconnected power systems. A nonlinear dynamic model of the OLTC, impedance loads and decoupled reactive power-voltage relations is used to reconstruct the voltage-collapse phenomenon. Trajectories leading to a monotonic fall of bus voltages are obtained from initial conditions outside the stability region of a simple power network. The construction of voltage stability regions is desirable for the prevention of voltage collapse. Based on the proposed M-bus power network model, this research results in (1) a simple criterion for stability of an equilibrium, and (2) a method to obtain a stability region by forming the union of hyperbox subsets of the true region. The theoretical foundations of the proposed method, i.e., characteristics of the equilibria and monotonic behaviour of system trajectories, are thoroughly studied. >
TL;DR: In this article, the performance of the frequency-domain block least-mean-square (FBLMS) adaptive digital filters, whose filter weights are updated efficiently using the fast Fourier transform, is investigated.
Abstract: The performance of the frequency-domain block least-mean-square (FBLMS) adaptive digital filters, whose filter weights are updated efficiently using the fast Fourier transform, is investigated. In particular, the convergence of the unconstrained FBLMS algorithm with reduced complexity, which is obtained by removing the constraint that has been known to be required in adjusting the frequency-domain weights based on overlap-save sectioning, is analyzed. The performance of the self-orthogonalizing FBLMS algorithm with improved convergence speed, in which different convergence factors normalized by frequency-domain power estimates are used for different frequency components of the weights, is also studied. >
TL;DR: In this article, it was shown that backpropagation is guaranteed to fail in the first example, and likely to fail on the second example, while the perceptron would correctly classify the linearly separable examples.
Abstract: It is widely believed that the back-propagation algorithm in neural networks, for tasks such as pattern classification, overcomes the limitations of the perceptron. The authors construct several counterexamples to this belief. They also construct linearly separable examples which have a unique minimum which fails to separate two families of vectors, and a simple example with four two-dimensional vectors in a single-layer network showing local minima with a large basin of attraction. Thus, back-propagation is guaranteed to fail in the first example, and likely to fail in the second example. It is shown that even multilayered (hidden-layer) networks can also fail in this way to classify linearly separable problems. Since the authors' examples are all linearly separable, the perceptron would correctly classify them. The results disprove the presumption, made in recent years, that, barring local minima, back-propagation will find the best set of weights for a given problem. >
TL;DR: In this article, it was shown that there is no general energy function for multimachine power systems with losses, but there does exist an energy function (defined in a compact set of the state space) which can be incorporated into direct methods for the stability analysis of power system with losses.
Abstract: It is shown that there is no general energy function for multimachine power systems with losses. It is also shown that under the condition of small losses, there does exist an energy function (defined in a compact set of the state space) which can be incorporated into direct methods for the stability analysis of power systems with losses. One implication of the results is that any general procedure attempting to construct an energy function for power systems with losses must include a step serving to check the existence of an energy function. This step would essentially play the same kind of role as the Lyapunov equation plays in determining the stability of an equilibrium point. The results confirm current practice in the area of direct analysis of power system stability for using numerical energy functions. >
TL;DR: In this paper, a switched-capacitor technique for realizing very large time constants is presented, which is insensitive to parasitic capacitances and is very area-efficient and does not require a complicated clocking scheme.
Abstract: A novel switched-capacitor technique for realizing very large time constants is presented. The technique is insensitive to parasitic capacitances and is very area-efficient. It does not require a complicated clocking scheme. The technique yields a complete family of integrators which in turn can be used to realize higher-order filtering functions based on cascaded biquadratic sections or ladder filters. These integrators have been used to implement an experimental 60-Hz notch filter working from a 128-kHz clock. >
TL;DR: In this article, the qualitative properties of a class of neural networks described by a system of first-order ordinary differential equations with discontinuous right hand side were investigated, and an efficient synthesis procedure was developed for this class of networks.
Abstract: An investigation was conducted of the qualitative properties of a class of neural networks described by a system of first-order ordinary differential equations with discontinuous right hand side. An efficient synthesis procedure is developed for this class of neural networks. The class of systems considered may be used as a representation of the analog Hopfield model with the nonlinearities having infinite gain. Also, under appropriate assumptions, the output of the class of systems considered may be viewed as representing the behavior of the discrete Hopfield model. Thus the results give insight into the qualitative behavior of the analog as well as the discrete Hopfield models, and they provide a means of designing such models. The applicability of the present results is demonstrated by several specific examples. >
TL;DR: Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing.
Abstract: A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described. This stochastic architecture provides massive parallelism (since stochastic logic is very space-efficient), reprogrammability (since synaptic weights are stored in digital shift registers), large dynamic range (by using either fixed- or floating-point weights), annealing (by coupling variable neuron gains with noise from stochastic arithmetic), high execution speed ( approximately=N*10/sup 8/ connections per second), expandability (by cascading of multiple chips to host large networks), and practicality (by building with very conservative MOS device technologies). Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing. >
TL;DR: In this paper, the analysis of a more general class E amplifier configuration that can yield results for most of the other classes of E amplifier configurations published thus far by simply imposing the proper design conditions.
Abstract: The authors describe the analysis of a more general class E amplifier configuration that can yield results for most of the other class E amplifier configurations published thus far by simply imposing the proper design conditions. The analysis takes into account most of the important parameters that affect the amplifier performance, such as the DC-feed inductance, the Q/sub L/ factor of the series-tuned circuit and the switching device ON resistance. Design and performance curves are given and discussed for the finite DC-feed inductance, shunt-capacitor, series-tuned configuration. It is seen that the amplifier performance is strongly affected by all of these parameters. Laboratory results show an excellent agreement between experimental values and theoretical predictions. >
TL;DR: In this article, a closed-form least-squares solution to the design problem of two-dimensional real zero-phase finite-impulse-response (FIR) filters with quadrantally symmetric or antisymmetric frequency response is obtained.
Abstract: A closed-form least-squares solution to the design problem of two-dimensional real zero-phase finite-impulse-response (FIR) filters with quadrantally symmetric or antisymmetric frequency response is obtained. An in-depth study of the matrices involved in the development of the design technique reveals a number of useful properties. It is shown that these properties lead to an optimal analytical solution for the filter coefficients, making it unnecessary to use the time-consuming methods of optimization, matrix inversion, and iteration. Because of the reduced order of the matrices involved, their specific characteristics, and the analytical approach, the computational complexity is greatly reduced. Simplicity and efficiency of the design technique is illustrated through examples. The results in terms of error in frequency response compare favorably with those obtained by using other techniques. It is shown that the design time using the proposed technique is significantly smaller than that required by the I/sub p/-optimization technique or weighted least-squares technique using Harris' ascent algorithm or modified Lawson's algorithm. >
TL;DR: In this article, a general theory based on an analysis of stationary points is presented for parallel and cascade realizations of adaptive infinite impulse response (IIR) filters and a parallel-form realization of adaptive IIR filters is introduced, and the behaviors of the recursive least-mean-square algorithm for this structure and for the direct form realization are compared.
Abstract: It is shown how different structures of an adaptive filter lead to a change in the characteristics of the corresponding error surface and, consequently, to a change in the corresponding convergence rate and minimum mean-square error. Alternate realizations of adaptive infinite impulse response (IIR) filters are presented, and some properties of their performance surfaces are found through mathematical analysis. A parallel-form realization of adaptive IIR filters is introduced, and the behaviors of the recursive least-mean-square algorithm for this structure and for the direct form realization are compared. A general theory based on an analysis of stationary points is presented. This general result is then specialized for parallel and cascade realizations. >
TL;DR: The center weighted Hadamard transform (CWHT) as mentioned in this paper is a transform that weights the region of mid-spatial frequencies of the signal more than the HT, which is similar to the HT in that it requires only real operations.
Abstract: The center weighted Hadamard transform (CWHT) is defined. This transform is similar to the Hadamard transforms (HT) in that it requires only real operations. The CWHT, however, weights the region of mid-spatial frequencies of the signal more than the HT. A simple factorization of the weighted Hadamard matrix is used to develop a fast algorithm for the CWHT. The matrix decomposition is of the form of the Kronecker products of fundamental Hadamard matrices and successively lower-order weighted Hadamard matrices. >