Showing papers in "IEEE Transactions on Circuits and Systems in 1991"

Synchronizing chaotic circuits

Abstract: The authors describe the conditions necessary for synchronizing a subsystem of one chaotic system with a separate chaotic system by sending a signal from the chaotic system to the subsystem. The general scheme for creating synchronizing systems is to take a nonlinear system, duplicate some subsystem of this system, and drive the duplicate and the original subsystem with signals from the unduplicated part. This is a generalization of driving or forcing a system. The process can be visualized with ordinary differential equations. The authors have build a simple circuit based on chaotic circuits described by R. W. Newcomb et al. (1983, 1986), and they use this circuit to demonstrate this chaotic synchronization. >

Center weighted median filters and their applications to image enhancement

Abstract: The center weighted median (CWM) filter, which is a weighted median filter giving more weight only to the central value of each window, is studied. This filter can preserve image details while suppressing additive white and/or impulsive-type noise. The statistical properties of the CWM filter are analyzed. It is shown that the CWM filter can outperform the median filter. Some relationships between CWM and other median-type filters, such as the Winsorizing smoother and the multistage median filter, are derived. In an attempt to improve the performance of CWM filters, an adaptive CWM (ACWM) filter having a space varying central weight is proposed. It is shown that the ACWM filter is an excellent detail preserving smoother that can suppress signal-dependent noise as well as signal-independent noise. >

Indeterminacy and identifiability of blind identification

Abstract: Blind identification of source signals is studied from both theoretical and algorithmic aspects. A mathematical structure is formulated from which the acceptable indeterminacy is represented by an equivalence relation. The concept of identifiability is then defined. Two identifiable cases are shown along with blind identification algorithms. The performance of FOBI (fourth-order blind identification), EFOBI (extended FOBI), and AMUSE algorithms is evaluated by some heuristic arguments and simulation results. It is shown that EFOBI outperforms the FOBI algorithm, and the AMUSE algorithm performs better than EFOBI in the case of nonwhite source signals. AMUSE is applied to a speech extraction problem and shown to have promising results. >

Fast algorithm and implementation of 2-D discrete cosine transform

Abstract: An algorithm for the fast computation of a 2-D discrete cosine transform (DCT) is presented. It is shown that the N*N DCT, where N=2/sup m/, can be computed using only N 1-D DCTs and additions, instead of using 2N 1-D DCTs as in the conventional row-column approach. Hence the total number of multiplications for the proposed algorithm is only half of that required for the row-column approach and is also less than that of most of other fast algorithms, whereas the number of additions is almost comparable to that of others. It is also shown that only N/2 1-D DCT module are required for hardware parallel implementation of the proposed algorithm. Thus the number of actual multipliers being used is only a quarter of that required for the conventional approach. >

The analysis and design of multidimensional FIR perfect reconstruction filter banks for arbitrary sampling lattices

Abstract: A general analysis of multidimensional multirate filter banks is presented. The approach is applicable to discrete signal spaces of any dimension, to multirate systems based on arbitrary downsampling and upsampling lattices, and for filter banks with any number of channels. A new numerical design procedure is also presented for multidimensional multirate perfect reconstruction filter banks, which is based on methods of nonlinearly constrained numerical optimization. An error function that depends only on the analysis filter impulse response coefficients is minimized, subject to a set of quadratic equality constraints that involve both the analysis and synthesis filter coefficients. With this design framework, it is possible to design a wide variety of filter banks that have a number of desirable properties. The analysis and synthesis filters that result are finite impulse response (FIR) and of equal size. In addition, both paraunitary and nonparaunitary filter banks can be designed with this method. Unlike paraunitary filter banks, nonparaunitary filter banks are capable of performing analysis bank functions more general than band-splitting with flat passband filters. >

FIR digital filters with least-squares stopbands subject to peak-gain constraints

Abstract: The use of digital filters with peak-constrained least weighted-squared errors (PCLWSE) is proposed. The emphasis is on PCLWSE filters with equiripple passbands and peak-constrained least-squares (PCLS) stopbands. The stopband energy is minimized subject to a constraint on the maximum stopband gain. A design algorithm is presented, and examples are discussed. Each example provides the unique optimal solution to the corresponding design problem. The tradeoff between the peak stopband gain and the total stopband energy is examined. It is shown that the most inefficient filters have minimax or least-squares stopbands. In particular, the stopband energy for minimax filters can be significantly reduced with almost no change in the peak stopband gain. Also, the peak stopband gain for filters with least-squares stopbands can be significantly reduced with almost no change in the total stopband energy. These results are supported by mathematical analysis, and examples are provided. >

A systematic approach for design of digit-serial signal processing architectures

Abstract: A systematic unfolding transformation technique for transforming bit-serial architecture into equivalent digit-serial ones is presented. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digit-serial architectures. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is referred to as the digit size; the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in past ad hoc designs). Digit-serial implementation of two's complement adders and multipliers is described. Least-significant-bit-first bit-serial implementation of two's complement division, square-root, and compare-select operations are presented, and the corresponding digit-serial architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiple-rate operations (such as interpolators and decimators) is also addressed. >

Systolic array implementation of multipliers for finite fields GF(2/sup m/)

Abstract: A parallel-in-parallel-out systolic array and a serial-in-serial-out systolic array are proposed for fast multiplication in finite fields GF(2/sup m/) with the standard basis representation. Both of the architectures possess features of regularity, modularity, concurrency, and unidirectional data flow. As a consequence, they have high throughput rates and are well suited to VLSI implementation with fault-tolerant design. As compared to the related multipliers presented by C.S. Yeh et al. (see IEEE Trans. Comput., vol.C-33, p.357-360, Apr. 1984), the proposed parallel implementation makes it easier to incorporate fault-tolerant design, and the proposed serial implementation requires only one control signal instead of two. >

On the representation of infinite-length distributed RC one-ports

Abstract: Representations of infinite distributed RC one-ports are described. Two functions are introduced: the dipole intensity function (as the generalization of pole-zero pattern) and the time-constant density (as the generalization of the discrete time-constant set of a lumped network). Relations between these representations and the complex impedance are presented. These representations can be regarded as the generalization of the descriptions commonly used in the theory of lumped networks. The representations offer possibilities for the identification and for the synthesis of distributed RC networks. Although the representations were introduced for the case of RC networks, the results can also be applied directly for inductance-resistance networks. The use of the new representations is demonstrated by some examples. >

Nonlinear P-I controller design for switchmode DC-to-DC power converters

Abstract: Extended linearization techniques are proposed for the design of nonlinear proportional-integral (P-I) controllers stabilizing, to a constant value, the average output voltage of pulsewidth modulation (PWM) switch-regulated DC-to-DC converters. The Ziegler-Nichols method is used for the P-I controller specification, as applied to a family of parametrized transfer function models of the linearized average converter behavior around a constant operating equilibrium point of the average PWM controlled circuit. The form in which the designed nonlinear P-I controllers are to be used in the actual discontinuous PWM feedback scheme is also indicated. The boost and the buck-boost converters are specifically treated, and the regulated performance is illustrated through computer simulation experiments. >

A CNN chip for connected component detection

Abstract: The first working chips that implement a cellular neural network (CNN) are reported. They have been integrated in a CMOS 2- mu m technology, and are intended for connected component detection processing applications. The operation is made in continuous time using analog circuitry. The design, fabrication, and testing of these chips are presented. >

A comparison of modulator networks for high-order oversampled Sigma Delta analog-to-digital converters

Abstract: After a discussion of the practical problem of comparing the relative performance of all known high-order modulator networks with respect to resolution, stability, input range, component sensitivities, finite amplifier gains, and bandwidths, equations are derived and verified by computer simulation that relate reduction in signal-to-noise ratio to component mismatch and finite amplifier gain, allowing designers to choose the best network for a particular application. A third-order, sigma-delta ( Sigma - Delta ) oversampled analog-to-digital (A/D) modulator network is presented. It shows improved performance in most respects over previous modulators. Although its theoretical performance in the absence of circuit nonidealities is below that of the triple first-order cascade network, when practical impairments such as finite amplifier gains and component mismatch are considered, it displays superior performance. Gain and offset errors are potentially lower for this network due to its ability to use a single capacitor for input signal and D/A feedback. A markedly reduced sensitivity to nonidealities for this network implies that monolithic circuits could be manufactured with better processing yields and hence lower unit costs. >

High-order absolutely stable neural networks

Abstract: The stability properties of arbitrary order continuous-time dynamic neural networks are studied in the spirit of an earlier analysis of a first-order system by M.A. Cohen and S. Grossberg (1983). The corresponding class of Lyapunov function is presented and the equilibrium points are characterized. The relationships with other continuous-time models are pointed out. >

Artificial neural networks for four-coloring map problems and K-colorability problems

Abstract: The computational energy required for solving a four-coloring map problem is determined. A parallel algorithm for solving the problem based on the McCulloch-Pits binary neuron model and the Hopfield neural network, is presented. It is shown that the computational energy is always guaranteed to monotonically decrease with the Newton equation. A 4*n neural array is used to color a map of n regions, where each neuron is a processing element that performs according to the proposed Newton equation. The capability of this system is demonstrated for a large number of simulation runs. The parallel algorithm is extended for solving the K-colorability problem. >

The effect of integrator leak in Sigma - Delta modulation

Abstract: A method is presented which makes it possible to determine exactly the effect of integrator leak on the performance of the single-loop Sigma - Delta modulator with DC input. Theory from the field of nonlinear dynamics is used to provide an analytical description of the behavior of the single-loop modulator with leaky integrators. Integrator leak is inevitable in any practical circuit implementation due to finite op-amp gain. The results obtained make it possible to discuss in quantitative rather than qualitative terms the robustness of the sigma-delta system to this circuit imperfection. >

The design of high dynamic range continuous-time integratable bandpass filters

Abstract: A method to design integratable continuous-time analog high-Q bandpass filters with a prescribed dynamic range is developed. The theory accompanying this method shows the fundamental restrictions for the dynamic range. The theory is meant to determine beforehand if the desired dynamic range is realizable. The possibilities of using dynamic range optimal filter networks are discussed. The usefulness of the theories is shown by the design of a complete bandpass filter, up to the transistor level. >

Continuous-time LMS adaptive recursive filters

Abstract: An approach for implementing continuous-time adaptive recursive filters is presented. The resulting filters should be capable of operating on much higher signal frequencies than their digital counterparts since no sampling is required. With respect to implementation problems, the effects of DC offsets are investigated and formulas derived so that these effects can be estimated and reduced. It is shown that the DC offset performance is strongly affected by the choice of structure for the adaptive filter. Experimental results from a discrete prototype are given where accurate adaption is observed and DC offset effects are compared to theoretical predictions. >

A chaotic attractor with cellular neural networks

Abstract: A chaotic attractor has been observed with a nonautonomous cellular neural network (CNN) using an opposite-sign template. The network consists of only two cells and is driven by a sinusoidal input. It possesses the horseshoe structure. The map shows multiple strongly stretching and folding processes of the volume of flow. The attractor has interesting fractal structures. >

Wirability of knock-knee layouts with 45 degrees wires

Abstract: The problem of wiring an arbitrary knock-knee layout (in a square grid with an arbitrary number of modules) in three and two layers using a small number of vias is investigated. A technique is proposed for transforming a knock-knee layout into a three-layer wirable layout by replacing knock-knees with 45 degrees wires. A 45 degrees replacing algorithm to achieve three-layer wirability is introduced. An efficient stretching technique to ensure two-layer wirability using 45 degrees wires is described. Conversion of an abstract layout into a corresponding physical layout is discussed. Experimental results are presented. >

A VLSI-efficient technique for generating multiple uncorrelated noise sources and its application to stochastic neural networks

Abstract: A method for generating multiple arbitrarily shifted pseudorandom bit streams from a single linear feedback shift register (LFSR) is presented. Each bit stream is obtained by tapping the outputs of selected LFSR cells and feeding these tapped cell outputs through a set of exclusive-OR gates. This enables many neurons to share a single LFSR, resulting in an acceptably small overhead for VLSI implementation. >

Pipelining in algorithms with quantizer loops

Abstract: High-speed implementation of signal processing algorithms for digital transmission is addressed. The internal feedback or recursion in these algorithms makes it difficult to implement recursive systems concurrently using either pipelining or parallelism. In the past, look-ahead computation techniques were successfully applied to create necessary concurrency in linear recursive and some nonlinear recursive operations (such as the add-compare-select operation). Novel computation approaches are proposed, and the look-ahead technique is extended to pipeline the feedback loops containing finite-level quantizers. Approaches to pipeline piecewise-linear recursive systems are presented. The proposed architectures are suitable for real-time high-speed implementation of quantizer loop operations where the levels of quantizer and the order of the loops are small. >

Stability of cellular neural networks with opposite-sign templates

Abstract: Cellular neural networks (CNNs) with opposite-sign templates have been successfully applied by T. Matsumoto et al. in connected component detection (CCD) in feature extraction (see ibid., vol.37, p.633-5, 1990). A stability analysis of this class of nonreciprocal CNN is provided by L.O. Chua et al. (see ibid., vol.37, p.1520-7, 1990). In this paper, a thorough stability analysis of this type of CNNs which shows the dependence of complete stability on the template values is presented. Parameter regions for complete stability and instability are determined, and the parameter region for the functionality of CCD is also given based on this investigation. Simulation examples verify that the complete stability of CNN with opposite-sign templates is not always preserved. >

Decomposition of binary integers into signed power-of-two terms

Abstract: Previous work has shown that approximation of digital filter coefficients using sums of signed power-of-two terms yields significant area/speed advantages in custom implementations, at the expense of a slight frequency response deterioration. The completeness, uniqueness, and resolving power of signed powers-of-two representations are studied, and circuits for extracting a prescribed number of signed power-of-two terms whose sum is the closest approximation to a given integer are presented. Examples of implementation of these circuits in a CMOS process are given. >

Wavelet construction using Lagrange halfband filters

Abstract: Using the approach described by M.J.T. Smith and T.P. Barnwell (1986) for obtaining exact-reconstruction filter banks, the authors present conjugate-quadrature and linear-phase solutions for two-channel filter banks using Lagrange halfband filters. It is shown that the wavelet solutions obtained by I. Daubechies (1988) under certain regularity conditions are the same as the conjugate-quadrature solutions derived from Lagrange halfband filters using the above approach. The linear-phase solution that is described provides filters with simple coefficients. >

An analytic method for designing simple cellular neural networks

Abstract: A method is proposed for synthesizing cellular neural networks (CNNs) designed for simple applications. Based on the comparison principle for ordinary differential equations, this method leads to a set of inequalities that must be satisfied by the parameters of the cloning template defining the cellular neural network in order to guarantee correct operation for the network. The authors review the architecture of CNNs, compute the bounds of the state and output of a cell, and illustrate how to use this technique to design CNNs for shadowing, motion detection, and hole filling. >

Simulation of arbitrary transmission line networks with nonlinear terminations

Abstract: The transient response of a high-speed digital circuit is determined by the interaction of a lossy distributed transmission line network and lumped nonlinear circuits. A robust and accurate method for the analysis of such a system is reported, and its implementation in an analog circuit simulator is discussed. The method uses a convolution technique and a time-domain impulse response to perform a transient simulation of a transmission line network. The time-domain impulse response is derived using a Fourier transform of modified frequency-domain scattering parameters. Implementation of the technique is verified by comparison with measured results. >

Improved compensation for analog-to-digital converters

Abstract: Two changes are recommended for procedures used in building two-dimensional state-space error correction tables to compensate high-speed analog-to-digital converters (ADCs). The modifications require three frequencies to calibrate all states as well as extrapolation of estimated outputs to achieve a straight line input-output integral characteristic for the ADC. A simulated 6-bit ADC with only 35-dBc spurious free signal range is shown to be correctable to 53 dB over 80% of the Nyquist band when suggested changes are used to calibrate the ADC. >

Synthesis of averaged circuit models for switched power converters

Abstract: An approach for synthesizing averaged circuit models for switching converters that realize their respective state-space averaged models is presented. The method proceeds in a systematic fashion by determining appropriate averaged circuit elements that are consistent with the averaged circuit waveforms. The averaged circuit models that are obtained are syntheses of the state-space averaged models for the underlying switched circuits. An important feature of the method is that it is applicable to switched circuits whose non-switch elements may be nonlinear. This approach is compared and contrasted with the results on averaged circuit models available in the literature. >

Efficient VLSI designs for data transformation of tree-based codes

Abstract: A class of VLSI architectures for data transformation of tree-based codes is proposed, concentrating on transformation functions used for data compression and decompression. Two algorithms are presented: a sequential algorithm that generates the code bits serially one bit per machine cycle, and a parallel algorithm that generates the entire code bits of a symbol in one machine cycle. The algorithms use the principle of propagation of a token in a reverse binary tree constructed from the original codes. The design approaches are applicable to any binary codes, although the static Huffman code is used as an illustration. A hardware algorithm for generating adaptive Huffman codes is proposed, and a VLSI architecture for implementing the algorithm is described. The high speed of the algorithms ensures that data transformation is done on the fly, as data are being transferred from/to high-speed I/O communication devices. >

Neural network architecture for crossbar switch control

Abstract: A Hopfield neural network architecture for the real-time control of a crossbar switch for switching pockets at maximum throughput is proposed. The network performance and processing time are derived from a numerical simulation of the transitions of the neural network. A method is proposed to optimize electronic component parameters and synaptic connections, and it is fully illustrated by the computer simulation of a VLSI implementation of 4*4 neural net controller. The extension to larger size crossbars is demonstrated through the simulation of an 8*8 crossbar switch controller, where the performance of the neural computation is discussed in relation to electronic noise and inhomogeneities of network components. >