Showing papers in "IEEE Transactions on Circuits and Systems in 2005"

A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback

Abstract: This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (/spl Sigma//spl Delta/) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous-time feedback digital-analog converter (DAC). The reduced sensitivity to jitter is both simulated and proven by measured results from two implemented third-order modulators. Additionally, the nonideal behavior is analyzed analytically and by simulations.

Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method

Abstract: In this paper, three generic RAM-based architectures are proposed to efficiently construct the corresponding two-dimensional architectures by use of the line-based method for any given hardware architecture of one-dimensional (1-D) wavelet filters, including conventional convolution-based and lifting-based architectures. An exhaustive analysis of two-dimensional architectures for discrete wavelet transform in the system view is also given. The first proposed architecture is for 1-level decomposition, which is presented by introducing the categories of internal line buffers, the strategy of optimizing the line buffer size, and the method of integrating any 1-D wavelet filter. The other two proposed architectures are for multi-level decomposition. One applies the recursive pyramid algorithm directly to the proposed 1-level architecture, and the other one combines the two previously proposed architectures to increase the hardware utilization. According to the comparison results, the proposed architecture outperforms previous architectures in the aspects of line buffer size, hardware cost, hardware utilization, and flexibility.

Prediction of chaotic behavior

Abstract: This paper considers the prediction of chaotic behavior using a master-slave synchronization scheme. Based on the stability theory for retarded systems using a Lyapunov-Krasovskii functional, we derive a sufficient condition for perfect state prediction of the master system via a time-delayed output signal of the slave system. The obtained result is based on the delay-dependent stability of time-delay systems. In addition, we derive an upper bound of the admissible time delay by using linear matrix inequality techniques. Finally, we show the effectiveness of the proposed predictor by two numerical examples.

A rail-to-rail amplifier input stage with ±0.35%g m fluctuation.

Abstract: A new scheme for achieving rail-to-rail input to an amplifier is introduced. Constant is obtained by using tunable level shifters and a single differential pair. Feedback circuitry con- trols the level shifters in a manner that fixes the common-mode input of the differential pair, resulting in consistent and stable oper- ation for rail-to-rail inputs. As the new technique avoids using com- plimentary input differential pairs, this method overcomes prob- lems such as common-mode rejection ratio and gain-bandwidth product degradation that exist in many other designs. The circuit was fabricated in 0.5- m process. The resulting differential pair had a constant transconductance that varied by only 0.35 for rail-to-rail input common-mode levels. The input common-mode range extended well past the supply levels of 1.5 V, resulting in only 1 fluctuation in for input common modes from to 2V.

Analysis of the Σ-Δ pulsed digital oscillator for MEMS.

Abstract: The aim of this paper is the analysis, simulation, and experimental verification of the - pulsed digital oscillator (PDO) topology. As it has been shown in previous works, the oscillation frequency and output spectrum in the PDO depend on the sampling frequency, the natural frequency of the micror- electromechanical systems (MEMS) resonator and its damping factor. Here, extensive discrete-time simulations have been carried out which show that the normalized oscillation frequency as a function of the normalized natural frequency of the resonator is very similar to a distorted Devil's Staircase fractal. This nonlinear behavior is a direct consequence of the damping losses of the MEMS resonator. Analytical conditions for a perfect oscillation at the natural frequency of the resonator are also calculated. For this set of what we call "perfect" frequencies, it is also shown that the energy transfer from the electrical to the mechanical domain is maximum. Then a more generalized structure of the oscillator is considered and the drawn conclusions are tested against experi- mental results obtained from an oscillator prototype which uses a MEMS resonator with thermoelectric actuation and piezoresistive position sensing.

A log-domain /spl mu/beamformer for medical ultrasound imaging systems

Abstract: A fully differential, Class-AB, log domain microbeamformer has been designed in a 60 GHz Si-Ge BiCMOS process The demonstrated microbeamformer has four input channels and four delays, though the concept can easily be extended to any desirable configuration The log domain, Class-AB architecture is perfect for medical ultrasound applications due to the fact that the received ultrasound signal has very low amplitude during the major part of the reception period This leads to very low power consumption because of the Class-AB configuration The delay-line in the microbeamformer is constructed using a cascade of low input impedance allpass filter cells A simple implementation of the zero in the allpass filter helps to keep the overall power consumption low The delay of each allpass filter cell is programmable through the adjustment of a tuning current Due to the Class-AB architecture used, every source signal must be shaped by a signal preconditioning circuit before connected to the filter cells A well-known preconditioning circuit has been modified to increase the dynamic range The modification introduces noise cancellation as well as a method to increases the maximum signal swing The dynamic range of one preconditioning cell is shown to increase 126 dB compared to the classic translinear circuit at a penalty of 15% increase in the power consumption Signal-to-noise ratio of one allpass filter cell is typically 565 dB, and the global dynamic range of the same cell is typically 638 dB at an average power consumption of 35 mW when 16 input signals are connected to the filter The power consumption at maximum signal amplitude for the microbeamformer having four input channels and four delays is 32 mW with a supply voltage of 25 V In the intended application, the quiescent power consumption is a much better description of the average power consumption This power consumption is 13 mW

An 11b 70-MHz 1.2-mm^2 49-mW 0.18-μm CMOS ADC with on-chip current/voltage references

Abstract: This work proposes an 11b 70MHz CMOS pipelined A/D converter (ADC) as one of core circuit blocks for high-speed VDSL system applications. The proposed ADC for the internal use has the strictly limited number of externally connected I/O pins while the ADC employs on-chip CMOS current/voltage (I/V) references and a merged-capacitor switching (MCS) technique to improve ADC performances. The ADC implemented in a 0.18µm n-well single-poly quad-metal CMOS technology shows the maximum SNDR of 60 dB at 70 MSample/s. The ADC maintains the SNDR of 58 dB and the SFDR of 68 dB for input frequencies up to the Nyquist rate at 60 MSample/s. The measured DNL and INL of the ADC are within ±0.63 and ±1.21 LSB, respectively. The active chip area is 1.2 mm2and the ADC consumes 49 mW at 70 MSample/s at a 1.8 V supply.

Design of double-sampling ΣΔ modulation A/D converters with bilinear integrators.

Abstract: Double-sampling techniques allow to double the sampling frequency of a switched capacitor analog-to-digital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator's performance. The fully floating double-sampling integrator is an interesting building block to be used in such a double sampling modulator be- cause its operation is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect. This effectively increases the order of the modulator by one. Due to this, previously presented structures don't have enough freedom to fully control the modulator pole positions. In this paper, we introduce mod- ified topologies for double-sampling modulators built with bilinear integrators. We show that these architectures provide full control of the modulator pole positions and hence can be used to implement any noise transfer function. Additionally, analytical expressions are obtained for the residual folded noise. Index Terms—Analog-to-digital convertors, double sampling, modulation.

Continuous-time ΔΣ modulators using distributed resonators.

Abstract: We derive a method for using distributed resonators in modulators and demonstrate these modulators have several advantages over existing modulator architectures. Like continuous-time (CT) modulators, the proposed modulators do not require a high-precision track-and-hold, and additionally can take advantage of the high- of distributed resonators. Like discrete-time modulators, the proposed modulators are relatively insensitive to feedback loop delays and can subsample. We present simulations of several types of these modulators and examine the challenges in their design.

A novel noise efficient feedback DAC within a switched capacitor ΣΔ ADC.

Abstract: Efficient sampling of the reference noise within a bi- linear switched capacitor analog-to-digital converter (ADC), resulting in improved thermal noise performance is presented. Bi- linear integrators contain a zero at the Nyquist frequency, with the result that no charge is transferred from the reference when a tran- sition occurs in the modulator output. The average noise power added by the reference digital-to-analog converter (DAC) can be reduced substantially if the reference DAC is sampled only when charge is to be transferred. For midscale inputs, the sampled noise from a single bit reference DAC is reduced by more than 5 dB. When multibit quantization and feedback is used the reference noise can be further suppressed, in the case of 5 bits of feedback the reference noise is reduced by more than 20 dB.